Xilinx Virtex-5 Field Programmable Gate Array Research Articles

RDCSAE-RKRVFLN: A unified deep learning framework for robust and accurate DOA estimation

This paper introduces an innovative unified deep learning (DL) model, “reduced deep convolutional stack autoencoder (RDCSAE)-robust kernel-based random vector functional link network (RKRVFLN)” (RDCSAE-RKRVFLN), for addressing practical challenges like phase and gain uncertainty, mutual coupling effects, and element position errors in direction of arrival (DOA) estimation. The RDCSAE utilizes deep convolutional neural network (DCNN) and stack autoencoder (SAE) for robust feature extraction. The RKRVFLN integrates a concise SAE output with kernel-based learning. Thus, the integration of RDCSAE (suitable for unsupervised feature extraction) and RKRVFLN (for supervised learning) in the developed model results in efficient use of limited training data. Performance metrics of this method include among others the accuracy (separation between sources), root mean square error (RMSE), signal-to-noise ratio (SNR), etc. The method performs better than existing data driven methods in terms of computational efficiency, faster learning speed, enhanced model generalization, higher accuracy, and shorter event regression time and empirical methods. In the presence of above mentioned four perturbations, this method successfully resolves multiple sources with a resolution of 0.3° with a RMSE of 0.00376. For real time application, the paper implements RDCSAE-RKRVFLN on a high-speed reconfigurable Xilinx Virtex-5 field-programmable gate array (FPGA) realizing a digital DOA estimator for one source. The hardware estimates the DOA with a maximum error of 0.01953125 which follows closely the simulation results indicating the efficiency and feasibility of the method.

Resource-aware Montgomery modular multiplication optimization for digital signal processing

Homomorphic encryption is an important technology for protecting data privacy, and the performance of modular multiplication directly affects the efficiency of homomorphic encryption. Currently, there are numerous FPGA-based acceleration techniques targeting modular multiplication. However, many of these implementations require substantial hardware resources or suffer from resource imbalance. This leads to a lower throughput. Therefore, we present a novel FPGA-based implementation of Montgomery Modular Multiplication aimed at addressing these challenges. Our design employs a suitable radix bit width and word size based on the digital signal processing (DSP) bit width rather than the conventional binary powers of two. We aim to instantiate more modular multipliers using limited resources while minimizing latency. We also introduce a novel DSP cascade structure, called parallel grouping cascade DSP, which reduces the number of clock cycles of internal multipliers. To balance the ratio of lookup table (LUT) and DSP usage, we also use multipliers implemented in the LUT to replace some DSPs. Our results, implemented on Xilinx Virtex-7 field-programmable gate array (FPGA), demonstrate more than 27% improvement in throughput on 1024-bit modular multiplication and more than 70% improvement on 2048-bit compared to the best previous state-of-the-art references.

A Flexible Hardware Accelerator for Booth Polynomial Multiplier

This article presents a parameterized/flexible hardware accelerator design tailored for the Booth polynomial multiplication method. The flexibility is achieved by allowing users to compute multiplication operations across various operand lengths, reaching up to 212 or 4096 bits. Our optimization strategy involves resource reuse, effectively minimizing the overall area cost of the Booth accelerator design. A comprehensive evaluation compares the proposed multiplier design with several non-digitized bit-serial polynomial multiplication accelerators. Implementation is realized in Verilog HDL using the Vivado IDE tool, featuring diverse operand sizes, and post-place and route assessments are performed on the Xilinx Virtex-7 field-programmable gate array device. For the largest considered operand size of 1024 × 1024, our Booth accelerator utilizes 1434 slices and can operate on a maximum frequency of 523.56 MHz. A single polynomial multiplication operation requires 0.977 μs and the total power consumption is 927 mW. Moreover, a comparison to state-of-the-art accelerators reveals that the proposed flexible accelerator is 1.34× faster in computation time and 1.05× more area-efficient than the recent dedicated polynomial multiplication design. Therefore, the implementation results and comparison to the state of the art show that the proposed accelerator is suitable for a wide range of cryptographic applications.

FPGA implementation of DTCWT architecture's high-speed DA structure for OFDM-based transceiver with CS

Communication systems at millimeter-wave (mm-wave) frequencies with high propagation losses use radio frequency (RF) budget analysis. RF system gains and losses ensure the receiver can recover the broadcast signal. Modern communication systems use compressive sensing (CS) and discrete wavelet transform (DWT). Hardware implementation is hard. Fieldprogrammable gate arrays (FPGA) adaptability, configurability, and processing speed make them popular. More mm-wave transceivers use FPGAs and advanced signal processing. FPGA-based mm-wave transceivers use compressed sensing and dual-tree complex wavelet transform (DTCWT). RF budget analysis recovers receiver signals. Energy and data efficiency transceivers have baseband processors, transmitters, and receivers. RF-to-mm-wave transmitter. Receiver demodulation and baseband conversion. CS and DTCWT processing modules boost baseband signal processing 5 Gbps Xilinx virtex-6 FPGAs. The system retrieves the signal while conserving power, according to simulations and testing. This study found that FPGA-based mm-wave transceivers can use advanced signal processing in future high-speed communication systems.

An Optimized Flexible Accelerator for Elliptic Curve Point Multiplication over NIST Binary Fields

This article proposes a flexible hardware accelerator optimized from a throughput and area point of view for the computationally intensive part of elliptic curve cryptography. The target binary fields, defined by the National Institute of Standards and Technology, are GF(2163), GF(2233), GF(2283), GF(2409), and GF(2571). For the optimization of throughput, the proposed accelerator employs a digit-parallel multiplier. The size of the digit is 41 bits. The proposed accelerator has reused the multiplication and squaring circuit for area optimization to compute modular inversions. Flexibility is included using three additional buffers on top of the proposed accelerator architecture to load different input parameters. Finally, a dedicated controller is used to optimize control signal handling. The architecture is modeled using Verilog and implemented up to the post-place-and-route level on a Xilinx Virtex-7 field-programmable gate array. The area utilization of our accelerator in slices is 1479, 1998, 2573, 3271, and 4469 for m=163 to 571. The time needed to perform one-point multiplication is 7.15, 10.60, 13.26, 20.96, and 30.42 μs. Similarly, the throughput over area figures for the same key lengths are 94.56, 47.21, 29.30, 14.58, and 7.35. Consequently, achieved results and a comprehensive performance comparison show the suitability of the proposed design for constrained environments that demand throughput/area-efficient implementations.

A Coprocessor Architecture for 80/112-bit Security Related Applications

We have proposed a flexible coprocessor key-authentication architecture for 80/112-bit security-related applications over field by employing Elliptic-curve Diffie Hellman (ECDH) protocol. Towards flexibility, a serial input/output interface is used to load/produce secret, public, and shared keys sequentially. Moreover, to reduce the hardware resources and to achieve a reasonable time for cryptographic computations, we have proposed a finite field digit-serial multiplier architecture using combined shift and accumulate techniques. Furthermore, two finite-state-machine controllers are used to perform efficient control functionalities. The proposed coprocessor architecture over and is programmed using Verilog and then implemented on Xilinx Virtex-7 FPGA (field-programmable-gate-array) device. For and , the proposed flexible coprocessor use 1351 and 1789 slices, the achieved clock frequency is 250 and 235 MHz, time for one public key computation is 40.50 and 79.20 μs and time for one shared key generation is 81.00 and 158.40 μs. Similarly, the consumed power over and is 0.91 and 1.37 mW, respectively. The proposed coprocessor architecture outperforms state-of-the-art ECDH designs in terms of hardware resources.

FPGA-Based Implementation of Multidimensional Reconciliation Encoding in Quantum Key Distribution.

We propose a multidimensional reconciliation encoding algorithm based on a field-programmable gate array (FPGA) with variable data throughput that enables quantum key distribution (QKD) systems to be adapted to different throughput requirements. Using the circulatory structure, data flow in the most complex pipeline operation in the same time interval, which enables the structural multiplexing of the algorithm. We handle the calculation and storage of eight-dimensional matrices cleverly to conserve resources and increase data processing speed. In order to obtain the syndrome more efficiently, we designed a simplified algorithm according to the characteristics of the FPGA and parity-check matrix, which omits the unnecessary operation of matrix multiplication. The simplified algorithm could adapt to different rates. We validated the feasibility and high speed of the algorithm by implementing the multidimensional reconciliation encoding algorithm on a Xilinx Virtex-7 FPGA. Our simulation results show that the maximum throughput could reach 4.88 M symbols/s.

Hardware Implementation of a High Efficiency and High-Speed Squaring Architecture

This paper presents the design of a high speed and simple squaring structure based on half adder and full adder. The proposed architecture consists of three main steps; simplification of the squaring structure, calculation and transferring of the carry bit to the next part, and finally, applying the modified Wallace Tree Adder to calculate the summation of the products. The proposed squaring architecture is formed only by 13 half adders and 20 full adders for 8-bit squaring which has the lowest complexity compared to other works. The proposed structure is modeled by using Field-Programmable Gate Array (FPGA) and has been successfully synthesized and implemented with Xilinx Spartan-6 and Virtex-4 FPGA. Simulation results show that the proposed structure has high speed and excellent performance with low power consumption while having the lowest propagation delay (3.25 ns) and acceptable hardware utilization compared to existing squaring models. The gate-level design of 8-bit squaring is implemented using Cadence layout tools in 65 nm CMOS technology which has a total area of 0.095 mm2.

A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication

The ring learning with error (RLWE)-based fully homomorphic encryption (FHE) scheme has become one of the most promising FHE schemes. However, its performance is limited by the homomorphic multiplication, especially the polynomial multiplication which occupies major computing resources. Therefore, efficient implementation of polynomial multiplication is crucial for high-performance FHE applications. In this article, we present an area-efficient and highly unified reconfigurable multicore number theoretic transform (NTT)/inverse NTT (INTT) architecture (named MCNA), which employs NTT and INTT for polynomial multiplier with a variable number of reconfigurable processing elements. To reduce latency, MCNA merges the preprocessing and postprocessing into the constant-geometry NTT and INTT, respectively. Also, a reconfigurable modular multiplier based on digital signal processor (DSP) is proposed to speed up the modular multiplication. In order to avoid designing independent memory access pattern for INTT, a unified read/write structure of NTT/INTT is presented. Furthermore, a novel memory access pattern named “cyclic-sharing” is proposed to reduce 25% memory capacity. MCNA is evaluated on a Xilinx Virtex-7 field-programmable gate array (FPGA) platform. Running at 250-MHz clock frequency, the throughput of MCNA for NTT/INTT achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.78\times \sim 9.32\times $ </tex-math></inline-formula> improvements in comparison to prior works, while the area efficiency of lookup table (LUT) and flip-flop (FF) is improved by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.25\times \sim 4.79\times $ </tex-math></inline-formula> . For polynomial multiplication, the throughput of MCNA achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.73\times \sim 7.69\times $ </tex-math></inline-formula> enhancements, as well as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.13\times \sim 14.8\times $ </tex-math></inline-formula> area efficiency improvements.

A reconfigurable PUF structure with dual working modes based on entropy separation model

Privacy Protection Mutual Authentication (PPMA) in the Internet of Things uses physical unclonable functions (PUFs) and true random number generators (TRNGs) as security primitives, providing a lightweight solution for key generation and protection. At present, the designs for achieving PUF and TRNG simultaneously on field programmable gate array (FPGA) lack theoretical support, and have poor randomness and stability. Therefore, this paper provides a separation model of PUF entropy (manufacturing delay) and TRNG entropy (jitter delay) based on ring oscillators (ROs). Based on this model, a reconfigurable PUF structure is proposed, which can be reconstructed to a TRNG by changing the working mode. The proposed structure not only improves the area utilization, but also realizes the low-power consumption. Experiments on Xilinx Spartan-6 FPGAs and Xilinx Virtex-6 FPGAs show that the proposed structure has wonderful performance. The PUF has excellent uniqueness (average resolution is 50.21%) and reliability (the average repeatability rate is 96.98%). TRNG's output sequences have high randomness and pass all National Institute of Standards and Technology (NIST) tests (average pass rate is 99%).

An Efficient Crypto Processor Architecture for Side-Channel Resistant Binary Huff Curves on FPGA

This article presents an efficient crypto processor architecture for point multiplication acceleration of side-channel secured Binary Huff Curves (BHC) on FPGA (field-programmable gate array) over GF(2233). We have implemented six finite field polynomial multiplication architectures, i.e., (1) schoolbook, (2) hybrid Karatsuba, (3) 2-way-karatsuba, (4) 3-way-toom-cook, (5) 4-way-toom-cook and (6) digit-parallel-least-significant. For performance evaluation, each implemented polynomial multiplier is integrated with the proposed BHC architecture. Verilog HDL is used for the implementation of all the polynomial multipliers. Moreover, the Xilinx ISE design suite tool is employed as an underlying simulation platform. The implementation results are presented on Xilinx Virtex-6 FPGA devices. The achieved results show that the integration of a hybrid Karatsuba multiplier with the proposed BHC architecture results in lower hardware resources. Similarly, the use of a least-significant-digit-parallel multiplier in the proposed design results in high-speed (in terms of both clock frequency and latency). Consequently, the proposed BHC architecture, integrated with a least-significant-digit-parallel multiplier, is 1.42 times faster and utilizes 1.80 times lower FPGA slices when compared to the most recent BHC accelerator architectures.

Design of True Random Number Generator Based on Multi-Stage Feedback Ring Oscillator

True random number generators (TRNGs) play an important role in encryption systems. In this brief, a novel method of generating true random numbers on a field-programmable gate array (FPGA) is proposed based on the random jitter of a multi-stage feedback ring oscillator (MSFRO) as the entropy source. Based on the traditional ring oscillator, a multi-stage feedback structure is added to enlarge the range of clock jitter, and improve the frequency of clock sampling and the randomness of the entropy source. Different from the traditional clock sampling structure, we use the clock jitter signal generated by the MSFRO to sample the clock signal generated by the phase-locked loop (PLL) of the FPGA. The obtained output value is operated by XOR to reduce the deviation of the output value and improve its randomness. The TRNG is implemented in Xilinx Virtex-6 FPGA, which has low hardware resource consumption and high throughput. The entropy source classification, hardware resources and throughput are compared with those of existing TRNGs. The results showed that the proposed TRNG only consumed 24 LUTs and 2 DFFs. Compared with other TRNGs, this design has very low hardware resource consumption and its throughput is up to 290 Mbps. The random bit sequence generated by this TRNG passes the NIST SP800-22 test and the NIST SP800-90B test.

FPGA Implementation of Elliptic-Curve Diffie Hellman Protocol

This paper presents an efficient crypto processor architecture for key agreement using ECDH (Elliptic-curve Diffie Hellman) protocol over . The composition of our key-agreement architecture is expressed in consisting of the following: (i) Elliptic-curve Point Multiplication architecture for public key generation (DESIGN-I) and (ii) integration of DESIGN-I with two additional routing multiplexers and a controller for shared key generation (DESIGN-II). The arithmetic operators used in DESIGN-I and DESIGN-II contain an adder, squarer, a multiplier and inversion. A simple shift and add multiplication method is employed to retain lower hardware resources. Moreover, an essential inversion operation is operated using the Itoh-Tsujii algorithm with similar hardware resources of used squarer and multiplier units. The proposed architecture is implemented in a Verilog HDL. The implementation results are given on a Xilinx Virtex-7 FPGA (field-programmable gate array) device. For DESIGN-I and DESIGN-II over , (i) the utilized Slices are 3983 and 4037, (ii) the time to compute one public key and a shared secret is 553.7 μs and 1170.7 μs and (iii) the consumed power is 29 μW and 57 μW. Consequently, the achieved area optimized and power reduced results show that the proposed ECDH architecture is a suitable alternative (to generate a shared secret) for the applications that require low hardware resources and power consumption.

Medical Image Demosaicing Based Design of Newton Gregory Interpolation Algorithm

In this paper, Field-Programmable Gate Array (FPGA) implementation-based image demosaicing is carried out. The Newton Gregory interpolation algorithm is designed based on FPGA frame work. Interpolation is the method of assessing the value of a function for any in-between value of self-regulating variable, whereas the method of computing the value of the function outside the specified range is named extrapolation. The natural images are collected from Kodak image database and medical images are collected from UPOL (University of Phoenix Online) database. The proposed algorithm is executed on using Xilinx ISE (Integrated Synthesis Environment) Design Suite 14.2 and is confirmed on Xilinx Virtex-5 FPGA board. The main aim of this paper is to develop a demosaicing method based on the FPGA technique. Implementing image processing on hardware reduces the cost and make simpler for debugging and verification. The hardware implementation in this system gives the better quality of output image. Implementing image processing on hardware reduces the cost and makes simpler for debugging and verification. Newton- Gregory interpolation technique produces the full resolution of green channel with red and blue channels. The experimental result clearly shows that proposed Newton-Gregory interpolation-based image demosaicing outperformed other algorithms. FPGA implementation attains the maximum Peak Signal-To-Noise Ratio (PSNR) of 40.53 dB and MATLAB (Matrix Laboratory<b>)</b>. implementation attains the maximum PSNR of 38.15 dB.

FPGA Hardware in the Loop Validation of Asynchronous Machine with Full Direct Torque Control Implementation

This article provides a full hardware implementation for direct torque control (DTC) of an asynchronous motor (AM) on the Field Programmable Gate Array (FPGA). Due to its high processing frequency, the FPGA circuit presents an alternative for achieving a high performance DTC implementation. This cannot be achieved by any DSP or microcontroller application. The proposed hardware architecture implements three components of DTC control strategy (the integral proportional speed regulator, the estimation and the switching blocks). This implementation has the advantage of being faster, more efficient and with minimum hardware resources on the target FPGA board. The hardware architecture of the DTC control was designed and simulated in Matlab / Simulink using XSG blocks, then synthesized with the Xilinx ISE 14.2 tool, implemented and validated on the Xilinx Virtex-4 FPGA circuit by Hardware in the Loop process.

A digital direction of arrival estimator based on fast on-line sequential random vector functional link network

This article develops a fast online sequential random vector functional network. In this network, input nodes are connected to both hidden nodes and output nodes. This architecture results in high-speed learning and testing. The network estimates the direction of arrival from signals received by the sparse array in real-time. Neither noisy signal nor effect of mutual coupling among array elements affect the estimation appreciably using the network. The network shows competitive performance in terms of learning speed, accuracy, short event regression time, simplicity, and robustness in comparison to other state-of-the-art methods such as support vector regression, extreme learning machine, and online sequential extreme learning machine. Finally, validation of the network translation into a hardware platform using a fast digital high-speed reconfigurable Xilinx Virtex-5 field-programmable gate array embedded processor for single-source detection completes the work. Comparison with reported measurement shows results with good accuracy and low root mean square error both by the network and its hardware-implemented platform. The direction of arrival estimation is thus possible using the network either through a computer or dedicated hardware as per necessity.

Accelerated Updating Mechanisms for FPGA-Based Ternary Content-Addressable Memory

Field-programmable gate array (FPGA)-based ternary content-addressable memories (TCAMs) are constantly evolving in terms of hardware, power consumption, and speed. One disadvantage of these emulated TCAMs is its poor update-latency. Traditional FPGA-based TCAMs have an update-latency of N clock cycles compared to the lookup-latency of one clock cycle, where N is the depth of TCAM. Later, the update-latency is improved to t clock cycles, where t is the number of don't care bits. In this letter, we presented two mechanisms for updating FPGA-based TCAM and successfully implemented on Xilinx Virtex-6 FPGA: an accelerated MUX-Update mechanism and a cost-effective LUT-Update mechanism. MUX-Update provides an update-latency of W+1 clock cycles by using only three input/output (I/O) pins, whereas W is the width of TCAM. LUT-Update yields a constant update-latency of 2 clock cycles, independent of the size of TCAM, by using W I/O pins.

ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture

In this article, we propose a novel data detection algorithm and a corresponding VLSI design for massive multiuser (MU) multiple-input-multiple-output (MIMO) wireless systems. Our algorithm uses alternating direction method of multipliers (ADMM)-based infinity-norm-constrained equalization and is called ADMIN. ADMIN is an iterative algorithm that outperforms linear detectors by a large margin when the ratio between the numbers of base-station (BS) and user antennas is small. In the first iteration, ADMIN computes the linear minimum mean-square error (MMSE) solution, which is sufficient when the ratio between the numbers of BS and user antennas is large. We develop time-shared and iterative VLSI architectures for LDL-decomposition-based soft-output ADMIN supporting 16- and 32-user systems. We present application-specific integrated circuit (ASIC) designs for 16-64 antenna base stations in 28-nm CMOS that supports up to 64 quadrature amplitude modulation (QAM). The 16-user ADMIN ASIC achieves 303 Mb/s while dissipating 85 mW. The 32-user ADMIN ASIC achieves 287 and 241 Mb/s while dissipating 121 and 135 mW for 32 and 64 BS antennas, respectively. ADMIN has also been implemented on a Xilinx Virtex-7 field-programmable gate array (FPGA) and is compared with state-of-the-art massive MIMO data detectors.

Innovative Dual-Binary-Field Architecture for Point Multiplication of Elliptic Curve Cryptography

High-performance Elliptic Curve Cryptography (ECC) implementation in encryption authentication severs has become a challenge due to the explosive growth of e-commerce’s demand for speed and security. Point multiplication (PM) is the most common and complex operation in ECC which directly determines the performance of the whole system. This article proposes a 6CC-6CC (clock cycle) dual-field PM architecture and a 6CC-4CC dual-field PM architecture based on maximizing utilization of Karatsuba multipliers and re-ordering schedule strategy in PM. The Montgomery Ladder algorithm used in PM is modified to a 4CC algorithm for better resource utilization and parallel computation. To solve the frequency drop problem while working on large finite field, the PM architectures for high and low field are carefully studied to have universal critical path length and balanced performance. Both of the architectures are implemented over GF(2571) and GF(2283) on Xilinx Virtex-5 and Virtex-7 FPGAs (Field-Programmable Gate Array) for comparison. The 6CC-6CC architecture is shown to have the best performance on GF(2571), which achieves one PM operation in $17.44~\mu s$ using 81549 LUTs (Look-Up-Table) with the frequency of 197.2 MHz on Virtex-5, and $12.55~\mu s$ using 80970 LUTs with the frequency of 274.1 MHz on Virtex-7. The 6CC-4CC architecture performs better on GF(2283) with the shortest computation time. It takes only $3.21~\mu s$ to finish one PM operation on Virtex-5 and $2.22~\mu s$ on Virtex-7, which are faster than all the previous designs. The implementation results prove that the proposed architectures have state-of-the-art performance as well as higher versatility for ECC designs.

Design and Implementation of Enhanced PUF Architecture onFPGA

ABSTRACT Physical un-clonable functions (PUF) play important role in hardware security due to its random response generation. It offers a wide range of security applications, such as key generation, digital rights management, and Field Programmable Gate Array (FPGA) intellectual property (IP) protection. In literature, several PUF structures of both Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) are used to improve the performance parameter, mainly reliability and uniqueness. Because of the large number of challenges and responses pairs (CRPS), Arbiter PUF (APUF) is widely used but suffers from less reliability and uniqueness. The proposed PUF structure is designed to achieve the ideal value of performance metrics and also to reduce the prediction rate. This paper presents a new approach to design Double Feed-Forward XOR Arbiter PUF (DFFX APUF), is a combination of Feed-Forward Arbiter PUF, the output of this combination is XORed to generate the single response. Newly proposed PUF is implemented on Xilinx Virtex-6 FPGA. The reliability and uniqueness are the parameters to evaluate the performance of the DFFX APUF and is compared with the Feed-Froward APUF and Double-APUF. The proposed PUF architecture results, the uniqueness of 5% and reliability of 8% greater than FF-APUF and Double-APUF.