Xeon Phi Coprocessor Research Articles

Performance Evaluation of Massively Parallel Systems Using SPEC OMP Suite

Performance analysis plays an essential role in achieving a scalable performance of applications on massively parallel supercomputers equipped with thousands of processors. This paper is an empirical investigation to study, in depth, the performance of two of the most common High-Performance Computing architectures in the world. IBM has developed three generations of Blue Gene supercomputers—Blue Gene/L, P, and Q—that use, at a large scale, low-power processors to achieve high performance. Better CPU core efficiency has been empowered by a higher level of integration to gain more parallelism per processing element. On the other hand, the Intel Xeon Phi coprocessor armed with 61 on-chip x86 cores, provides high theoretical peak performance, as well as software development flexibility with existing high-level programming tools. We present an extensive evaluation study of the performance peaks and scalability of these two modern architectures using SPEC OMP benchmarks.

Performance analysis of parallel high‐resolution image restoration algorithms on Intel supercomputer

SummaryIn this article, we present an experimental performance study of a parallel implementation of two Poissonian image restoration algorithms. Hybrid parallelization, based on MPI and OpenMP standards, is investigated. The implementation is tested for high‐resolution radiographic images, on a supercomputer based on Intel Xeon processors, combined with Intel Xeon Phi coprocessors. The experimental results show an essential improvement in the execution times, when running experiments for a variety of problem sizes, and number of threads.

A novel data partitioning algorithm for dynamic energy optimization on heterogeneous high‐performance computing platforms

SummaryEnergy is one of the most important objectives for optimization on modern heterogeneous high‐performance computing (HPC) platforms. The tight integration of multicore CPUs with accelerators such as graphical processing units (GPUs) and Xeon Phi coprocessors in these platforms presents several challenges to the optimization of multithreaded data‐parallel applications for energy. In this work, the problem of optimization of data‐parallel applications on heterogeneous HPC platforms for dynamic energy through workload distribution is formulated. We propose a workload partitioning algorithm to solve this problem. It employs load‐imbalancing technique to determine the workload distribution minimizing the dynamic energy consumption of the parallel execution of an application. The inputs to the algorithm are discrete dynamic energy profiles of individual computing devices. The profiles are practically constructed using an approach that accurately models the energy consumption by execution of a hybrid scientific data‐parallel application on a heterogeneous platform containing different computing devices such as CPU, GPU, and Xeon Phi. The proposed algorithm is experimentally analyzed using two multithreaded data‐parallel applications, matrix multiplication and 2D fast Fourier transform. The load‐imbalanced solutions provided by the algorithm achieve significant dynamic energy reductions for the two applications (in average by 130% and 44%, respectively) compared with the load‐balanced solutions.

Debugging Parallel Programs in DVM-System

DVM-system is designed for the development of parallel programs of scientific and technical calculations in the C-DVMH and Fortran-DVMH languages. These languages use a single DVMH-model of parallel programming model and are an extension of the standard C and Fortran languages with parallelism specifications in the form of compiler directives. The DVMH model makes it possible to create efficient parallel programs for heterogeneous computing clusters, in the nodes of which accelerators, graphic processors or Intel Xeon Phi coprocessors can be used as computing devices along with universal multi-core processors. The article describes the method of debugging parallel programs in DVM-system, as well as new features of DVM-debugger.

The Using of DVM-System for Developing of a Program for Calculations of the Problem of Radiation Magnetic Gas Dynamics and Research of Plasma Dynamics in the QSPA Channel

DVM-system is designed for the development of parallel programs of scientific and technical calculations in the C-DVMH and Fortran-DVMH languages. These languages use a single DVMH-model of parallel programming model and are an extension of the standard C and Fortran languages with parallelism specifications in the form of compiler directives. The DVMH model makes it possible to create efficient parallel programs for heterogeneous computing clusters, in the nodes of which accelerators, graphic processors or Intel Xeon Phi coprocessors can be used as computing devices along with universal multi-core processors. The article describes the experience of the successful using of DVM-system to develop a parallel software code for calculating the problem of radiation magnetic gas dynamics and for research of plasma dynamics in the QSPA channel.

Progress in Dvm-System

DVM-system is designed for the development of parallel programs of scientific and technical calculations in the C-DVMH and Fortran-DVMH languages. These languages use a single DVMH-model of parallel programming model and are an extension of the standard C and Fortran languages with parallelism specifications in the form of compiler directives. The DVMH model makes it possible to create efficient parallel programs for heterogeneous computing clusters, in the nodes of which accelerators, graphic processors or Intel Xeon Phi coprocessors can be used as computing devices along with universal multi-core processors. The article presents new features of DVM-system that have been developed recently.

Parallel approaches of genetic algorithm in the MIC architecture of the Intel Xeon Phi

Today, genetic algorithms are widely used in many fields such as bioinformatics, computer science, artificial intelligence, finance ... Genetic algorithms are applied to create high quality solutions for complex optimization problems in the above industries. There have been many studies based on the proposed new hardware architecture that aims to speed up the execution of genetic algorithms as quickly as possible. Some studies suggest parallel genetic algorithms on systems with multicore CPUs and / or graphics processing units (GPUs). However, very few solutions propose a genetic algorithm that can be run on systems that use the new Intel Xeon Phi co-processor (Intel Many-Integrated Core (MIC) architecture). For that reason, we propose and develop the study of the genetic algorithm on high-performance computing systems with Intel Xeon Phi co-processors. This study will present the results of parallel approaches of genetic algorithm on one and more Intel Xeon Phi co-processors by the following methods: (i) Intel Xeon Phi programming model Offload and Native; and (ii) a combined model of MPI and OpenMP. The proposed genetic algorithm can find the optimal schedule for the energy-efficient scheduling problem of virtual machines on physical machines with the goal of minimization total energy consumption. The results of the simulations show the feasibility of implementing a genetic algorithm on one or many Intel Xeon Phi. Genetic algorithm on one or more distributed Intel Xeon Phi always results in faster algorithm execution time than sequential genetic algorithm and the ability to find better solutions using more Intel Xeon Phi. This research result can be applied to other meta-heuristic like TABU search, Ant Colony Optimization.

A benchmark set of highly-efficient CUDA and OpenCL kernels and its dynamic autotuning with Kernel Tuning Toolkit

In recent years, the heterogeneity of both commodity and supercomputers hardware has increased sharply. Accelerators, such as GPUs or Intel Xeon Phi co-processors, are often key to improving speed and energy efficiency of highly-parallel codes. However, due to the complexity of heterogeneous architectures, optimization of codes for a certain type of architecture as well as porting codes across different architectures, while maintaining a comparable level of performance, can be extremely challenging. Addressing the challenges associated with performance optimization and performance portability, autotuning has gained a lot of interest. Autotuning of performance-relevant source-code parameters allows to automatically tune applications without hard coding optimizations and thus helps with keeping the performance portable. In this paper, we introduce a benchmark set of ten autotunable kernels for important computational problems implemented in OpenCL or CUDA. Using our Kernel Tuning Toolkit, we show that with autotuning most of the kernels reach near-peak performance on various GPUs and outperform baseline implementations on CPUs and Xeon Phis. Our evaluation also demonstrates that autotuning is key to performance portability. In addition to offline tuning, we also introduce dynamic autotuning of code optimization parameters during application runtime. With dynamic tuning, the Kernel Tuning Toolkit enables applications to re-tune performance-critical kernels at runtime whenever needed, for example, when input data changes. Although it is generally believed that autotuning spaces tend to be too large to be searched during application runtime, we show that it is not necessarily the case when tuning spaces are designed rationally. Many of our kernels reach near peak-performance with moderately sized tuning spaces that can be searched at runtime with acceptable overhead. Finally we demonstrate, how dynamic performance tuning can be integrated into a real-world application from cryo-electron microscopy domain.

A server-side accelerator framework for multi-core CPUs and Intel Xeon Phi co-processor systems

Processing-intensive web server requests can lead to low Quality of Service (QoS), such as longer mean response time and lower throughput, which calls for a new web server software framework that can improve the performance of web servers. The characteristic of request-level parallelism in web servers is fit for many-core architecture accelerators, such as GPU and Intel Xeon Phi co-processors, but traditional web server model cannot make full use of the performance of these accelerators. We proposed a new web server software framework— called MIC-based Server-side Accelerator Framework (MSAF)—for a machine with not only multi-core CPUs but also Intel Xeon Phi co-processors based on Staged Event Driven Architecture (SEDA). The framework can fully exploit the performance of Intel Xeon Phi co-processors and multi-core CPUs, and improve power/energy efficiency by offloading the stage of handling requests to Intel Xeon Phi co-processors. We implemented the web server simulation software based on MSAF framework on a machine with multi-core CPUs and Intel Xeon Phi co-processors, and evaluated it by means of Apache Benchmark (AB). Our evaluation of MSAF shows its performance is about equivalent to that of a web server cluster consisting of four to five computing nodes. This paper indicates that if MSAF is applied to, Intel Xeon Phi co-processors are suitable for server side software, such as web servers, DNS servers, and database servers, because of its characteristic of lower communication latency between Intel Xeon Phi co-processors and host, more powerful logic processing ability, and more energy efficiency.

A Hierarchical Data-Partitioning Algorithm for Performance Optimization of Data-Parallel Applications on Heterogeneous Multi-Accelerator NUMA Nodes

Modern HPC platforms are highly heterogeneous with tight integration of multicore CPUs and accelerators (such as Graphics Processing Units, Intel Xeon Phis, or Field-Programmable Gate Arrays) empowering them to address the twin critical concerns of performance and energy efficiency. Due to this inherent characteristic, processing elements contend for shared on-chip resources such as Last Level Cache (LLC), interconnect, etc. and shared nodal resources such as DRAM, PCI-E links, etc., resulting in complexities such as resource contention, non-uniform memory access (NUMA), and accelerator-specific limitations such as limited main memory thereby necessitating support for efficient out-of-card execution. Due to these complexities, the performance profiles of data-parallel applications executing on these platforms are not smooth and deviate significantly from the shapes that allowed state-of-the-art load-balancing algorithms to find optimal solutions. In this paper, we propose a hierarchical two-level data partitioning algorithm minimizing the parallel execution time of data-parallel applications on clusters of $h$ identical nodes where each node has $c$ heterogeneous processors. This algorithm takes as input $c$ discrete speed functions of cardinality $m$ corresponding to the $c$ heterogeneous processors. It does not make any assumptions about the shapes of these functions. Unlike load balancing algorithms, optimal solutions found by the algorithm may not load-balance an application in terms of execution time. The proposed algorithm has low time complexity of $O(m^{2} \times h + m^{3} \times c^{3})$ unlike the state-of-the-art algorithm solving the same problem with the complexity of $O(m^{3} \times c^{3} \times h^{3})$ . We also propose an extension of the algorithm for clusters of $h$ non-identical nodes where each node has $c$ heterogeneous processors. We experimentally demonstrate the optimality of our algorithm using two well-known and highly optimized multi-threaded data-parallel applications, matrix-matrix multiplication and 2D fast Fourier transform, on a heterogeneous multi-accelerator NUMA node containing an Intel multicore Haswell CPU, an Nvidia K40c GPU, and an Intel Xeon Phi co-processor and a simulated homogeneous cluster of such nodes.

Toward a BLAS library truly portable across different accelerator types

Scientific applications are some of the most computationally demanding software pieces. Their core is usually a set of linear algebra operations, which may represent a significant part of the overall run-time of the application. BLAS libraries aim to solve this problem by exposing a set of highly optimized, reusable routines. There are several implementations specifically tuned for different types of computing platforms, including coprocessors. Some examples include the one bundled with the Intel MKL library, which targets Intel CPUs or Xeon Phi coprocessors, or the cuBLAS library, which is specifically designed for NVIDIA GPUs. Nowadays, computing nodes in many supercomputing clusters include one or more different coprocessor types. To fully exploit these platforms might require programs that can adapt at run-time to the chosen device type, hardwiring in the program the code needed to use a different library for each device type that can be selected. This also forces the programmer to deal with different interface particularities and mechanisms to manage the memory transfers of the data structures used as parameters. This paper presents a unified, performance-oriented, and portable interface for BLAS. This interface has been integrated into a heterogeneous programming model (Controllers) which supports groups of CPU cores, Xeon Phi accelerators, or NVIDIA GPUs in a transparent way. The contribution of this paper includes: An abstraction layer to hide programming differences between diverse BLAS libraries; new types of kernel classes to support the context manipulation of different external BLAS libraries; a new kernel selection policy that considers both programmer kernels and different external libraries; a complete new Controller library interface for the whole collection of BLAS routines. This proposal enables the creation of BLAS-based portable codes that can execute on top of different types of accelerators by changing a single initialization parameter. Our software internally exploits different preexisting and widely known BLAS library implementations, such as cuBLAS, MAGMA, or the one found in Intel MKL. It transparently uses the most appropriate library for the selected device. Our experimental results show that our abstraction does not introduce significant performance penalties, while achieving the desired portability.

DL_POLY - A performance overview analysing, understanding and exploiting available HPC technology

ABSTRACT This paper considers the performance attributes of the molecular simulation code, DL_POLY, as measured and analysed over the past two decades. Following a brief overview of HPC technology, and the performance improvements over that period, we define the benchmark cases – for both DL_POLY Classic and DL_POLY 3 & 4 – used in generating a broad overview of performance across well over 100 HPC systems, from the Cray T3E/1200 to today’s Intel Skylake clusters and accelerator technology offerings from Intel’s Xeon Phi co-processor family. Consideration is given to the tools that have proved helpful in analysing the code’s performance. With a more rigorous analysis of performance on recent systems, we discuss the optimum choice of processor and interconnect, and present power measurements when running the code, comparing these to measurements for other community codes.

Investigations of High Throughput Computing for Event Selection Process of MuCh@CBM

There is a requirement of High Throughput Computation (HTC) for the large scale experiment Compressed Baryonic Matter (CBM) experiment which is carried out at Facility for Antiproton and Ion Research (FAIR) centre at GSI Darmstadt, Germany. CBM is a dedicated relativistic heavy ion collision experiment. In this experiment, highly energized ions will be collided with a fixed target resulting production of a rare particle J/Ψ named charmonia which will pass through different detectors of the experiment. One such detector is Muon Chamber (MuCh) Detector System to measure key observables including the measurement of J/Ψ which can be measured via their decay into the di-muon (µ+ and µ-) channel. However the production of charmonium is extremely small therefore experiment is instrumented such that per second total 107 events, one collision is known as one event, will be gathered to have good statistics. To select probable candidate of J/Ψ, an algorithm has been developed. To process the algorithm in optimal way use of heterogeneous platforms consisting of various types of processors are under study. In this work Intel, AMD CPUs and Intel Xeon-Phi co-processors are used with Open MP and P Thread parallel processing methodologies for the mentioned event selection process. The results of using different processors with different methodologies will be presented in this article. It is found that problem scales with the number of threads and optimal at the maximum number of hardware thread (without hyper-threading).

Parallel Algorithm for Frequent Itemset Mining on Intel Many-core Systems

Frequent itemset mining leads to the discovery of associations and correlations among items in large transactional databases. Apriori is a classical frequent itemset mining algorithm, which employs iterative passes over database combining with generation of candidate itemsets based on frequent itemsets found at the previous iteration, and pruning of clearly infrequent itemsets. The Dynamic Itemset Counting (DIC) algorithm is a variation of Apriori, which tries to reduce the number of passes made over a transactional database while keeping the number of itemsets counted in a pass relatively low. In this paper, we address the problem of accelerating DIC on the Intel Xeon Phi many-core system for the case when the transactional database fits in main memory. Intel Xeon Phi provides a large number of small compute cores with vector processing units. The paper presents a parallel implementation of DIC based on OpenMP technology and thread-level parallelism. We exploit the bit-based internal layout for transactions and itemsets. This technique reduces the memory space for storing the transactional database, simplifies the support count via logical bitwise operation, and allows for vectorization of such a step. Experimental evaluation on the platforms of the Intel Xeon CPU and the Intel Xeon Phi coprocessor with large synthetic and real databases showed good performance and scalability of the proposed algorithm.

An OpenMP parallel implementation using a coprocessor for numerical simulation of oil reservoirs

The objective of this work is to parallelize, using the Application Programming Interface (API) OpenMP (Open Multi-Processing) and Intel Xeon Phi coprocessor based on Intel Many Integrated Core (MIC) architecture, the numerical method used to solve the algebraic system resulting from the discretization of the differential partial equation (PDE) that describes the single-phase flow in an oil reservoir. The set of governing equations are the continuity equation and the Darcy’s law. The Hydraulic Diffusivity Equation (HDE), for the unknown pressure, is obtained from these fundamental equations and it is discretized by means of the Finite Difference Method (FDM) along with a time implicit formulation. Different numerical tests were performed to study the computational efficiency of the parallelized versions of Conjugate Gradient, BiConjugate Gradient and BiConjugate Gradient Stabilized methods. Speedup results were considered to evaluate the performance of the parallel algorithms for the horizontal well simulation case. The methodology also included a sensibility analysis for different production scenarios including variations on the permeability, formation-value-factor, well length and production rate.

Решение прикладных задач с использованием DVM-системы

DVM-system was designed to create parallel programs of scientific-technical computations in C-DVMH and Fortran-DVMH languages. These languages use the same model of parallel programming (DVMH-model) and are the extensions of standard C and Fortran languages by parallelism specifications, implemented as compiler directives. DVMH-model allows creating efficient parallel programs for heterogeneous computational clusters, the nodes of which use as computing devices not only universal multi-core processors but also can use attached accelerators (GPUs or Intel Xeon Phi coprocessors). This article describes the experience of parallelizing various application programs using DVM-system. The method of incremental or partial parallelization, the system's capabilities for working with unstructured grids, new tools for mapping MPI-programs to multi-core processors and accelerators are considered. The efficiency of parallel DVMH-programs on heterogeneous computing clusters K-10, K-100, Lomonosov and MVS-10P is investigated. The main advantages of DVM-approach for the development of parallel programs are described. The main features of DVM-system tools for performance analysis and functional debugging of parallel programs are presented. The directions for further development of DVM-system are determined.

Fast solution of electromagnetic scattering problems using Xeon Phi coprocessors

Electromagnetic scattering problems can be solved by discretizing and transforming integral equations into matrix equations using the method of moments. In large-scale problems, the problem cannot be solved directly and needs to be solved using iterative methods, which use matrix vector products (MVP) to perform the iterative convergence to the solution. An efficient parallel implementation of MVP over Intel Xeon Phi coprocessor is proposed in this paper to speed up the solution of the scattering over a generalized minimal residual method. Using these manycore integrated processors, we can solve an electromagnetic scattering three-dimensional problem improving runtime on a coprocessor system.

Modeling Nonlinear Stabilization System on Clusters with Intel Xeon Phi Coprocessors

Currently, cluster systems are widely used, the nodes of which use processors with a large number of cores. Effective software implementation on such computing systems requires that the corresponding mathematical models have a significant parallelism resource. For the problems of modeling of hybrid dynamical systems (HDS) a significant resource of parallelism is typical, since in this class of mathematical models the (theoretically infinite-dimensional) phase space of control objects with space-distributed parameters is isolated. The purpose of this work is to study the effectiveness of the software implementation on parallel computing systems of the class of modeling problems of the influence of typical nonlinearities and nonstationarity on the output vector function of the HDS. As an example, a nonlinear stabilization system for a mobile control object (the rocket taking into account the elastic deformations of its body) is considered.

MSNP: A Massively Parallel Algorithm for Large-Scale SNP Detection

Single Nucleotide Polymorphism (SNP) detection is a fundamental procedure of whole genome analysis. SOAPsnp, a classic tool for detection, would take more than one week to analyze one typical human genome, which limits the efficiency of downstream analyses. In this paper, we present mSNP, an optimized version of SOAPsnp, which leverages Intel Xeon Phi coprocessors for large-scale SNP detection. Firstly, we redesigned the essential data structures of SOAPsnp, which significantly reduces memory footprint and improves computing efficiency. Then we developed a coordinated parallel framework for a higher hardware utilization of both CPU and Xeon Phi. Also, we tailored the data structures and operations to utilize the wide VPU of Xeon Phi to improve data throughput. Last but not the least, we proposeed a read-based window division strategy to improve throughput and obtain better load balance. mSNP is the first SNP detection tool empowered by Xeon Phi. We achieved a 38x single thread speedup on CPU, without any loss in precision. Moreover, mSNP successfully scaled to 4,096 nodes on Tianhe-2. Our experiments demonstrate that mSNP is efficient and scalable for large-scale human genome SNP detection.

A Novel Data-Partitioning Algorithm for Performance Optimization of Data-Parallel Applications on Heterogeneous HPC Platforms

Modern HPC platforms have become highly heterogeneous owing to tight integration of multicore CPUs and accelerators (such as Graphics Processing Units, Intel Xeon Phis, or Field-Programmable Gate Arrays) empowering them to maximize the dominant objectives of performance and energy efficiency. Due to this inherent characteristic, processing elements contend for shared on-chip resources such as Last Level Cache (LLC), interconnect, etc. and shared nodal resources such as DRAM, PCI-E links, etc. This has resulted in severe resource contention and Non-Uniform Memory Access (NUMA) that have posed serious challenges to model and algorithm developers. Moreover, the accelerators feature limited main memory compared to the multicore CPU host and are connected to it via limited bandwidth PCI-E links thereby requiring support for efficient out-of-card execution. To summarize, the complexities (resource contention, NUMA, accelerator-specific limitations, etc.) have introduced new challenges to optimization of data-parallel applications on these platforms for performance. Due to these complexities, the performance profiles of data-parallel applications executing on these platforms are not smooth and deviate significantly from the shapes that allowed state-of-the-art load-balancing algorithms to find optimal solutions. In this paper, we formulate the problem of optimization of data-parallel applications on modern heterogeneous HPC platforms for performance. We then propose a new model-based data partitioning algorithm, which minimizes the execution time of computations in the parallel execution of the application. This algorithm takes as input a set of $p$ discrete speed functions corresponding to $p$ available heterogeneous processors. It does not make any assumptions about the shapes of these functions. We prove the correctness of the algorithm and its complexity of $O(m^3 \times p^3)$ , where $m$ is the cardinality of the input discrete speed functions. We experimentally demonstrate the optimality and efficiency of our algorithm using two data-parallel applications, matrix multiplication and fast Fourier transform, on a heterogeneous cluster of nodes where each node contains an Intel multicore Haswell CPU, an Nvidia K40c GPU, and an Intel Xeon Phi co-processor.