A server-side accelerator framework for multi-core CPUs and Intel Xeon Phi co-processor systems

Abstract

Processing-intensive web server requests can lead to low Quality of Service (QoS), such as longer mean response time and lower throughput, which calls for a new web server software framework that can improve the performance of web servers. The characteristic of request-level parallelism in web servers is fit for many-core architecture accelerators, such as GPU and Intel Xeon Phi co-processors, but traditional web server model cannot make full use of the performance of these accelerators. We proposed a new web server software framework— called MIC-based Server-side Accelerator Framework (MSAF)—for a machine with not only multi-core CPUs but also Intel Xeon Phi co-processors based on Staged Event Driven Architecture (SEDA). The framework can fully exploit the performance of Intel Xeon Phi co-processors and multi-core CPUs, and improve power/energy efficiency by offloading the stage of handling requests to Intel Xeon Phi co-processors. We implemented the web server simulation software based on MSAF framework on a machine with multi-core CPUs and Intel Xeon Phi co-processors, and evaluated it by means of Apache Benchmark (AB). Our evaluation of MSAF shows its performance is about equivalent to that of a web server cluster consisting of four to five computing nodes. This paper indicates that if MSAF is applied to, Intel Xeon Phi co-processors are suitable for server side software, such as web servers, DNS servers, and database servers, because of its characteristic of lower communication latency between Intel Xeon Phi co-processors and host, more powerful logic processing ability, and more energy efficiency.