X86 Processors Research Articles

A parallel implementation of an MHD code for the simulation of mechanically driven, turbulent dynamos in spherical geometry

A parallel implementation of a nonlinear pseudo-spectral MHD code for the simulation of turbulent dynamos in spherical geometry is reported. It employs a dual domain decomposition technique in both real and spectral space. It is shown that this method shows nearly ideal scaling going up to 128 CPUs on Beowulf-type clusters with fast interconnect. Furthermore, the potential of exploiting single precision arithmetic on standard x86 processors is examined. It is pointed out that the MHD code thereby achieves a maximum speedup of 1.7, whereas the validity of the computations is still granted. The combination of both measures will allow for the direct numerical simulation of highly turbulent cases ( 1500 < Re < 5000 ), which have been previously impractical, given today's computational speed.

Implementation of a constant‐time dynamic storage allocator

AbstractThis paper describes the design criteria and implementation details of a dynamic storage allocator for real‐time systems. The main requirements that have to be considered when designing a new allocator are concerned with temporal and spatial constraints. The proposed algorithm, called TLSF (two‐level segregated fit), has an asymptotic constant cost, O(1), maintaining a fast response time (less than 200 processor instructions on a x86 processor) and a low level of memory usage (low fragmentation). TLSF uses two levels of segregated lists to arrange free memory blocks and an incomplete search policy. This policy is implemented with word‐size bitmaps and logical processor instructions. Therefore, TLSF can be categorized as a good‐fit allocator. The incomplete search policy is shown also to be a good policy in terms of fragmentation. The fragmentation caused by TLSF is slightly smaller (better) than that caused by best fit (which is one of the best allocators regarding memory fragmentation). In order to evaluate the proposed allocator, three analyses are presented in this paper. The first one is based on worst‐case scenarios. The second one provides a detailed consideration of the execution cost of the internal operations of the allocator and its fragmentation. The third analysis is a comparison with other well‐known allocators from the temporal (number of cycles and processor instructions) and spatial (fragmentation) points of view. In order to compare them, a task model has been presented. Copyright © 2007 John Wiley &amp; Sons, Ltd.

8088 ORAL Supportive cancer care in British Forces Germany: perceptions of patients, carers and health and social care professionals

This chapter is the first of three that explores the Intel(R) Architecture, focusing on the fundamental design. The chapter begins with the Intel(R) 8086, the first x86 processor. Then the Intel(R) 8087 coprocessor is covered, along with the IEEE 754 floating point specification and the Intel(R) 80286. The chapter ends by looking at the Intel(R) 80386, the first 32-bit Intel(R) processor and the first processor to run Linux.

Performance and security lessons learned from virtualizing the alpha processor

Virtualization has become much more important throughout the computer industry both to improve security and to support multiple workloads on the same hardware with effective isolation between those workloads. The most widely used chip architecture, the Intel and AMD x86 processors, have begun to support virtualization, but the initial implementations show some limitations. This paper examines the virtualization properties of the Alpha architecture with particular emphasis on features that improve performance and security. It shows how the Alpha's features of PALcode, address space numbers, software handling of translation buffer misses, lack of used and modified bits, and secure handling of unpredictable results all contribute to making virtualization of the Alpha particularly easy. The paper then compares the virtual architecture of the Alpha with Intel's and AMD's virtualization approaches for x86. It also comments briefly on Intel's virtualization technology for Itanium, IBM's zSeries and pSeries hypervisors and Sun's UltraSPARC virtualization. It particularly identifies some differences between translation buffers on x86 and translation buffers on VAX and Alpha that can have adverse performance consequences.

AN ULTRA HIGH BANDWIDTH AUTOMOTIVE RAPID PROTOTYPE SYSTEM

For developers of automotive control, prototyping and initial tests are a hassle. Commercial solutions are available but the price and especially the price/performance ratio opens the field for more cost effective solutions. Automotive rapid prototype systems seen so far are mainly processor based systems with standard interrupt driven measurement and actuation. Control systems based on high time resolution measurements of for example cylinder pressure are difficult to implement using these systems, neither is it possible to implement controller loops with an extremely high bandwidth in combination with expensive algorithms. Measurement and actuation within the same engine cycle, In Cycle Control (ICC) are not possible. The proposed system is based on a mixed system consisting of one standard x86 processor which is configured through Simulink and a reconfigurable application specific integrated circuit (an FPGA) configured either by relevant FPGA design tools or by Simulink. This layout of the rapid prototype system enables the designer to implement either ICC with very high bandwidth (only limited by the capacity of the injection system) or between-cycle control with medium bandwidth. The aim of this paper is to describe one possible configuration of such a system and to discuss the possible performance outcome of the final system.

On Applying Graph Theory to ILP Analysis

The evaluation of computer architectures requires new tools that complement the customary simulations. Graph theory can help to create a new frame of fine grain parallelism analysis. The differences found between the superscalar performance in x86 and non-x86 processors and the peculiar characteristics of the x86 instruction set architecture recommend to carry out a thorough study of the available parallelism at the machine language layer. Starting off from graph theory foundations, new concepts are introduced, from reduced valence to data dependence matrix D, the latter characterizing a code sequence in a mathematical manner. This matrix satisfies a series of properties and restrictions and provides information about the ability of the code to be processed concurrently. The different sources of data dependencies can be composed, facilitating a way to analyze their final influence on the degree of parallelism.

Sequential in-core sorting performance for a SQL data service and for parallel sorting on heterogeneous clusters

The aim of the paper is to introduce techniques in order to tune sequential in-core sorting algorithms in the frameworks of two applications. The first application is parallel sorting when the processor speeds are not identical in the parallel system. The second application is the Zeta-Data Project [M. Koskas, A hierarchical database management algorithm, in: Annales 67 du Lamsade, vol. 2, 2004, pp. 277–317. [9]] whose aim is to develop novel algorithms for databases issues. About 50% of the work done in building indexes is devoted to sorting sets of integers. We develop and compare algorithms built to sort with equal keys. Algorithms are variations of the 3Way-Quicksort of Sedgewick. In order to observe performances and to fully exploit functional units in processors, and also in order to optimize the use of the memory system and the different functional units, we use hardware performance counters that are available on most modern microprocessors. We also develop analytical results for one of our algorithms and compare expected results with the measures. For the two applications, we show, through fine experiments on an Athlon processor (a three-way superscalar x86 processor), that L1 data cache misses are not the central problem, but a subtle proportion of independent retired instructions should be advised to get performance for in-core sorting.

Dam buffer overflow

From the infamous Morris worm in 1988, to the Zotob worm in August 2005, the buffer overflow has been the issue causing most of network administrators' security headaches. Yet three key issues remain misunderstood: how buffer overflows happen, how attackers use them to break into networks, and what can be done about them from the perspective of network administrators, developers and management. Several attempts have been made to cure the problem - no remedies have proved totally effective. For simplicity, this technical discussion is limited to the Intel x86 processors, since the mechanics of buffer overflows can vary significantly for different types of processor. A buffer overflow occurs when data is copied into a buffer that is too small to hold it.

The impact of x86 instruction set architecture on superscalar processing

Performance improvement of x86 processors is a relevant matter. From the point of view of superscalar processing, it is necessary to complement the studies on instruction use with analogous ones on data use and, furthermore, analyze the data flow graphs, as its dependencies are responsible for limitations on ILP. In this work, using instruction traces from common applications, quantitative analyses of implicit operands, memory addressing and condition codes have been performed, three sources of significant limitations on the maximum achievable parallelism in the x86 architecture. In order to get a deeper knowledge of these limitations, the data dependence graphs are built from traces. By means of graph matrix representation, potentially exploitable parallelism is quantified and parallelism distributions from the traces are shown. The method has also been applied to measure the impact of the use of condition codes. Results are compared with previous work and some conclusions are presented relating the obtained degree of parallelism with negative characteristics of x86 instruction set architecture.

SCELib2: the new revision of SCELib, the parallel computational library of molecular properties in the single center approach

SCELib2: the new revision of SCELib, the parallel computational library of molecular properties in the single center approach

네트워크 프로세서 기반의 침입탐지 시스템 구현

To help network intrusion detection systems(NIDSs) keep up with the demands of today`s networks, that we the increasing network throughput and amount of attacks, a radical new approach in hardware and software system architecture is required. In this paper, we propose a Network Processor(NP) based In-Line mode NIDS that supports the packet payload inspection detecting the malicious behaviors, as well as the packet filtering and the traffic metering. In particular, we separate the filtering and metering functions from the deep packet inspection function using two-level searching scheme, thus the complicated and time-consuming operation of the deep packet inspection function does not hinder or flop the basic operations of the In-line mode system. From a proto-type NP-based NIDS implemented at a PC platform with an x86 processor running Linux, two Gigabit Ethernet ports, and 2.5Gbps Agere PayloadPlus(APP) NP solution, the experiment results show that our proposed scheme can reliably filter and meter the full traffic of two gigabit ports at the first level even though it can inspect the packet payload up to 320 Mbps in real-time at the second level, which can be compared to the performance of general-purpose processor based Inspection. However, the simulation results show that the deep packet searching is also possible up to 2Gbps in wire speed when we adopt 10Gbps APP solution.

Optimizing precision overhead for x86 processors

AbstractIt is a major challenge for a Java JIT compiler to perform single‐precision floating‐point operations efficiently for the x86 processors. In previous research, the double‐precision mode is set as the default precision mode when methods are invoked. Sophisticated approaches then use heuristic approaches to optimization by considering the trade‐offs between roundings and mode switches. However, this convention introduces redundant mode switches across method boundaries. Furthermore, methods that include both single‐ and double‐precision operations cannot switch the mode, even if single‐precision operations are dominant. We propose a new approach to these problems. We eliminate redundant mode switches by ignoring the default precision mode and calling a method in the same precision mode as the caller. For methods that include both single‐ and double‐precision methods, we reduce the overhead of rounding by isolating code segments of a given method that should be executed in the single‐precision mode. We implemented our approach in IBM's Just‐in‐Time compiler, and obtained experimental results demonstrating that, in SPECjvm98, it consistently shows the best performance in any configuration of benchmark programs, inline policies, and processor architectures compared with previous research approaches. Copyright © 2004 John Wiley &amp; Sons, Ltd.

실시간 운영체제 Qplus-P용 그래픽 윈도우 라이브러리 구현

디지털 TV, 인터넷 셋탑박스, 인터넷 전화기 등과 같은 정보가전 제품이 속속 등장하면서 이들 제품의 기능을 제어하는데 필수적인 실시간 운영체제 시장이 크게 성장하고 있다. 한국전자통신연구원에서는 소형의 휴대 정보 단말에서부터 디지털 셋탑박스 및 홈 서버까지 다양한 종류의 정보가전 기기에 공통으로 사용될 수 있는 확장 가능한 표준 실시간 운영체제 Qplus-P를 개발하였다. 본 논문에서는 정보가전용 실시간 운영체제 Qplus-P에 탑재되는 그래픽 윈도우 라이브러리의 구현에 대해 기술한다. Qplus-P 그래픽 윈도우 라이브러리는 공개소스인 tiny-X 그래픽 서버에 한글 처리 기능, 화면 회전 기능, 터치스크린 입력 기능, 그래픽 가속 기능 등을 추가하였다. Qplus-P 그래픽 윈도우 라이브러리는 현재 arm 프로세서를 사용하는 아이팩 3600 PDA, 삼성 S3C2400 보드, 자우루스 PDA와 x86 프로세서를 사용하는 홈서버에 탑재되었으며, Qplus-P타겟 빌더에 통합된 형태로 제공된다. As the Internet appliances like digital TV, Internet set-top boxes, and Internet phone, are showing up in the market, the economics of real-time operating system (RTOS), which is an essential for controlling those devices, is expanding faster than ever before. ETRI has developed describes RTOS called Qplus-P, targeting various platforms ranging from PDA to Internet set-top box and home server. This paper describes the implementation of graphic window library for Qplus-P. The Qplus-P graphic window library was implemented using tiny-X graphic server and gtk graphic toolkit, which are open source software. To port this library to various aliances, hangul processing, screen rotation, touch screen, and graphic acceleration functions are added to the tiny-X graphic server of the implementd graphic window library. Currently, Qplus-P graphic window is running on ARM-based appliances such as iPaq PDA, Samsung S3C2400 board, Zaurus PDA, and on Home Server that uses x86 processor. Qplus-P graphic library is provided as a of Qplus-P target builder.

A novel all-binary motion estimation (ABME) with optimized hardware architectures

We present a fast motion estimation algorithm using only binary representation, which is desirable for both embedded system and hardware implementation with parallel architectures. The key algorithm distinction is that only the high-frequency spectrum is used. Our experimental results show that it provides excellent performance at both low and high bit rates. Because of its binary-only representation, the proposed algorithm offers low computational complexity and low memory bandwidth consumption. For multimedia-embedded system design, we further investigated specific implementation techniques for several well-known hardware platforms including Intel x86 processors, single-instruction multiple-data processors, and systolic array circuit design. The systolic array architecture requires only single memory access for both the reference and current frames from the on-chip memory. Such an implementation provides an optimized solution with great throughput, while the quality is maintained. Finally, we show that our binarization methods are closely coupled to the accuracy of binary motion estimation algorithms. The binarization and coding efficiencies can be improved using various filters and binarization methods.

GROMACS 3.0: a package for molecular simulation and trajectory analysis

GROMACS 3.0 is the latest release of a versatile and very well optimized package for molecular simulation. Much effort has been devoted to achieving extremely high performance on both workstations and parallel computers. The design includes an extraction of virial and periodic boundary conditions from the loops over pairwise interactions, and special software routines to enable rapid calculation of x–1/2. Inner loops are generated automatically in C or Fortran at compile time, with optimizations adapted to each architecture. Assembly loops using SSE and 3DNow! Multimedia instructions are provided for x86 processors, resulting in exceptional performance on inexpensive PC workstations. The interface is simple and easy to use (no scripting language), based on standard command line arguments with self-explanatory functionality and integrated documentation. All binary files are independent of hardware endian and can be read by versions of GROMACS compiled using different floating-point precision. A large collection of flexible tools for trajectory analysis is included, with output in the form of finished Xmgr/Grace graphs. A basic trajectory viewer is included, and several external visualization tools can read the GROMACS trajectory format. Starting with version 3.0, GROMACS is available under the GNU General Public License from http://www.gromacs.org.

Design and implementation of a distributed virtual machine for networked computers

This paper describes the motivation, architecture and performance of a distributed virtual machine (DVM) for networked computers. DVMs rely on a distributed service architecture to meet the manageability, security and uniformity requirements of large, heterogeneous clusters of networked computers. In a DVM, system services, such as verification, security enforcement, compilation and optimization, are factored out of clients and located on powerful network servers. This partitioning of system functionality reduces resource requirements on network clients, improves site security through physical isolation and increases the manageability of a large and heterogeneous network without sacrificing performance. Our DVM implements the Java virtual machine, runs on x86 and DEC Alpha processors and supports existing Java-enabled clients.

Execution characteristics of desktop applications on Windows NT

This paper examines the performance of desktop applications running on the Microsoft Windows NT operating system on Intel x86 processors, and contrasts these applications to the programs in the integer SPEC95 benchmark suite. We present measurements of basic instruction set and program characteristics, and detailed simulation results of the way these programs use the memory system and processor branch architecture. We show that the desktop applications have similar characteristics to the integer SPEC95 benchmarks for many of these metrics. However, compared to the integer SPEC95 applications, desktop applications have larger instruction working sets, execute instructions in a greater number of unique functions, cross DLL boundaries frequently, and execute a greater number of indirect calls.