X86 Platform Research Articles

A new scheme for improving the utilisation of nested-cloud resources

In recent years, cloud computing has played an important role in IT fields. It brings benefits such as high computing efficiency, cost saving, provisioning on-demand of computing resources and high utilisation of the hardware. However, with more fields and businesses involved in cloud computing, the inherent problems in its structure are restricting the further development of cloud computing. And the most serious problem is how to maximumly achieve the high-usage of the cloud resources. In this paper, we present a scheme based on multi-layer nested virtualisation technology. It can make full use of the allocations of a virtual machine (VM) provided by an infrastructure-as-a-service (IaaS) provider. Furthermore, we also propose a task scheduling approach for nested cloud environment correspondingly. The task scheduling algorithm considers both the computing efficiency and the monetary costs paid for the cloud service. In order to justify our proposal, we use KVM as unmodified multiple hypervisor to run multi-layer VMs on x86 platform. We also do simulations to test our task scheduling algorithm. And the result shows encouraging support for our proposal.

A new scheme for improving the utilisation of nested-cloud resources

In recent years, cloud computing has played an important role in IT fields. It brings benefits such as high computing efficiency, cost saving, provisioning on-demand of computing resources and high utilisation of the hardware. However, with more fields and businesses involved in cloud computing, the inherent problems in its structure are restricting the further development of cloud computing. And the most serious problem is how to maximumly achieve the high-usage of the cloud resources. In this paper, we present a scheme based on multi-layer nested virtualisation technology. It can make full use of the allocations of a virtual machine (VM) provided by an infrastructure-as-a-service (IaaS) provider. Furthermore, we also propose a task scheduling approach for nested cloud environment correspondingly. The task scheduling algorithm considers both the computing efficiency and the monetary costs paid for the cloud service. In order to justify our proposal, we use KVM as unmodified multiple hypervisor to run multi-layer VMs on x86 platform. We also do simulations to test our task scheduling algorithm. And the result shows encouraging support for our proposal.

A Retargetable System-level DBT Hypervisor

System-level Dynamic Binary Translation (DBT) provides the capability to boot an Operating System (OS) and execute programs compiled for an Instruction Set Architecture (ISA) different from that of the host machine. Due to their performance-critical nature, system-level DBT frameworks are typically hand-coded and heavily optimized, both for their guest and host architectures. While this results in good performance of the DBT system, engineering costs for supporting a new architecture or extending an existing architecture are high. In this article, we develop a novel, retargetable DBT hypervisor, which includes guest-specific modules generated from high-level guest machine specifications. Our system simplifies retargeting of the DBT, but it also delivers performance levels in excess of existing manually created DBT solutions. We achieve this by combining offline and online optimizations and exploiting the freedom of a Just-in-time (JIT) compiler operating in a bare-metal environment provided by a Virtual Machine (VM) hypervisor. We evaluate our DBT using both targeted micro-benchmarks as well as standard application benchmarks, and we demonstrate its ability to outperform the de facto standard Q EMU DBT system. Our system delivers an average speedup of 2.21× over Q EMU across SPEC CPU2006 integer benchmarks running in a full-system Linux OS environment, compiled for the 64-bit ARMv8-A ISA and hosted on an x86-64 platform. For floating-point applications the speedup is even higher, reaching 6.49× on average. We demonstrate that our system-level DBT system significantly reduces the effort required to support a new ISA while delivering outstanding performance.

Memory Forensic Challenges Under Misused Architectural Features

With increasingly complex cyber attacks occurring every day, memory-based forensic techniques are becoming instrumental in digital investigations. Forensic examiners can unravel what happened on a system by acquiring and inspecting in-memory data. However, the foundation of this analysis can be invalidated if the memory acquisition has been altered. In this paper, we study the feasibility of malicious software misusing architectural features to sabotage memory forensics. The misuse of two architectural features, namely, physical address layout and secure containers, is presented. The first architectural feature explored in this paper is the physical address layout. It is used by the northbridge to route memory access to either physical memory or I/O devices on x86 platforms. Observing this design choice, we propose Hidden in I/O Space (HIveS), which manipulates CPU registers to alter the physical address layout to conceal memory. The system uses a novel I/O shadowing technique to lock a memory region named HIveS memory into I/O address space to prevent access. Two novel techniques, blackbox write and TLB camouflage, are developed to further protect the unlocked HIveS memory against memory forensics while allowing access for attackers. The second architectural feature explored in this paper is hardware-aided secure execution technology. More specifically, hardware-enforced memory encryption in Intel secure guard extension is used in malicious enclave software (Malclaveware) to prevent introspection and memory forensics. A prototype of HIveS is built and tested against a set of memory acquisition tools for both Windows and Linux running on the x86 platform. Malclaveware is also prototyped in Windows to demonstrate the risk. More importantly, we proposed countermeasures and mitigations for the newly discovered attacks. Through these discussions, we aim to raise the awareness of the potential risks of misusing hardware architectural features.

Predictable Shared Cache Management for Multi-Core Real-Time Virtualization

Real-time virtualization has gained much attention for the consolidation of multiple real-time systems onto a single hardware platform while ensuring timing predictability. However, a shared last-level cache (LLC) on modern multi-core platforms can easily hamper the timing predictability of real-time virtualization due to the resulting temporal interference among consolidated workloads. Since such interference caused by the LLC is highly variable and may have not even existed in legacy systems to be consolidated, it poses a significant challenge for real-time virtualization. In this article, we propose a predictable shared cache management framework for multi-core real-time virtualization. Our framework introduces two hypervisor-level techniques, vLLC and vColoring, that enable the cache allocation of individual tasks running in a virtual machine (VM), which is not achievable by the current state of the art. Our framework also provides a cache management scheme that determines cache allocation to tasks, designs VMs in a cache-aware manner, and minimizes the aggregated utilization of VMs to be consolidated. As a proof of concept, we implemented vLLC and vColoring in the KVM hypervisor running on x86 and ARM multi-core platforms. Experimental results with three different guest OSs (i.e., Linux/RK, vanilla Linux, and MS Windows Embedded) show that our techniques can effectively control the cache allocation of tasks in VMs. Our cache management scheme yields a significant utilization benefit compared to other approaches while satisfying timing constraints.

Multi-threaded ATLAS simulation on Intel Knights Landing processors

The Knights Landing (KNL) release of the Intel Many Integrated Core (MIC) Xeon Phi line of processors is a potential game changer for HEP computing. With 72 cores and deep vector registers, the KNL cards promise significant performance benefits for highly-parallel, compute-heavy applications. Cori, the newest supercomputer at the National Energy Research Scientific Computing Center (NERSC), was delivered to its users in two phases with the first phase online at the end of 2015 and the second phase now online at the end of 2016. Cori Phase 2 is based on the KNL architecture and contains over 9000 compute nodes with 96GB DDR4 memory. ATLAS simulation with the multithreaded Athena Framework (AthenaMT) is a good potential use-case for the KNL architecture and supercomputers like Cori. ATLAS simulation jobs have a high ratio of CPU computation to disk I/O and have been shown to scale well in multi-threading and across many nodes. In this paper we will give an overview of the ATLAS simulation application with details on its multi-threaded design. Then, we will present a performance analysis of the application on KNL devices and compare it to a traditional x86 platform to demonstrate the capabilities of the architecture and evaluate the benefits of utilizing KNL platforms like Cori for ATLAS production.

TinyVisor: An extensible secure framework on android platforms

As the utilization of mobile platform keeps growing, the security issue of mobile platform becomes a serious threat to user privacy. The current security measures mainly focus on the application level and the framework level, with little protection on the kernel. Virtualization technologies have been used in x86 platforms to protect the security of the kernel. With a higher privilege than the guest operating system, the hypervisor can effectively detect and defend against the malicious activity inside the guest kernel. In this paper, we build a hypervisor framework called TinyVisor leveraging the ARM virtualization extensions to protect the guest system security. The framework is transparent to the guest operating system and applications without any code modification. On top of the framework, we propose a secure module called H-Binder to protect the integrity and secrecy of the Binder transaction data in Android system. We implement the prototype of TinyVisor with the H-Binder module and evaluate the performance. The experiment results show non-significant performance loss.

Ahead-of-time compilation of JavaScript programs

Modern virtual machines for JavaScript use just-in-time (JIT) compilation to produce binary code. JIT compilers cannot perform complex optimizations. In contrast, static compilation has unlimited capabilities for complex optimizing transformations, but it cannot be efficiently applied to dynamic languages, such as JavaScript. In this paper, a general approach to the ahead-of-time compilation of programs in dynamic languages is proposed, and this approach is used for improving two virtual machines JavaScript- Core and V8. In the implementation of the improved JavaScriptCore engine with ahead-of-time compilation, the specifics of using JavaScript programs as a part of locally stored applications for the ARM platform were taken into account. In the V8 engine for the x86-64 platform, the ahead-of-time compilation is implemented by caching an optimized internal representation in a separate file.

Virtualizing Programmable Logic Controllers: Toward a Convergent Approach

Modern programmable logic controllers (PLCs) are pervasive components in industrial control systems (ICSs) such as supervisory control and data acquisition, designed to control industrial processes autonomously or as part of a distributed system topology. Its success may be explained by its robustness and reliability, being one of the most enduring legacies on modern ICS, despite having evolved very little over the last years. This letter proposes an x86-based virtual PLC (vPLC) architecture that decouples the logic and control capabilities from the I/O components, while virtualizing the PLC logic within a real-time hypervisor. To demonstrate the feasibility of this concept, the topic of real-time virtualization for x86 platforms is analyzed, together with an evaluation study of the properties of real-time workloads in partitioned hypervisor environments.

HW/SW co-optimization for stencil computation: Beginning with a customizable core

Energy efficiency is one of the most important issues for High Performance Computing (HPC) today. Heterogeneous HPC platform with some energy-efficient customizable cores (as application-specific accelerators) is believed as one of the promising solutions to meet ever-increasing computing needs and to overcome power density limitations. In this paper, we focus on using customizable processor cores to optimize the typical stencil computations — the kernel of many high-performance applications. We develop a series of effective software/hardware co-optimization strategies to exploit the instruction-level and memory-computation parallelism, as well as to decrease the energy consumption. These optimizations include loop tiling, prefetching, cache customization, Single Instruction Multiple Data (SIMD), and Direct Memory Access (DMA), as well as necessary ISA extensions. Detailed tests of power-efficiency are given to evaluate the effect of all these optimizations comprehensively. The results are impressive: the combination of these optimizations has improved the application performance by 341% while the energy consumption has been decreased by 35%; a preliminary comparison with X86, GPU, and FPGA platforms also showed that the design could achieve an order of magnitude higher performance efficiency. We believe this work can help understand sources of inefficiency in general-purpose chips and can be used as a beginning to customize an energy efficient CMP for further improvement.

FEA simulation of thermal processes during the direct metal laser sintering of Ti64 titanium powder

Abstract With regard to the fact that laser sintering belongs to the high-temperature processes in which metal particles are sintered by a high-power laser, forming a homogenous structure, it is necessary and important to know the characteristics and the mechanism of these thermal processes. A high-power laser system produces three forms of heat that include convection, conduction, and radiation. These thermal processes affect the formation of internal stresses and tension that lead to deformations and rapidly influence the resulting quality, dimensions, density, micro-structure, and mechanical properties of fabricated parts. In response to this fact, it was important to analyse these heat transfer methods instantly during the direct metal laser sintering (DMLS) process simulation and subsequently monitor the parameters and settings of the sintering equipment in order to obtain acceptable manufacture outputs intended for further use. This work is focused on the creation of a FEA simulation model and the simulation of thermal processes across an object during and after the sintering process in the cooling stage, when it is important to consider a laser beam trajectory, temperatures of individual elements affected by the laser beam, and current laser energy in time. A 3D FEA simulation model was created in order to represent actual behaviour of a part during the sintering process. The simulation model consisted of two sub-models, particularly the building platform model with the dimensions of 250 mm × 250 mm × 22 mm, with stainless steel as the selected material, and the model of individual layers of sintered titanium powder with the dimensions of 10 mm × 10 mm × 0.03 mm. The total number of used layers was 12, which represents the total thickness of 0.36 mm. Applied power was P = 170 W. The simulation as such was carried out using the FEA software, Simulia Abaqus supported on the Windows x86-64 platform, which uses an integrated solver to make thermal and mechanic calculations. The calculations included also the impact of the protective argon atmosphere located in the process chamber. Mutual impact between individual layers was also considered. The simulation results were confronted with the results of already performed experimental studies of other scientific works, with the compliance and confirmation of assumptions being on a very good level.

Effect of portable fine-grained locality on energy efficiency and performance in concurrent search trees

Recent research has suggested that improving fine-grained data-locality is one of the main approaches to improving energy efficiency and performance. However, no previous research has investigated the effect of the approach on these metrices in the case of concurrent data structures. This paper investigates how fine-grained data locality influences energy efficiency and performance in concurrent search trees, a crucial data structure that is widely used in several important systems. We conduct a set of experiments on three lock-based concurrent search trees: DeltaTree, a portable fine-grained locality-aware concurrent search tree; CBTree, a coarse-grained locality-aware B+tree; and BST-TK, a locality-oblivious concurrent search tree. We run the experiments on a commodity x86 platform and an embedded ARM platform. The experimental results show that DeltaTree has 13--25% better energy efficiency and 10--22% more operations/second on the x86 and ARM platforms, respectively. The results confirm that portable fine-grained locality can improve energy efficiency and performance in concurrent search trees.

Application execution path analysis for the automatic parallelisation of binary codes in the Intel x86 platform

Traditionally, computer programs have been developed using the sequential programming paradigm. With the advent of parallel computing systems, such as multicore processors and distributed environments, the sequential paradigm became a barrier to the utilisation of the available resources, since the program is restricted to a single processing unit. To address this issue, we propose a transparent automatic parallelisation tool with a binary rewriter. The steps of our approach are: the disassembly of the Intel x86 application, its transformation into an intermediary language; the analysis of this intermediary representation to obtain the flow and dependency graphs; the partitioning of the application into parallel units, using the obtained graphs; and, finally, the reassembly of the application back into the original Intel x86 architecture. By transforming the compiled application software, we aim at obtaining a program which can better explore the parallel resources, with no extra effort required from users or developers.

4K Real-Time and Parallel Software Video Decoder for Multilayer HEVC Extensions

Two High Efficiency Video Coding (HEVC) extensions, namely, the scalable HEVC (SHVC) extension and multiview HEVC (MV-HEVC) extension, have been finalized in July 2014 by the Moving Picture Experts Group and Video Coding Experts Group. These two extensions enable additional features not covered in the first version of the HEVC standard such as spatial, fidelity, bitdepth, and color gamut scalability, as well as stereoscopic and multiview representations. In this paper, we propose a software parallel decoder architecture for the HEVC standard and its multilayer extensions, including SHVC and MV-HEVC extensions. The decoder consists of multiple instances of the OpenHEVC decoder, one instance to decode each layer with a communication between dependent layers to perform inter-layer predictions. The proposed multilayer HEVC decoder is parallel friendly and supports both wavefront parallelism to simultaneously process adjacent rows of the frame and frame-based parallelism to decode a set of temporal and spatial frames in parallel. Moreover, the most time-consuming operation introduced in the SHVC extension, namely, the resampling of the inter-layer reference picture in spatial scalability, is optimized in single instruction multiple data for x86 platform. We assess the complexity of the multilayer HEVC decoder with respect to the simulcast configuration. The multilayer decoder decoding two SHVC layers introduces in average 40%–71% additional complexity compared with the single layer HEVC decoder. Moreover, the low level optimizations with a hybrid parallel processing solution enable a real-time decoding of 4Kp60 enhancement layer on a 6-core Intel i7 processor running at 3.4 GHz.

Omni-Kernel: An Operating System Architecture for Pervasive Monitoring and Scheduling

The omni-kernel architecture is designed around pervasive monitoring and scheduling. Motivated by new requirements in virtualized environments, this architecture ensures that all resource consumption is measured, that resource consumption resulting from a scheduling decision is attributable to an activity, and that scheduling decisions are fine-grained. Vortex , implemented for multi-core x86-64 platforms, instantiates the omni-kernel architecture, providing a wide range of operating system functionality and abstractions. With Vortex, we experimentally demonstrated the efficacy of the omni-kernel architecture to provide accurate scheduler control over resource allocation despite competing workloads. Experiments involving Apache, MySQL, and Hadoop quantify the cost of pervasive monitoring and scheduling in Vortex to be below $6$ percent of cpu consumption.

Intercepting Functions for Memoization

Memoization is the technique of saving the results of executions so that future executions can be omitted when the input set repeats. Memoization has been proposed in previous literature at the instruction, basic block, and function levels using hardware, as well as pure software--level approaches including changes to programming language. In this article, we focus on software memoization for procedural languages such as C and Fortran at the granularity of a function. We propose a simple linker-based technique for enabling software memoization of any dynamically linked pure function by function interception and illustrate our framework using a set of computationally expensive pure functions—the transcendental functions. Transcendental functions are those that cannot be expressed in terms of a finite sequence of algebraic operations (trigonometric functions, exponential functions, etc.) and hence are computationally expensive. Our technique does not need the availability of source code and thus can even be applied to commercial applications, as well as applications with legacy codes. As far as users are concerned, enabling memoization is as simple as setting an environment variable. Our framework does not make any specific assumptions about the underlying architecture or compiler toolchains and can work with a variety of current architectures. We present experimental results for a x86-64 platform using both gcc and icc compiler toolchains, and an ARM Cortex-A9 platform using gcc. Our experiments include a mix of real-world programs and standard benchmark suites: SPEC and Splash2x. On standard benchmark applications that extensively call the transcendental functions, we report memoization benefits of up to 50% on Intel Ivy Bridge and up to 10% on ARM Cortex-A9. Memoization was able to regain a performance loss of 76% in bwaves due to a known performance bug in the GNU implementation of the pow function. The same benchmark on ARM Cortex-A9 benefited by more than 200%.

HSPT

Cross-ISA (Instruction Set Architecture) system-level virtual machine has a significant research and practical value. For example, several recently announced virtual smart phones for iOS which run smart phone applications on x86 based PCs are deployed on cross-ISA system level virtual machines. Also, for mobile device application development, by emulating the Android/ARM environment on the more powerful x86-64 platform, application development and debugging become more convenient and productive. However, the virtualization layer often incurs high performance overhead. The key overhead comes from memory virtualization where a guest virtual address (GVA) must go through multi-level address translation to become a host physical address (HPA). The Embedded Shadow Page Table (ESPT) approach has been proposed to effectively decrease this address translation cost. ESPT directly maps GVA to HPA, thus avoid the lengthy guest virtual to guest physical, guest physical to host virtual, and host virtual to host physical address translation. However, the original ESPT work has a few drawbacks. For example, its implementation relies on a loadable kernel module (LKM) to manage the shadow page table. Using LKMs is less desirable for system virtual machines due to portability, security and maintainability concerns. Our work proposes a different, yet more practical, implementation to address the shortcomings. Instead of relying on using LKMs, our approach adopts a shared memory mapping scheme to maintain the shadow page table (SPT) using only ''mmap'' system call. Furthermore, this work studies the support of SPT for multi-processing in greater details. It devices three different SPT organizations and evaluates their strength and weakness with standard and real Android applications on the system virtual machine which emulates the Android/ARM platform on x86-64 systems.

Deep Packet Inspection Based on Many-Core Platform

With the development of computer technology, network bandwidth and network traffic continue to increase. Considering the large data flow, it is imperative to perform inspection effectively on network packets. In order to find a solution of deep packet inspection which can appropriate to the current network environment, this paper built a deep packet inspection system based on many-core platform, and in this way, verified the feasibility to implement a deep packet inspection system under many-core platform with both high performance and low consumption. After testing and analysis of the system performance, it has been found that the deep packet inspection based on many-core platform TILE_Gx36 [1] [2] can process network traffic of which the bandwidth reaches up to 4 Gbps. To a certain extent, the performance has improved compared to most deep packet inspection system based on X86 platform at present.

Real-time Implementation of a xAVS Video Decoder

AVS video decoder consumes a huge number of computation, so real-time implementation of an AVS decoder has some challenging on x86 computing platform. This article describes a xAVS open source project to solve this problem. First of all, the reason for the low efficiency of the code of the existing AVS video decoder open source reference software RM52J_r1 is analyzed according to the description of AVS key technologies and decoding principles in the official documentation. Then according to the main problems of the reference software, re-design the optimized xAVS decoder architecture, and real-time property significantly improved with C code. Finally, use the x86 platform multimedia instruction sets to further optimize xAVS semantic processor. The experimental results show that, under the precondition of ensuring the quality of decoding, the decoding speed of the xAVS decoder for D1 has increased more than 14 times, to fully meet the needs of real-time decoding. DOI : http://dx.doi.org/10.11591/telkomnika.v12i6.5473 Full Text: PDF

Efficient and Retargetable Dynamic Binary Translation on Multicores

Dynamic binary translation (DBT) is a core technologyto many important applications such as system virtualization, dynamic binary instrumentation, and security. However, there are several factors that often impede its performance: 1) emulation overhead before translation; 2) translation and optimization overhead; and 3) translated code quality. The issues also include its retargetabilitythat supports guest applications from different instruction-set architectures (ISAs) to host machines also with different ISAs-an important feature to system virtualization. In this work, we take advantage of the ubiquitous multicore platforms, and use a multithreaded approach to implement DBT. By running the translator and the dynamic binary optimizer on different cores with different threads, it could off-load the overhead incurred by DBT on the target applications; thus, afford DBT of more sophisticated optimization techniques as well as its retargetability. Using QEMU (a popular retargetable DBT for system virtualization) and Low-Level Virtual Machine (LLVM) as our building blocks, we demonstrated in a multithreaded DBT prototype, called Hybrid-QEMU (HQEMU), that it could improve QEMU performance by a factor of 2.6x and 4.1x on the SPEC CPU2006 integer and floating point benchmarks, respectively, for dynamic translation of x86 code to run on x86-64 platforms. For ARM codes to x86-64 platforms, HQEMU can gain a factor of 2.5x speedup over QEMU for the SPEC CPU2006 integer benchmarks. We also address the performance scalability issue of multithreaded applications across ISAs. We identify two major impediments to performance scalability in QEMU: 1) coarse-grained locks used to protect shared data structures, and 2) inefficient emulation of atomic instructions across ISAs. We proposed two techniques to mitigate those problems: 1) using indirect branch translation caching (IBTC) to avoid frequent accesses to locks, and 2) using lightweight memory transactions to emulate atomic instructions across ISAs. Our experimental results show that for multithread applications, HQEMU achieves 25X speedups over QEMU for the PARSEC benchmarks.