WS2 Transistors Research Articles

Understanding the Impact of Contact-Induced Strain on the Electrical Performance of Monolayer WS2 Transistors.

Two-dimensional (2D) electronics require low contact resistance (RC) to approach their fundamental limits. WS2 is a promising 2D semiconductor that is often paired with Ni contacts, but their operation is not well understood considering the nonideal alignment between the Ni work function and the WS2 conduction band. Here, we investigate the effects of contact size on nanoscale monolayer WS2 transistors and uncover that Ni contacts impart stress, which affects the WS2 device performance. The strain applied to the WS2 depends on contact size, where long (1 μm) contacts (RC ≈ 1.7 kΩ·μm) show a 78% reduction in RC compared to shorter (0.1 μm) contacts (RC ≈ 7.8 kΩ·μm). We also find that thermal annealing can relax the WS2 strain in long-contact devices, increasing RC to 8.5 kΩ·μm. These results reveal that thermo-mechanical phenomena can significantly influence 2D semiconductor-metal contacts, presenting opportunities to optimize device performance through nanofabrication and thermal budget.

Biaxial Tensile Strain Enhances Electron Mobility of Monolayer Transition Metal Dichalcogenides.

Strain engineering can modulate the properties of two-dimensional (2D) semiconductors for electronic and optoelectronic applications. Recent theory and experiments have found that uniaxial tensile strain can improve the electron mobility of monolayer MoS2, a 2D semiconductor, but the effects of biaxial strain on charge transport are not well characterized in 2D semiconductors. Here, we use biaxial tensile strain on flexible substrates to probe electron transport in monolayer WS2 and MoS2 transistors. This approach experimentally achieves ∼2× higher on-state current and mobility with ∼0.3% applied biaxial strain in WS2, the highest mobility improvement at the lowest strain reported to date. We also examine the mechanisms behind this improvement through density functional theory simulations, concluding that the enhancement is primarily due to reduced intervalley electron-phonon scattering. These results underscore the role of strain engineering in 2D semiconductors for flexible electronics, sensors, integrated circuits, and other optoelectronic applications.

Nanoironing van der Waals Heterostructures toward Electrically Controlled Quantum Dots.

Assembling two-dimensional van der Waals (vdW)-layered materials into heterostructures is an exciting development that sparked the discovery of rich correlated electronic phenomena. vdW heterostructures also offer possibilities for designer device applications in areas such as optoelectronics, valley- and spintronics, and quantum technology. However, realizing the full potential of these heterostructures requires interfaces with exceptionally low disorder which is challenging to engineer. Here, we show that thermal scanning probes can be used to create pristine interfaces in vdW heterostructures. Our approach is compatible at both the material- and device levels, and monolayer WS2 transistors show up to an order of magnitude improvement in electrical performance from this technique. We also demonstrate vdW heterostructures with low interface disorder enabling the electrical formation and control of quantum dots that can be tuned from macroscopic current flow to the single-electron tunneling regime.

Ultrashort channel chemical vapor deposited bilayer WS2 field-effect transistors

Two-dimensional transition metal dichalcogenides (TMDs) are potential candidates for next generation channel materials owing to their atomically thin structure and high carrier mobility, which allow for the ultimate scaling of nanoelectronics. However, TMDs-based field-effect transistors are still far from delivering the expected performance, which is mainly attributed to their high contact resistance and low saturation velocity (vsat). In this work, we report high-performance short-channel WS2 transistors based on bandgap engineering. The bilayer WS2 channel not only shows a higher average field-effect mobility (μFE) than the monolayer channel but also exhibits excellent metal-Ohmic contact using a regular physical vapor deposition deposited Ni/Au contact, reducing the Rc value to a record low value of 0.38 kΩ · μm without any intentional doping. The bilayer WS2 device of the 80 nm channel exhibits a high on-state current of 346 μA/μm at Vds = 1 V, near-zero drain-induced barrier lowering, and a record high Ion/Ioff ratio over 109. Furthermore, a record high on-state current of 635 μA/μm at Vds = 1 V and a record high vsat of 3.8 × 106 cm/s have been achieved for a shorter 18 nm channel device, much higher than previous WS2 transistors. This work reveals the intrinsically robust nature of bilayer WS2 crystals with promising potential for integration with conventional fabrication processes.

Low‐Power Logic‐in‐Memory Complementary Inverter Based on p‐WSe2 and n‐WS2

AbstractTransition metal dichalcogenides have been considered as candidate materials to construct logic‐in‐memory devices for realizing non‐von‐Neumann architecture. Thus, reducing the power consumption is extremely critical for their applications in big data and artificial intelligence. Here, a low‐power logic‐in‐memory device is demonstrated by constructing complementary inverter with p‐WSe2 and n‐WS2 transistors. By engineering the interface states between WSe2 (WS2) and substrate artificially, non‐volatile memory with resistance ratio of 104 and 103 after 500 s are achieved in individual WSe2 and WS2 transistors, respectively. Furthermore, a complementary inverter with a retention time longer than 500 s is realized by connecting p‐WSe2 and n‐WS2 transistors. More importantly, the static operating source‐drain current Ids of this inverter is around 0.5/0.1 nA at low/high resistance states with source‐drain voltage Vds = 5 V, and the hysteresis window is located around 0 V, both of which can reduce the energy consumption dramatically and leads to the low operation power. This work provides a convenient strategy to build a non‐von‐Neumann device toward post‐Moore information processing technology.

Improved Self-Heating in Short-Channel Monolayer WS2 Transistors with High-Thermal Conductivity BeO Dielectrics.

Two-dimensional semiconducting transition metal dichalcogenides (TMDs) enable ultimate channel length scaling of transistor technology due to their atomic-thin body nature, which also brings the challenge of a pronounced self-heating effect inside the ultrathin channel. In particular, high current density under high electric field could lead to negative differential resistance behavior due to self-heating, not only limiting the current carrying capability of the TMDs transistors but also leading to severe reliability issues. Here, we report high-performance monolayer WS2 transistors on a high-thermal-conductivity BeO dielectric with effective suppression of the self-heating effects, eliminating the negative differential resistance behavior at high field, as observed in the case of the HfO2 dielectric. The monolayer CVD WS2 device on BeO with a 50 nm channel length exhibits a record-high on-state current of 325 μA/μm, transconductance (gm) of 150 μS/μm, and a on/off ratio of 1.8 × 108 at Vds = 1 V, far exceeding previous results.

Performance enhancement of WS2 transistors via double annealing

Herein, we report the double annealing strategy to improve the device performance of WS2 transistors fabricated using multilayer WS2 flakes on SiO2/p++-Si substrates. In the double annealing approach, the annealing is performed twice, both before and after electrode formation. The statistical analysis of 50 WS2 transistors indicated that, compared to the conventional single annealing, the double annealing increased the average field-effect mobility and reduced the average contact resistance. The enhanced device performance could be attributed to the improved interface quality between WS2 and the electrodes, owing to the removal of organic residues and desorption of surface adsorbents during the first annealing before the electrode formation. These results demonstrate the effectiveness of double annealing in enhancing the device performance of WS2 transistors, suggesting the important role of process optimization in fabricating WS2 transistors and other transition metal dichalcogenide devices.

The origin of gate bias stress instability and hysteresis in monolayer WS2 transistors

Due to the ultra-thin nature and moderate carrier mobility, semiconducting two-dimensional (2D) materials have attracted extensive attention for next-generation electronics. However, the gate bias stress instability and hysteresis are always observed in these 2D materials-based transistors that significantly degrade their reliability for practical applications. Herein, the origin of gate bias stress instability and hysteresis for chemical vapor deposited monolayer WS2 transistors are investigated carefully. The transistor performance is found to be strongly affected by the gate bias stress time, sweeping rate and range, and temperature. Based on the systematical study and complementary analysis, charge trapping is determined to be the major contribution for these observed phenomena. Importantly, due to these charge trapping effects, the channel current is observed to decrease with time; hence, a rate equation, considering the charge trapping and time decay effect of current, is proposed and developed to model the phenomena with excellent consistency with experimental data. All these results do not only indicate the validity of the charge trapping model, but also confirm the hysteresis being indeed caused by charge trapping. Evidently, this simple model provides a sufficient explanation for the charge trapping induced gate bias stress instability and hysteresis in monolayer WS2 transistors, which can be also applicable to other kinds of transistors.

Design of MXene contacts for high-performance WS2 transistors

Achieving low-resistance contact is crucial for enhancing the performances of nanoelectronic devices. To find high-performance WS2 transistors, we systematically investigated the interfacial properties of monolayer WS2 in contact with a series of MXenes (Ti2C, V2C, Cr2C, Zr2C, Hf3C2, and Ti3C2) using first-principles calculations. Analyses of the interface structure, effective potential, electron localization function, energy bands, and density of states of the MXene top contacts with monolayer WS2 indicated that Ti2C, Zr2C, Hf3C2, and Ti3C2 couple strongly with WS2, leading to the metallization of monolayer WS2 and the formation of ideal Ohmic contacts in the vertical direction. To further evaluate the performances of the WS2/MXene transistors, the quantum transport properties were simulated using the nonequilibrium Green’s function method. The results indicated that the WS2 transistors with Zr2C and Hf3C2 electrodes have small lateral Schottky barrier heights of 0 and 0.08 eV, respectively, implying the formation of Ohmic and quasi-Ohmic contacts in WS2/Zr2C and WS2/Hf3C2. It means that low-resistance contacts can be achieved at WS2/Zr2C and WS2/Hf3C2 systems, indicating that Zr2C and Hf3C2 are promising electrode for monolayer WS2 to form high-performance transistors. These findings provide vital insights for the design of high-performance nanoelectronic devices based on two-dimensional materials.

Reduced Turn-On Voltage and Boosted Mobility in Monolayer WS2 Transistors by Mild Ar+ Plasma Treatment.

Monolayer two-dimensional transition-metal dichalcogenides, such as tungsten disulfide (WS2), are regarded as promising candidates for optoelectronic and electronic applications. Although theoretical calculations have predicted outstanding electronic properties of WS2, the performance of WS2-based electronic devices is still limited by the relatively high Schottky barrier and low carrier mobility. In this work, low-energy argon (Ar+) plasma treatment was used as a nondestructive preconditioning technique to tailor the electrical properties of the WS2 monolayer grown by chemical vapor deposition. Photoluminescence and Raman spectroscopy were used to monitor the modified optical properties of WS2 with increasing plasma treatment time. An improved electrical conductivity was observed after a short-time plasma treatment. The physical mechanism was further revealed by a comparative study between top-electrode and bottom-electrode devices and simulation based on the density functional theory. It is concluded that mild Ar+ plasma treatment can effectively lower the Schottky barrier height and the effective mass of carriers, which reduces the turn-on voltage and enhances the mobility, respectively. However, if the processing time is too long, the WS2 lattice structure will be destroyed. This work has provided an effective method for manipulating the Schottky barrier and mobility of monolayer WS2 transistors and paves the way for developing high-performance electronic devices based on 2D semiconductors.

Utilizing a NaOH Promoter to Achieve Large Single-Domain Monolayer WS2 Films via Modified Chemical Vapor Deposition.

Because of their fascinating properties, two-dimensional (2D) nanomaterials have attracted a lot of attention for developing next-generation electronics and optoelectronics. However, there is still a lack of cost-effective, highly reproducible, and controllable synthesis methods for developing high-quality semiconducting 2D monolayers with a sufficiently large single-domain size. Here, utilizing a NaOH promoter and W foils as the W source, we have successfully achieved the fabrication of ultralarge single-domain monolayer WS2 films via a modified chemical vapor deposition method. With the proper introduction of a NaOH promoter, the single-domain size of monolayer WS2 can be increased to 550 μm, while the WS2 flakes can be well controlled by simply varying the growth duration and oxygen concentration in the carrier gas. Importantly, when they are fabricated into global backgated transistors, WS2 devices exhibit respectable peak electron mobility up to 1.21 cm2 V-1 s-1, which is comparable to those of many state-of-the-art WS2 transistors. Photodetectors based on these single-domain WS2 monolayers give an impressive photodetection performance with a maximum responsivity of 3.2 mA W-1. All these findings do not only provide a cost-effective platform for the synthesis of high-quality large single-domain 2D nanomaterials, but also facilitate their excellent intrinsic material properties for the next-generation electronic and optoelectronic devices.

Improvement of the Bias Stress Stability in 2D MoS2 and WS2 Transistors with a TiO2 Interfacial Layer.

The fermi-level pinning phenomenon, which occurs at the metal–semiconductor interface, not only obstructs the achievement of high-performance field effect transistors (FETs) but also results in poor long-term stability. This paper reports on the improvement in gate-bias stress stability in two-dimensional (2D) transition metal dichalcogenide (TMD) FETs with a titanium dioxide (TiO2) interfacial layer inserted between the 2D TMDs (MoS2 or WS2) and metal electrodes. Compared to the control MoS2, the device without the TiO2 layer, the TiO2 interfacial layer deposited on 2D TMDs could lead to more effective carrier modulation by simply changing the contact metal, thereby improving the performance of the Schottky-barrier-modulated FET device. The TiO2 layer could also suppress the Fermi-level pinning phenomenon usually fixed to the metal–semiconductor interface, resulting in an improvement in transistor performance. Especially, the introduction of the TiO2 layer contributed to achieving stable device performance. Threshold voltage variation of MoS2 and WS2 FETs with the TiO2 interfacial layer was ~2 V and ~3.6 V, respectively. The theoretical result of the density function theory validated that mid-gap energy states created within the bandgap of 2D MoS2 can cause a doping effect. The simple approach of introducing a thin interfacial oxide layer offers a promising way toward the implementation of high-performance 2D TMD-based logic circuits.

Electronic properties of monolayer tungsten disulfide grown by chemical vapor deposition

We demonstrate chemical vapor deposition of large monolayer tungsten disulfide (WS2) (>200 μm). Photoluminescence and Raman spectroscopy provide insight into the structural and strain heterogeneity of the flakes. We observe exciton quenching at grain boundaries that originate from the nucleation site at the center of the WS2 flakes. Temperature variable transport measurements of top-gated WS2 transistors show an apparent metal-to-insulator transition. Variable range and thermally activated hopping mechanisms can explain the carrier transport in the insulating phase at low and intermediate temperatures. The devices exhibit room-temperature field-effect electron mobility as high as 48 cm2/V.s. The mobility increases with decreasing temperature and begins to saturate at below 100 °K, possibly due to Coulomb scattering or defects.

Full-range electrical characteristics of WS2 transistors

We fabricated transistors formed by few layers to bulk single crystal WS2 to quantify the factors governing charge transport. We established a capacitor network to analyze the full-range electrical characteristics of the channel, highlighting the role of quantum capacitance and interface trap density. We find that the transfer characteristics are mainly determined by the interplay between quantum and oxide capacitances. In the OFF-state, the interface trap density (<1012 cm–2) is a limiting factor for the subthreshold swing. Furthermore, the superior crystalline quality and the low interface trap density enabled the subthreshold swing to approach the theoretical limit on a back-gated device on SiO2/Si substrate.

Electron transport of WS2 transistors in a hexagonal boron nitride dielectric environment

We present the first study of the intrinsic electrical properties of WS2 transistors fabricated with two different dielectric environments WS2 on SiO2 and WS2 on h-BN/SiO2, respectively. A comparative analysis of the electrical characteristics of multiple transistors fabricated from natural and synthetic WS2 with various thicknesses from single- up to four-layers and over a wide temperature range from 300 K down to 4.2 K shows that disorder intrinsic to WS2 is currently the limiting factor of the electrical properties of this material. These results shed light on the role played by extrinsic factors such as charge traps in the oxide dielectric thought to be the cause for the commonly observed small values of charge carrier mobility in transition metal dichalcogenides.

Scanning photocurrent microscopy reveals electron-hole asymmetry in ionic liquid-gated WS2 transistors

We perform scanning photocurrent microscopy on WS2 ionic liquid-gated field effect transistors exhibiting high-quality ambipolar transport. By properly biasing the gate electrode, we can invert the sign of the photocurrent showing that the minority photocarriers are either electrons or holes. Both in the electron- and hole-doping regimes the photocurrent decays exponentially as a function of the distance between the illumination spot and the nearest contact, in agreement with a two-terminal Schottky-barrier device model. This allows us to compare the value and the doping dependence of the diffusion length of the minority electrons and holes on a same sample. Interestingly, the diffusion length of the minority carriers is several times larger in the hole accumulation regime than in the electron accumulation regime, pointing out an electron-hole asymmetry in WS2.