Worst-case Stress Condition Research Articles

Hot-Carrier-Induced Degradation and Optimization for Lateral DMOS With Split-STI-Structure in the Drift Region

The lateral double-diffusion MOS with split shallow trench isolation structure (split-STI LDMOS) in the drift region has been investigated under two hotcarrier stresses including the maximum bulk current stress (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bulkmax</sub> ) and maximum operating gate stress (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gmax</sub> ). For the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bulkmax</sub> stress condition, the main damage point causing the degradation of RON is found at the STI corner closest to the source with the interface state generation. In addition, the hot hole injection is found at the edge of the shrinking poly-gate region. For the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gmax</sub> stress condition, the main damage point causing the degradation of R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> is found at the two STI corners with interface state generation. Due to the more serious degradation of R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> , the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bulkmax</sub> stress condition is regarded as the worst-case stress condition. The novel structure with the H-shape STI in the drift region is proposed. It is demonstrated that the H-shape STI structure is effectively helpful to alleviate the hot-carrier degradation without altering the tradeoff between the OFF-state breakdown voltage and specific ON-resistance.

Worst Case Stress Conditions for Hot Carrier Degradation with Technology Nodes from 0.35µm to 45nm

The worst case stress conditions for hot carrier degradation have been investigated in detail at the devices fabricated with CMOS technologies from 0.35µm to 45nm. In nMOSFETs with long channel devices (L>0.18µm), Vg at Ibmax and the lowest temperature is the worst case condition; For short channel devices (0.13 µm ≤ L ≤ 0.18μm), Vg @ Ibmax and Vg=Vd stress conditions result in comparable hot carrier damage; For the very short channel transistors (L<0.13µm), the worst case stress condition has been found to be Vg=Vd instead of Vg@Ibmax. In this case, the higher temperature will induce worse hot carrier degradation. In pMOSFETs, the stress conditions Vg@Igmax is the worst case condition for the long channel devices (L≥0.35µm). As the channel length scaled to sub-0.25µm, the worst case stress condition shifts from Vg@Igmax to VG = VD.

Gate voltage dependence on hot carrier degradation at an elevated temperature in a device with ultrathin silicon oxynitride

The effects of hot carrier stress (HCS) at elevated temperature on a device with ultrathin silicon oxynitride have been investigated. It was shown that the degradation of the device was more significant at elevated temperature compared with at room temperature. This behavior attributed to more generation of interface states due to an increase in the high-energy tail electrons. By the theory of electron-electron scattering, the threshold voltage shift was the most severe at the condition of VG&amp;gt;VD. However, based on the results of extrapolating the device lifetime, the worst case stress condition under HCS was the VG=VD condition at elevated temperature due to a higher generation rate.

Worst case stress conditions for hot carrier induced degradation of p-channel SOI MOSFETs

In this paper a comprehensive study of the worst case hot carrier stress conditions for p-channel partially depleted SOI MOSFETs is carried out. It is found that while stress at maximum gate current results to the conventional PMOSFET degradation mechanism (i.e., electron trapping in the gate oxide on the drain side), significant damage is also introduced following stress at the high gate/high drain voltage ( V G = V D) condition. A series of experiments unambiguously demonstrate that this damage is not caused by hot hole injection and that device degradation mechanism at V G = V D stress condition (formation of interface states and positive oxide charges) is in fact due to negative bias temperature instability which is activated because of the self-heating effect. In addition, stress at high temperature is found to result in a shift of the worst case stress condition from maximum gate current to V G = V D.

Empirical reliability modeling for 0.18-μm MOS devices

This paper presents a simple yet effective approach to modeling empirically the 0.18-μm MOS reliability. Short-term stress data are first measured, and the well-known power law is used to project the MOS long-term degradation and lifetime. These results are then used as the basis for the development of an empirical model to predict the MOS lifetime as a function of drain voltage and channel length. Our study focuses on the worst-case stress condition, and both the linear and saturation operations are considered in the modeling. Very good agreement between the measurements and model calculations has been demonstrated.

Low and high temperature device reliability investigations of buried p-channel MOSFETs of a 0.17 μm technology

The hot carrier degradation of buried p-channel MOSFETs of a 0.17 μm technology is assessed in the temperature range between −40°C and 125°C. Within this temperature range, the degradation of the electrical parameter is investigated for different drain voltages and channel lengths (0.2–0.3 μm) in the gate voltage range between V GS=0 V and V GS= V DS. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are discussed by reviewing previous works. Based on hot carrier modelling and lifetime extrapolation to operating conditions the stressing voltage conditions are analysed. For the experimentally investigated temperature range the worst case stress condition is identified at low temperatures for gate voltage at the maximum of the gate current ( I G max ). In the case of V GS corresponding to I G max two activation energies are determined for low and high temperatures. For temperatures above 125°C the worst case bias condition changes from V GS =V GS @I G max to V GS= V DS.

Influence of the lightly doped drain resistance on the worst-case hot-carrier stress condition for NMOS devices

In this paper the underlying mechanisms that produce the cross-over in worst-case hot-carrier stress condition observed at room temperature in some deep submicron lightly doped drain (LDD) NMOS devices and at cryogenic temperatures for devices with longer channel lengths are investigated. Experiments were performed that demonstrate the generality of the cross-over. The role of stress temperature, measurement temperature and stress condition were experimentally addressed. The temperature dependence of the mobility was measured, and an analysis is presented that shows that mobility changes alone do not explain the observed changes in the transconductance. A model is proposed that allows for changes in the source–drain resistance with stress time. It is suggested that the origin of the time-dependent increasing source–drain resistance is the injection of charge, either in the form of fixed charge or as interface states, into the spacer oxide above the LDD region. This model is used to explain the qualitative dependence of the worst-case stress condition on channel length and temperature. Finally, it is suggested that the methodology used to design the LDD structure be modified to account for these new observations.

Projecting lifetime of deep submicron MOSFETs

A detailed examination of hot-carrier-induced degradation in MOSFETs from a 0.25-/spl mu/m and a 0.1-/spl mu/m technology is performed. Although the worst case stress condition depends on the stress voltage, channel length, and oxide thickness, I/sub b,peak/ is projected to be the worst case stress condition at the operating voltage for both nMOSFETs and pMOSFETs. Post-metallization anneal (PMA) in deuterium can significantly improve the device lifetime if the primary degradation mechanism at the stress condition is interface trap generation due to interface depassivation by energetic electrons.