Worst-case Response Time Research Articles

Implications of architecture and implementation choices on timing analysis of automotive CAN networks

The Controller Area Network (CAN) protocol is widely adopted in industry such as automotive. It has been analyzed in a number of studies in the real-time systems community to compute the worst case response time of messages, based on an ideal model on the behavior of the message queuing and CAN controller. Recently, more results are being added to study systems that are not constructed according to the ideal model.In this paper, we further investigate the architecture choices that may affect the timing analysis. Specifically, we provide an assessment on the practical relevance of several analysis results. We also present theory and empirical studies on the relative importance of architecture implementation issues that are quite common in real systems but further deviate from the ideal behavior. We also experimentally evaluate the response time while using TxObjects without preemption. We propose a heuristic for the design of multiple software queues when TxObjects are not preemptable. Finally, we derive an upper bound on the worst case response time when message output at the CAN driver is polling based.

Schedulability Analysis in Fixed-Priority Real-Time Multicore Systems with Contention

In the scheduling of hard real-time systems on multicore platforms, significant unpredictability arises from interference caused by shared hardware resources. The objective of this paper is to offer a schedulability analysis for such systems by assuming a general model that introduces interference as a time parameter for each task. The analysis assumes constrained deadlines and is provided for fixed priorities. It is based on worst-case response time analysis, which exists in the literature for monocore systems. We demonstrate that the worst-case response time is an upper bound, and we evaluate our proposal with synthetic loads and execution on a real platform.

A real-time vital control module to increase capabilities of railway control systems in highly automated train operations

Recent advances in technology and railway have led to the introduction of systems and infrastructures capable of driving trains automatically. The Automatic Train Operation (ATO) system has been optimized for active human supervision. The next challenge is to realize ATO systems capable of achieving unsupervised operations on the mainlines. However, at this aim, additional safety functionalities should be provided. In this paper, we propose a pioneer hardware/software Vital Control Module (VCM) architecture capable of expanding the control capabilities of the existing train control system. The VCM includes a Printed Circuit Board (PCB), to be integrated into the cabin equipment, managed by a reliable and safe hard Real-Time Operating System (RTOS). Both hardware and software are developed to be compliant with related safety standards. The VCM integrates an application logic that acts as an on-board equipment control core, assessing the overall operativity in real-time, and promptly issuing emergency brakes if hazardous situations occur. The application logic has been developed with a model-based approach via Simulink/Stateflow tool and implemented as a C-script on the Xilinx Ultrascale + core housed on the PCB. We have used two testbeds to evaluate the VCM performance. Experimental results showed that the Worst-Case Response Time (WCRT) by the application logic is 13.6 times smaller than the most limiting specification-related deadline. The achieved earliness (− 1.8 ms out of 2 ms of deadline) allows for the easy expansion of VCM’s train protection capabilities in the future. Results from the second testbed showed that the VCM can intervene to mitigate hazardous situations ~ 2 times faster than the current automatic train protection systems according to the related standard.

Compositional verification of embedded real-time systems

In an embedded real-time system (ERTS), real-time tasks (software) are typically executed on a multicore shared-memory platform (hardware). The number of cores is usually small, contrasted with a larger number of complex tasks that share data to collaborate. Since most ERTSs are safety-critical, it is crucial to rigorously verify their software against various real-time requirements under the actual hardware constraints (concurrent access to data, number of cores). Both the real-time systems and the formal methods communities provide elegant techniques to realize such verification, which nevertheless face major challenges. For instance, model checking (formal methods) suffers from the state-space explosion problem, whereas schedulability analysis (real-time systems) is pessimistic and restricted to simple task models and schedulability properties. In this paper, we propose a scalable and generic approach to formally verify ERTSs. The core contribution is enabling, through joining the forces of both communities, compositional verification to tame the state-space size. To that end, we formalize a realistic ERTS model where tasks are complex with an arbitrary number of jobs and job segments, then show that compositional verification of such model is possible, using a hybrid approach (from both communities), under the state-of-the-art partitioned fixed-priority (P-FP) with limited preemption scheduling algorithm. The approach consists of the following steps, given the above ERTS model and scheduling algorithm. First, we compute fine-grained data sharing overheads for each job segment that reads or writes some data from the shared memory. Second, we generalize an algorithm that, aware of the data sharing overheads, computes an affinity (task-core allocation) guaranteeing the schedulability of hard-real-time (HRT) tasks. Third, we devise a timed automata (TA) model of the ERTS, that takes into account the affinity, the data sharing overheads and the scheduling algorithm, on which we demonstrate that various properties can be verified compositionally, i.e., on a subset of cores instead of the whole ERTS, therefore reducing the state-space size. In particular, we enable the scalable computation of tight worst-case response times (WCRTs) and other tight bounds separating events on different cores, thus overcoming the pessimism of schedulability analysis techniques. We fully automate our approach and show its benefits on three real-world complex ERTSs, namely two autonomous robots and an automotive case study from the WATERS 2017 industrial challenge.

Partial-order reduction in reachability-based response-time analyses of limited-preemptive DAG tasks

Response-time analysis (RTA) has been a means to evaluate the temporal correctness of real-time systems since the 1970 s. While early analyses were successful in capturing the exact upper bound on the worst-case response-time (WCRT) of systems with relatively simple computing platforms and task activation models, nowadays we see that most existing RTAs either become pessimistic or do not scale well as systems become more complex (e.g., parallel tasks running on a multicore platform). To make a trade-off between accuracy and scalability, recently, a new reachability-based RTA, called schedule-abstraction graph (SAG), has been proposed. The analysis is at least three orders of magnitude faster than other exact RTAs based on UPPAAL. However, it still has a fundamental limitation in scalability as it suffers from state-space explosion when there are large uncertainties in the timing parameters of the input jobs (e.g., large release jitters or execution-time variations). This could impede its applicability to large industrial use cases, or to be integrated with automated tools that explore alternative design choices. In this paper, we improve the scalability of the SAG analysis by introducing partial-order reduction rules that avoid combinatorial exploration of all possible scheduling decisions. We include systems with dependent and independent task execution models (i.e., with and without precedence constraint). Our empirical evaluations show that the proposed solution is able to reduce the runtime by five orders of magnitude and the number of explored states by 98% in comparison to the original SAG analysis. These achievements come only at a negligible cost of an over-estimation of 0.1% on the actual WCRT. We applied our solution on an automotive case study showing that it is able to scale to realistic systems made of hundreds of tasks for which the original analysis fails to finish.

Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation.

One of the fundamental requirements of a real-time system (RTS) is the need to guarantee re-al-time determinism for critical tasks. Task execution rates, operating system (OS) overhead, and task context switching times are just a few of the parameters that can cause jitter and missed deadlines in RTS with soft schedulers. Control systems that are susceptible to jitter can be used in the control of HARD RTS as long as the cumulative value of periodicity deviation and worst-case response time is less than the response time required by that application. This artcle presents field-programmable gate array (FPGA) soft-core processors integration based on different instruction set architectures (ISA), custom central processing unit (CPU) datapath, dedicated hardware thread context, and hardware real-time operating system (RTOS) implementations. Based on existing work problems, one parameter that can negatively influence the performance of an RTS is the additional costs due to the operating system. The scheduling and thread context switching operations can significantly degrade the programming limit for RTS, where the task switching frequency is high. In parallel with the improvement of software scheduling algorithms, their implementation in hardware has been proposed and validated to relieve the processor of scheduling overhead and reduce RTOS-specific overhead.

Deadline-Aware Online Scheduling of TSN Flows for Automotive Applications

The Time-Sensitive Networking (TSN) set of standards allows to support on the same channel the different kinds of traffic flows that are typically found in automotive scenarios. This article proposes the introduction of online Earliest Deadline First-based scheduling in TSN to provide support for event-driven real-time traffic. The proposed approach, called Deadline-TSN, is an online approach, and therefore, unlike other approaches in the literature, it does not require complex offline schedule calculations. Moreover, Deadline-TSN is able to uniformly deal with real-time periodic and event-driven traffic flows. This article presents Deadline-TSN and provides both worst-case response time analysis and simulative assessments in realistic automotive scenarios.

Comparing the Worst-Case Response Time of Complex Intersections Management

Comparing the Worst-Case Response Time of Complex Intersections Management

Toward Minimum WCRT Bound for DAG Tasks Under Prioritized List Scheduling Algorithms

Many modern real-time parallel applications can be modeled as a directed acyclic graph (DAG) task. Recent studies show that the worst-case response time (WCRT) bound of a DAG task can be significantly reduced when the execution order of the vertices is determined by the priority assigned to each vertex of the DAG. How to obtain the optimal vertex priority assignment, and how far from the best-known WCRT bound of a DAG task to the minimum WCRT bound are still open problems. In this article, we aim to construct the optimal vertex priority assignment and derive the minimum WCRT bound for the DAG task. We encode the priority assignment problem into an integer linear programming (ILP) formulation. To solve the ILP model efficiently, we do not involve all variables or constraints. Instead, we solve the ILP model iteratively, i.e., we initially solve the ILP model with only a few primary variables and constraints, and then at each iteration, we increment the ILP model with the variables and constraints which are more likely to derive the optimal priority assignment. Experimental work shows that our method is capable of solving the ILP model optimally without involving too many variables or constraints, e.g., for instances with 50 vertices, we find the optimal priority assignment by involving 12.67% variables on average and within several minutes on average.

How windows size and number can influence the schedulability of hierarchically-scheduled time-partitioned distributed real-time systems

Partitioning techniques are implemented in the development of safety-critical applications to ensure isolation among components. An adequate scheduling of the execution of such partitions is a key challenge so that applications meet the hard deadlines imposed. In this work, we study the effect of different partition window configuration parameters, with the aim of analyzing their impact in the worst-case response times of system tasks. This is the first step in the development of an algorithm for optimizing partition windows in hierarchically-scheduled time partitioned distributed systems.

Schedulability analysis for 3-phase tasks with partitioned fixed-priority scheduling

Multicore platforms are being increasingly adopted in Cyber-Physical Systems (CPS) due to their advantages over single-core processors, such as raw computing power and energy efficiency. Typically, multicore platforms use a shared memory bus that connects the cores to the off-chip main memory. This sharing of memory bus may cause tasks running on different cores to compete for access to the main memory whenever data/instructions are need to be read/written from/to the main memory. Such competition is problematic, as it may cause variations in the execution time of tasks in a non-deterministic way. To reduce the complexity of analyzing this problem, the 3-phase task model was proposed that divides tasks’ executions into distinct memory and execution phases. The distinctive memory phases are then scheduled to eliminate/minimize main memory contention between concurrently executing tasks. However, 3-phase tasks running on different cores may still compete to access the shared memory bus/main memory in order to execute memory phases. This paper presents a partitioned scheduling-based approach that allows one to derive memory bus contention-aware worst-case response time of tasks that follow the 3-phase task model. In particular, the bus-contention analysis is derived by considering two memory access models, i.e., (i) dedicated memory access model, where a core having allowed to access the main memory via memory bus is permitted to execute more than one memory phase, and (ii) fair memory access model, that restrict each core to execute only one memory phase in its allocated bus access. Both these models represent different system and application requirements, and the resulting bus contention of tasks may vary depending on the considered model. To evaluate the effectiveness of the proposed bus contention analysis, we compare its performance against an existing analysis in the state-of-the-art by performing (i) case-study experiments, using benchmarks from the Mälardalen Benchmark suite, and (ii) empirical evaluation using synthetic task sets. Results show that our proposed analysis can improve task set schedulability of 3-phase tasks by up to 88 percentage points.

Improving Interference Analysis for Real-Time DAG Tasks Under Partitioned Scheduling

Real-time systems with strict timing constraints have been widely applied in many fields. The Directed acyclic graph (DAG) task model has been widely studied and applied to model real-time systems with partial parallelism and precedence constraints in each task. Our paper focuses on the worst-case response time (WCRT) analysis of DAG tasks under partitioned scheduling on multiprocessors. We investigate a parallel structure named <formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex>$Str$</tex> </formula> , which helps obtain more accurate analysis results, and propose a new offline scheduling analysis algorithm named reducing repetitive calculation (RRC). Experiments with synthetic workload are conducted to compare the results calculated by RRC and the state-of-the-art, as well as the observed average response time on a real embedded system. Results show that RRC has better performance in terms of analysis accuracy.

Determining rate monotonic schedulability of real-time periodic tasks using continued fractions

Fixed-priority scheduling algorithms are widely used for real-time systems with a single processor because of their implementation simplicity and relatively low run-time overheads. However, determining whether a task set is schedulable by a fixed-priority scheduling algorithm has been shown to be NP-hard. There are few exact schedulability test methods such as the time demand analysis or the worst-case response time analysis for Rate Monotonic scheduling, while much research has been done to find a tighter sufficient condition for the fixed-priority schedulability. In this paper, a new approach to analyze the schedulability of fixed-priority scheduling using well-known mathematical tool called continued fractions is presented. With continued fractions, a new schedulability test for Rate Monotonic algorithm is derived. The schedulability test condition is an exact condition that can be applied tasks with total utilization less than 1.

A New Scheduling Algorithm for Shortening Response Time of Static Priority Task

In scheduling algorithms based on the Rate Monotonic (RM) method which are widely used in development of real-time systems, tasks with shorter periods have higher priorities. In contrast, ones with longer periods are likely to suffer from increased response times and jitter due to their lower priorities. We propose an Execution Right Delegation (ERD) method based on RM where a high-priority server for particular (or important) task is introduced to shorten response time and jitter of the task. In the evaluation, it is confirmed that response times and jitter of a particular (important) task are reduced. We also show Response Time Analysis (RTA), which assures worst-case response time of the task. This paper shows the algorithm and RTA of ERD and evaluates it by comparing it to a Deadline Monotonic method. The evaluation by simulation shows that ERD can reduce the average worst-case response time by 13.45% at maximum compared to the Deadline Monotonic scheduling. In addition, we confirm that the RTA provides a worst-case response time close to the simulation results.

A New Scheduling Algorithm for Shortening Response Time of Static Priority Task

In scheduling algorithms based on the Rate Monotonic (RM) method which are widely used in development of real-time systems, tasks with shorter periods have higher priorities. In contrast, ones with longer periods are likely to suffer from increased response times and jitter due to their lower priorities. We propose an Execution Right Delegation (ERD) method based on RM where a high-priority server for particular (or important) task is introduced to shorten response time and jitter of the task. In the evaluation, it is confirmed that response times and jitter of a particular (important) task are reduced. We also show Response Time Analysis (RTA), which assures worst-case response time of the task. This paper shows the algorithm and RTA of ERD and evaluates it by comparing it to a Deadline Monotonic method. The evaluation by simulation shows that ERD can reduce the average worst-case response time by 13.45% at maximum compared to the Deadline Monotonic scheduling. In addition, we confirm that the RTA provides a worst-case response time close to the simulation results.

Dynamic Performance Analysis of STEP System in Internet of Vehicles Based on Queuing Theory.

The Internet of vehicles (IoV) is an important research area of the intelligent transportation systems using Internet of things theory. The complex event processing technology is a basic issue for processing the data stream in IoV. In recent years, many researchers process the temporal and spatial data flow by complex event processing technology. Spatial Temporal Event Processing (STEP) is a complex event query language focusing on the temporal and spatial data flow in Internet of vehicles. There are four processing models of the event stream processing system based on the complex event query language: finite automata model, matching tree model, directed acyclic graph model, and Petri net model. In addition, the worst-case response time of the event stream processing system is an important indicator of evaluating the performance of the system. Firstly, this paper proposed a core algorithm of the temporal and spatial event stream processing program based on STEP by Petri net model. Secondly, we proposed a novel method to estimate the worst-case response time of the event stream processing system, which is based on stochastic Petri net and queuing theory. Finally, through the simulation experiment based on queuing theory, this paper proves that the data stream processing system based on STEP has good dynamic performance in processing the spatiotemporal data stream in Internet of vehicles.

Response time analysis of parallel tasks on accelerator-based heterogeneous platforms

Due to the inherent high parallelism and heterogeneity, accelerator-based heterogeneous platforms have been regarded as promising solutions for computation-intensive applications. With respect to latency and power consumption, accelerator often performs better than general-purpose processors. The directed acyclic graph (DAG) model is widely used to represent parallel applications, where each vertex represents an independent workload and each edge represents the precedence constraint between two vertices. The response time analysis of DAG tasks is of paramount importance to the judgment of task schedulability. However, the existing response time analysis method of DAG tasks on accelerator-based heterogeneous platforms just offloading one vertex to the accelerator cannot comply with the actual application scenarios. The well-known worst-case response time (WCRT) bounds of DAG tasks on heterogeneous platforms are pessimistic for judging the task schedulability. This paper studies the response time analysis method of DAG tasks that offload multiple vertices to the accelerator. We transform the graph structure of the DAG task to reduce the interference of vertices running on the accelerator to vertices on the general-purpose processor. Finally, we propose a new WCRT bound for the transformed DAG. The experimental results show that the new WCRT bound is more precise than the existing bounds of DAG tasks.

MIAT Efficient analysis of adaptive variable-rate tasks

Response time analysis of adaptive variable-rate tasks (AVR tasks) is a challenging problem in automotive real-time systems. While in periodic event-triggered systems, the worst-case response time is easy to determine, the analysis of AVR tasks has to deal with an exponentially growing number of combinations of execution paths. Each execution path has a specific dynamic behavior. In this paper, we present a new approach for reducing the number of potential worst-case combinations by introducing an intuitive view on the relation of start and end speeds given by speed-phase diagram. Here we propose a minimal inter-arrival time algorithm (MIAT) which is built on time constant lines (isochrones) in a speed-phase diagram first introduced in this work. Compared with previous work, the MIAT algorithm is more accurate and shows a significant improvement in runtime.

Computing exact WCRT for typed DAG tasks on heterogeneous multi-core processors

Heterogeneous multi-core architectures achieve high performance and energy efficiency in real-time domain towards various applications. Most real-time parallel applications on heterogeneous multi-cores can be modeled as a typed directed acyclic graph (DAG) task, where the workload of each vertex is only allowed to execute on a particular type of core. Traditional worst-case response time (WCRT) analysis methods for these applications modeled as DAG are very pessimistic and impractical, i.e., there is a big gap between existing WCRT bounds and the exact WCRT. In this paper, we propose a satisfiability modulo theories-based method to exactly analyze the WCRT of the typed DAG task scheduled upon heterogeneous multi-cores. Experimental results show that our method can significantly improve the precision of the WCRT, and thus, dramatically increase the acceptance rate in the schedulability analysis.

Worst-Case Response Time Analysis of Multitype DAG Tasks Based on Reconstruction

With the wide application of heterogeneous multi-core processor real-time systems, the existing analysis methods of worst-case response time (WCRT) overestimate the blocking information among tasks, resulting in a rather pessimistic estimation. To improve the accuracy of the WCRT, we propose a reconstruction-based WCRT analysis method for multi-type directed acyclic graph (DAG) tasks scheduling algorithm(RMDS). The RMDS algorithm comprises the following steps: First, we unitize all task nodes in the multi-type DAG task; Then, we use key factors as task priorities to schedule tasks and reconstruct the DAG task model into a parallel node segment model; Finally, we estimate the WCRT of multi-type DAG tasks according to the parallel node segment model to assess task schedulability. To verify the performance of our algorithm, we compared it with traditional algorithms. RDMS showed an acceptance rate 6.13% higher and its overall performance increased by 25.95% in comparison with traditional algorithms.