Worst-case Execution Time Research Articles

Analysis of benchmark program results of worst case execution time for multithreaded programs

<span lang="EN-US">Worst case execution time (WCET) estimation by static analyzers is being investigated with keen interest in view of their importance in designing applications for embedded systems that have real- time requirements. Recent work reported on improving precision of estimates of WCET of multithreaded programs, by improving precision of shared instruction cache analysis, shows significant improvement in WCET estimates. An abstraction of a multithreaded program as Hoare’s communicating sequential processes (CSP) specification program is realized to enable higher precision in micro-architectural modelling unit of WCET analyzer of multithreaded programs. A thread is viewed as a composition of CSP. The WCET of a thread may be viewed as dependent on WCET of processes in a thread and in turn WCET of each process is the WCET of the sub-graph of basic block nodes in the process. Corresponding CSP in interacting threads, based on calls to synchronization primitives wait and notify, generate shared cache interferences to the process in a thread whose WCET is being estimated by the analyzer. A detailed study of how partitioning of a thread into processes yields higher reduction in WCET is performed on benchmark programs. Furthermore, which processes in a thread yield higher reduction in WCET is performed.</span>

Multitimescale Mitigation for Performance Variability Improvement in Time-Critical Systems

Ensuring a timing guarantee is crucial for time-critical applications. However, this task becomes more challenging with the increasing performance variability generated by complicated modern hardware and software. A widespread solution to the problem is real-time scheduling, which depends on worst-case execution time (WCET) and dynamic voltage frequency scaling (DVFS). Although these techniques provide the necessary guarantees, they also exhibit important limitations from the long switching time of DVFS and the overly pessimistic execution time model of WCET. In this work, a multitimescale mitigation methodology is proposed to improve the way of tackling performance variability in both timing guarantee and energy saving. By using both the DVFS and heterogeneous datapath (HDP) knobs, this methodology can push the timescale of mitigation down to the submillisecond level. Moreover, this methodology can calculate a tight upper bound of execution time at run-time using dynamic scenarios (DSs). Simulation shows that the proposed methodology can ensure zero deadline misses with a smaller safety time margin than the method using only DVFS and WCET. This advantage can translate into an energy reduction by half compared to the conventional WCET-based method with a single DVFS knob.

Reducing the fault vulnerability of hard real-time systems

With the progress of the technology, the presence of transient faults (e.g. bit-flipping errors) in cache memories becomes a challenge, especially in embedded real-time systems. These are mission critical systems that are often subject to both fault-tolerant and real-time constraints.To reduce the impact of transient faults, hardware protection mechanisms are usually proposed. However, these mechanisms introduce too much pessimism in the computation of the worst-case execution time of a task, decreasing the overall system performance.In this paper, we propose a methodology to evaluate and reduce the vulnerability of hard real-time applications to soft errors in IL1 cache memories.We use static analysis tools to analyze a binary program and compute the overall vulnerability of its instructions. Then, we propose to reduce this vulnerability by invalidating some cache blocks at specific instants during the execution, thus forcing vulnerable instruction blocks to be reloaded from higher layers of memory. Since adding invalidation points will likely increase the WCETs of the tasks, we perform a static analysis to guarantee that the application deadlines are respectedFinally, we analyze how our methodology can be combined with hardware protection mechanisms as ECC memories, and we evaluate the performance on a set of benchmarks.

BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems

An increasing trend for reducing cost, space, and weight leads to modern embedded systems that execute multiple tasks with different criticality levels on a common hardware platform while guaranteeing a safe operation. In such mixed-criticality (MC) systems, multiple worst case execution times (WCETs) are defined for each task, corresponding to the system operation mode to improve the MC system’s timing behavior at runtime. Determining the appropriate WCETs for lower criticality (LC) modes is nontrivial. On the one hand, considering a very low WCET for tasks can improve the processor utilization by scheduling more tasks in that mode, on the other hand, using a larger WCET ensures that the mode switches (which causes by task overrunning) are minimized, thereby improving the quality of service for all tasks, albeit at the cost of processor utilization. Hitherto, no analytical solutions are proposed to determine WCETs in LC modes. In this regard, we propose a scheme to determine WCETs by the Chebyshev theorem, to make a tradeoff between the number of scheduled tasks at design-time and the number of dropped low-criticality tasks at runtime as a result of frequent mode switches. To have a tight bound of execution times and mode switching probability, we also propose a distribution analytics-based scheme, in which the mode switching probability is obtained based on the cumulative distribution function. Our experimental results show that our scheme improves the utilization of state-of-the-art MC systems by up to 72.27%, while maintaining 24.28% mode switching probability in the worst case scenario. Besides, the results of running embedded real-time benchmarks on a real platform show that the distribution-based scheme can improve the utilization by 7.30% while bounding the mode switching probability by 4.85% more, compared to the Chebyshev-based scheme.

Sampling Rate Optimization and Execution Time Analysis for Two-Degrees-of-Freedom Control Systems

The current journal paper proposes an end-to-end analysis for the numerical implementation of a two-degrees-of-freedom (2DOF) control structure, starting from the sampling rate selection mechanism via a quasi-optimal manner, along with the estimation of the worst-case execution time (WCET) for the specified controller. For the sampling rate selection, the classical Shannon–Nyquist sampling theorem is replaced by an optimization problem that encompasses the trade-off between the fidelity of the controllers’ representation, along with the fidelity of the resulting closed-loop systems, and the implementation difficulty of the controllers. Additionally, the WCET analysis can be seen as a verification step before automatic code generation, a computational model being provided. The proposed computational model encompasses infinite-impulse response (IIR) and finite-impulse response (FIR) filter models for the controller implementation, along with additional relevant phenomena being discussed, such as saturation, signal scaling and anti-windup techniques. All proposed results will be illustrated on a DC motor benchmark control problem.

Using Python Modules in Real-Time Plasma Systems for Fusion.

One of the most important applications of sensors is feedback control, in which an algorithm is applied to data that are collected from sensors in order to drive system actuators and achieve the desired outputs of the target plant. One of the most challenging applications of this control is represented by magnetic confinement fusion, in which real-time systems are responsible for the confinement of plasma at a temperature of several million degrees within a toroidal container by means of strong electromagnetic fields. Due to the fast dynamics of the underlying physical phenomena, data that are collected from electromagnetic sensors must be processed in real time. In most applications, real-time systems are implemented in C++; however, Python applications are now becoming more and more widespread, which has raised potential interest in their applicability in real-time systems. In this study, a framework was set up to assess the applicability of Python in real-time systems. For this purpose, a reference operating system configuration was chosen, which was optimized for real time, together with a reference framework for real-time data management. Within this framework, the performance of modules that computed PID control and FFT transforms was compared for C++ and Python implementations, respectively. Despite the initial concerns about Python applicability in real-time systems, it was found that the worst-case execution time (WCET) could also be safely defined for modules that were implemented in Python, thereby confirming that they could be considered for real-time applications.

Wfspan: Wait-free Dynamic Memory Management

Dynamic memory allocation plays a vital role in modern application programs. Modern lock-free memory allocators based on hardware atomic primitives usually provide good performance. However, threads may starve in these lock-free implementations, leading to unbounded worst-case execution time that is not allowed in real-time embedded systems. This article presents decentralized dynamic memory management, wfspan, based on non-linearizable wait-free lists. It employs a helping mechanism to ensure no starvation in the lock-free implementation. From the perspective of design tradeoff, wfspan guarantees bounded execution steps in both allocation and deallocation procedure, at the cost of increasing bounded worst-case memory footprint. The results of running benchmarks on an x86/64 and an aarch64 machine illustrate that wfspan achieves competitive performance and memory footprint compared to lock-based and lock-free practical memory allocators while showing superior to other allocators in terms of worst-case execution time.

Towards an energy-efficient quarter-clairvoyant mixed-criticality system

Mode switch is the key strategy in mixed-criticality systems, enabling a dynamic balance between system performance and safety. Mode switch in conventional MCS frameworks is always triggered by over-execution of a task, i.e., a task overrunning the less pessimistic worst-case execution time. In cyber–physical systems, the data volume generated by I/O affects and even dominates task execution time. Based on this observation, we propose a novel MCS framework, named Pythia-MCS, which predicts task execution time according to I/O run-time behaviors. With the new feature of future-prediction, Pythia-MCS provides more timely, but still accurate, mode switches. We specifically introduce the Pythia-MCS design methods, including different allocations of I/O monitoring and an efficient energy management framework. We present a new theoretical model (quarter-clairvoyance), which guarantees the timing predictability of the design, and a new schedulability analysis for Pythia-MCS, which demonstrates improved schedulability compared to conventional MCS frameworks. In addition, Pythia-MCS is comprehensively evaluated using a number of metrics.

Accounting for Preemption and Migration Costs in the Calculation of Hard Real-Time Cyclic Executives for MPSoCs

This work introduces a methodology to consider preemption and migration overhead in hard real-time cyclic executives on multicore architectures. The approach performs two iterative stages. The first stage takes a cyclic executive, from which the number and timing of all preemptions and migrations for every task is known. Then, it includes this overhead by updating the worst-case execution time (WCET) of the tasks. The second stage calculates a new cyclic executive considering the new WCET of tasks. The stages iterate until the preemption and migration overhead keeps constant.

A Framework for Calculating WCET Based on Execution Decision Diagrams

Due to the dynamic behaviour of acceleration mechanisms such as caches and branch predictors, static Worst-case Execution Time (WCET) analysis methods tend to scale poorly to modern hardware architectures. As a result, a trade-off must be found between the duration and the precision of the analysis, leading to an overestimation of the WCET bounds. In turn, this reduces the schedulability and resource usage of the system. In this article, we present a new data structure to speed up the analysis: the eXecution Decision Diagram (XDD), which is an ad hoc extension of Binary Decision Diagrams tailored for WCET analysis problems. We show how XDDs can be used to represent efficiently execution states in a modern hardware platform. Moreover, we propose a new process to build the Integer Linear Programming system of the Implicit Path Enumeration Technique using XDD. We use benchmark applications to demonstrate how the use of an XDD substantially increases the scalability of WCET analysis and the precision of the obtained WCET.

Optimized partitioning and priority assignment of real-time applications on heterogeneous platforms with hardware acceleration

Hardware accelerators, such as those based on GPUs and FPGAs, offer an excellent opportunity to efficiently parallelize functionalities. Recently, modern embedded platforms started being equipped with such accelerators, resulting in a compelling choice for emerging, highly computational intensive workloads, like those required by next-generation autonomous driving systems. Alongside the need for computational efficiency, such workloads are commonly characterized by real-time requirements, which need to be satisfied to guarantee the safe and correct behavior of the system. To this end, this paper proposes a holistic framework to help designers partition real-time applications on heterogeneous platforms with hardware accelerators. The proposed model is inspired by a realistic setup of an advanced driving assistance system presented in the WATERS 2019 Challenge by Bosch, further generalized to encompass a broader range of heterogeneous architectures. The resulting analysis is linearized and used to encode an optimization problem that jointly (i) guarantees timing constraints, (ii) finds a suitable task-to-core mapping, (iii) assigns a priority to each task, and (iv) selects which computations to accelerate, seeking for the most convenient trade-off between the smaller worst-case execution time provided by accelerators and synchronization and queuing delays.

Response time analysis of memory-bandwidth-regulated multiframe mixed-criticality systems

The multiframe mixed-criticality task model eliminates the pessimism in many systems where the worst-case execution times (WCETs) of successive jobs vary greatly by design, in a known pattern. Existing feasibility analysis techniques for multiframe mixed-criticality tasks are shared-resource-oblivious, hence unsafe for commercial-off-the-shelf (COTS) multicore platforms with a memory controller shared among all cores. Conversely, the feasibility analyses that account for the interference on shared resource(s) in COTS platforms do not leverage the WCET variation in multiframe tasks. This paper extends the state-of-the-art by presenting an analysis that incorporates the memory access stall in memory-bandwidth-regulated multiframe mixed-criticality multicore systems. An exhaustive enumeration approach is proposed for this analysis to further enhance the schedulability success ratio. The running time of the exhaustive analysis is improved by proposing a pruning mechanism that eliminates the combinations of interfering job sequences that subsume others. Experimental evaluation, using synthetic task sets, demonstrates up to 72% improvement in terms of schedulability success ratio, compared to frame-agnostic analysis.

Compiler-assisted energy reduction of java real-time programs

Optimizations in energy consumption are critical for battery-powered hard real-time embedded systems. Energy management is often accomplished by dynamic frequency scaling which requires compilers to insert special instructions in the code at appropriate places, which are then used by the operating system and the processor to calculate and change the frequency at these places in the code. The addition of code snippets for frequency change may affect the worst-case execution time of the program, which is a major concern for hard real-time systems. In addition to the above problem, run time calculation of the optimal frequency prohibits a compile-time estimate of the battery life by the system designers. In this paper, we present compiler optimizations for hard real-time Java applications executing on a time predictable Java processor, which reduces the energy consumption of the program while retaining the original worst-case execution time for the program intact. We also generate a compile-time frequency change schedule for the program resulting in compile-time estimates for worst-case energy consumption. We found that on average, reduction in energy consumption is better in run-time frequency schedule based mechanism but the compile-time frequency schedule allows us to get bounds on energy consumption at the compile-time.

Hybrid probabilistic timing analysis with Extreme Value Theory and Copulas

The primary challenge of time-critical systems is to guarantee that a task completes its execution before its deadline. In order to ensure compliance with timing requirements, it is necessary to analyze the timing behavior of the overall software. Worst-Case Execution Time (WCET) represents the maximum amount of time an individual software unit takes to execute and is used for scheduling analysis in safety-critical systems. Recent studies focus on statistical approaches, which augments measurement-based timing analysis with probabilistic confidence level by applying stochastic methods. Common approaches either utilize Extreme Value Theory (EVT) for end-to-end measurements or convolution techniques for a group of program units to derive probabilistic upper bounds for the program. The former method does not ensure path coverage while the latter suffers from ignoring possible extreme cases. Furthermore, current state-of-the-art convolution methods employed in a commercial WCET analysis tool overestimates the results because of using the assumption of worst-case dependence between basic blocks. In this paper, we propose a hybrid probabilistic timing analysis framework and modeling the program units with EVT to capture extreme cases and use Copulas to model the dependency between the units to derive tighter distributional bounds in order to mitigate the effects of co-monotonic assumptions.

A Flexible Communication Protocol With Guaranteed Determinism for Distributed, Safety-Critical Real-Time Systems

Dependable, safety-critical real-time (SCRT) systems are becoming increasingly important and complex. Examples of such systems are autonomous or self-driving cars which are poised to revolutionise the transport industry. A critical part of these SCRT systems is the network communication protocol that is used by components in an SCRT system to exchange data. Communication protocols for SCRT systems are required to exhibit predictable, worst-case execution times and thus have to be designed in a more static and less flexible way. To ensure this predictability, current state-of-art communication protocols for SCRT systems are based on the Time-Triggered Architecture (TTA), where static and equal-length time-slots are used for all nodes to access the communication channel, irrespective of the size of their transmission payload. This determinism forms the basis of predictable timing, behaviour and fault tolerance. However, this determinism comes at the cost of poor channel and bandwidth utilisation, which hinders the development of SCRT systems. In this paper, we propose a more flexible approach, INCUS+, that allocates the slot length of a node based on its transmission requirements in a Time Division Multiple Access (TDMA) round. We achieve this while retaining the level of dependability required for SCRT systems and ensuring fail-silence. We validate this through formal verification of the timing parameters for the transmission windows of all participating nodes as well as independent bus guardians. Our design exhibits a significant improvement in bandwidth and channel utilisation, as we demonstrate in an autonomous vehicle case study.

Bus-contention aware WCRT analysis for the 3-phase task model considering a work-conserving bus arbitration scheme

Nowadays multicore processors are used in most modern systems. However, their applicability in systems with stringent timing requirements is still ongoing research. The main reason behind this is the difficulty of ensuring the timing correctness of tasks executing on such systems as they comprise a number of shared hardware resources, as for instance, caches, memory bus, and the main memory. Concurrent accesses to any of these shared resources can generate uncontrolled interference, which complicates the estimations of the worst-case execution time and the worst-case response time of tasks. The use of the 3-phase task execution model helps in upper bounding the contention due to the sharing of bus/main memory in multicore systems. This model divides the execution time of tasks into distinct memory and execution phases, where tasks can only access the bus/main memory during their memory phases. This makes bus and memory access patterns of tasks predictable by enabling a precise computation of bus/memory contention. In this work, we show how the bus contention can be computed for the 3-phase task model considering a round-robin-based arbitration policy at the memory bus. We differ from existing works that analyze the time-division multiple access and first-come-first-serve-based bus arbitration policies. First, we present a solution that models the bus contention that can be suffered/caused by tasks executing on the same/remote cores of a multicore system under an RR-based bus arbitration scheme. Then, the impact of the resulting bus contention on taskset schedulability is evaluated. Experimental results show that our proposed RR-based bus contention analysis can improve taskset schedulability by up to 100 percentage points when compared to a state-of-the-art TDMA-based analysis, and up to 40 percentage points when compared to the state-of-the-art FCFS-based bus contention analysis.

Software-Level Memory Regulation to Reduce Execution Time Variation on Multicore Real-Time Systems

Modern real-time embedded systems are equipped with multi-core processors to execute computationally intensive tasks. In multi-core architecture, last-level cache memory is shared by cores. The shared cache becomes a non-deterministic resource, which affects the independent execution of real-time tasks. We propose a solution to remedy a variation in execution time when interference happens in a shared cache. Current solutions have relied on memory scheduling approaches that avoid concurrent memory access to guarantee deterministic execution time. However, these methods required complex analysis to accurately estimate the worst-case execution time and to schedule tasks in an overly conservative manner. Unlike existing works, the proposed method prevents simultaneous memory access using the side effect of memory barriers rather than the complicated analysis. A memory barrier is inserted based on a simple code analysis that is performed in units of basic blocks using the LLVM compiler. The proposed method not only does not require the modification of the operating system or task execution flow but also relatively shows fast analysis time. Experimental results show that the proposed basic block-based memory barrier insertion method can reduce the variation in execution time by up to 80% when interference occurs.

Supporting Swap in Real-Time Task Scheduling for Unified Power-Saving in CPU and Memory

As the size of data grows rapidly in modern IoT (Internet-of-Things) and CPS (Cyber-Physical System) applications, the memory power consumption of real-time embedded systems increases dramatically. Unlike general-purpose systems where memory consumes about 10% of the CPU power consumption, modern real-time systems have the memory power of 20–50% of CPU power. This is because the memory size of a real-time system should be large enough to accommodate the entire task set, and thus DRAM refresh operations become a major source of power consumption. In this article, we present a new swap scheme for real-time systems, which aims at reducing memory power consumption. To support swap with real-time constraints, we adopt high-speed NVM storage and co-optimize power-savings in CPU and memory. Unlike traditional real-time task models that only consider the executions in CPU, we define an extended task model that characterizes memory and storage paths of tasks as well, and tightly evaluate the worst-case execution time by formulating the overlapped latency between CPU and memory. By optimizing the CPU supply voltage and the memory swap ratio of given task set, our scheme reduces the energy consumption of real-time systems by 31.1% on average under various workload conditions.

A generic framework to integrate data caches in the WCET analysis of real-time systems

Worst-case execution time (WCET) analysis of systems with data caches is one of the key challenges in real-time systems. Caches exploit the inherent reuse properties of programs by temporarily storing certain memory contents near the processor, in order that further accesses to such contents do not require costly memory transfers. Current worst-case data cache analysis methods focus on specific cache organizations (set-associative LRU, locked, ACDC, etc.), most of the times adapting techniques designed to analyze instruction caches. On the other hand, there are methodologies to analyze the data reuse of a program, independently of the data cache. In this paper we propose a generic WCET analysis framework to analyze data caches taking profit of such reuse information. It includes the categorization of data references and their integration in an IPET model. We apply it to a conventional LRU cache, an ACDC, and other baseline systems, and compare them using the TACLeBench benchmark suite. Our results show that persistence-based LRU analyses dismiss essential information on data, and a reuse-based analysis improves the WCET bound around 17% in average. In general, the best WCET estimations are obtained with optimization level 2, where the ACDC cache performs 39% better than a set-associative LRU.

Big data-driven scheduling optimization algorithm for Cyber–Physical Systems based on a cloud platform

In this paper, we study big data-driven Cyber–Physical Systems (CPS) through cloud platforms and design scheduling optimization algorithms to improve the efficiency of the system. A task scheduling scheme for large-scale factory access under cloud–edge collaborative computing architecture is proposed. The method firstly merges the directed acyclic graphs on cloud-side servers and edge-side servers; secondly, divide the tasks using a critical path-based partitioning strategy to effectively improve the allocation accuracy; then achieves load balancing through reasonable processor allocation, and finally compares and analyses the proposed task scheduling algorithm through simulation experiments. The experimental system is thoroughly analysed, hierarchically designed, and modelled, simulated, and the experimental data analysed and compared with related methods. The experimental results prove the effectiveness and correctness of the worst-case execution time analysis method and the idea of big data-driven CPS proposed in this paper and show that big data knowledge can help improve the accuracy of worst-case execution time analysis. This paper implements a big data-driven scheduling optimization algorithm for Cyber–Physical Systems based on a cloud platform, which improves the accuracy and efficiency of the algorithm by about 15% compared to other related studies.