Bits In Worst Case Research Articles

12-nm Stable Pre-Amplifier Physical Unclonable Function With Self-Destruct Capability

Physical unclonable functions (PUFs) produce full security keys without needing to store the key directly in nonvolatile memory (NVM) or publicly. PUFs rely on a stable entropy source across voltage, temperature, and lifetime. A high-gain preamplifier (Pre-Amp) bit cell was built into a dense 2-D array configured as 16 cells per bitline (BL) and 64 cells per wordline (WL). A hardware (HW) sample of 40 chips (1 Kb/chip) was manufactured in GLOBAL FOUNDRIES (GF) 12-nm (12 lp) CMOS technology for a total raw bit count of 40 960 bits. HW characterization was performed to support power supply ranging from 0.7 to 1.0 V and junction temperatures ranging from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 40 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> C to 125 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> C with a worst case bit error rate (BER) of 0.174% after stabilization. The entropy source array is complete for productization with control logic and analog power system block for process, voltage, and temperature (PVT) compensation. A stable bit identification and sensing circuit is designed to identify bit cells that are robust against varied test conditions. The NIST 800-90B test suite was run on the native array and stable entropy source bits with minimum entropy scores of 0.65/bit and 0.697/bit, respectively. This article then introduces for the first time ever the ability for a PUF key to be corrupted and physically destroyed, which can be utilized to stop a tamper event or to corrupt obsolete chips. In the self-destruct (SD) mode, the entropy source data can be irreversibly destroyed, blocking all future authentication attempts. HW data show the before and after SD bitmaps, where electromigration (EM) physically breaks the connection of the entropy source bit cells from the sensing circuits. A safety lock circuit is also included to prevent inadvertent SD.

An Optically-Reconfigurable PUF Based on Logarithmic Photoreceptor of CMOS Dynamic Vision Sensors

In this brief, a novel optically-reconfigurable physical unclonable function (OR-PUF) is presented for CMOS dynamic vision sensor (DVS). By utilizing the in-pixel logarithmic photoreceptor’s spatial photoresponse nonuniformity (PRNU) as the entropy source, raw physical unclonable function (PUF) bits having high reliability and randomness can be generated with monochromatic illumination in visible spectrum. In addition, the proposed OR-PUF can be reconfigured to new challenge-response-pair (CRP) spaces under the illumination with different visible wavelengths. Moreover, the proposed implementation is validated by prototype chips fabricated using a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> standard CMOS process. Featuring excellent randomness by passing the widely-adopted National Institute of Standards and Technology (NIST) and autocorrelation function (ACF) test tools, the fabricated PUF chips exhibit a uniqueness of 49.37% and a worst case bit error rate (BER) of 1.93% under the voltage–temperature (VT) range of 0 °C–80 °C and 1.65–2.2 V.

PTOPO: Computing the geometry and the topology of parametric curves

We consider the problem of computing the topology and describing the geometry of a parametric curve in Rn. We present an algorithm, PTOPO, that constructs an abstract graph that is isotopic to the curve in the embedding space. Our method exploits the benefits of the parametric representation and does not resort to implicitization.Most importantly, we perform all computations in the parameter space and not in the implicit space. When the parametrization involves polynomials of degree at most d and maximum bitsize of coefficients τ, then the worst case bit complexity of PTOPO is O˜B(nd6+nd5τ+d4(n2+nτ)+d3(n2τ+n3)+n3d2τ). This bound matches the current record bound O˜B(d6+d5τ) for the problem of computing the topology of a plane algebraic curve given in implicit form. For plane and space curves, if N=max⁡{d,τ}, the complexity of PTOPO becomes O˜B(N6), which improves the state-of-the-art result, due to Alcázar and Díaz-Toca [CAGD'10], by a factor of N10. In the same time complexity, we obtain a graph whose straight-line embedding is isotopic to the curve. However, visualizing the curve on top of the abstract graph construction, increases the bound to O˜B(N7). For curves of general dimension, we can also distinguish between ordinary and non-ordinary real singularities and determine their multiplicities in the same expected complexity of PTOPO by employing the algorithm of Blasco and Pérez-Díaz [CAGD'19]. We have implemented PTOPO in maple for the case of plane and space curves. Our experiments illustrate its practical nature.

A Highly Reliable and Energy-Efficient Schmitt Trigger PUF Featuring Ultra-Wide Supply Voltage Range

In this brief, we present a Schmitt trigger physical unclonable function (ST-PUF) featuring high reliability under ultra-low supply voltage. By replacing the standard complementary-metal-oxide-semiconductor (CMOS) inverter of traditional static random access memory (SRAM) PUFs to ST inverter, the relatively large transition width can be significantly reduced by 1.91~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$121.8\times $ </tex-math></inline-formula> under different supply voltage and temperature (VT) conditions. This leads to dramatically enhanced reliability against the environmental noise and VT variations. The proposed implementation is validated using a 65-nm 1.2 V standard CMOS process, and the reference supply voltage is optimized to be 0.4 V, in order to strike an excellent balance between the power/energy consumption and the reliability. According to our extensive post-layout simulation results, the worst-case bit error rate (BER) is reported to be 2.14% with the supply voltage varying from 0.3 V to 0.5 V and the temperature varying from −40°C to 120°C. The core energy consumption is simulated to be 2.31 fJ/bit at a throughput of 160 Mb/s. Moreover, the generated raw PUF bits have passed both the National Institute of Standards and Technology (NIST) and auto-correlation function (ACF) randomness tests.

A CRP-Space-Extended RRAM PUF With In-Cell Zero-Overhead Salicide-Blocked Contact

In this brief, we present an ultracompact physical unclonable function (PUF) based on the resistive random access memory (RRAM) with the in-cell salicide-blocked (SAB) contact. Different from most previously reported RRAM PUFs with only the RRAM cell's high-resistance state (HRS) utilized as the static entropy, its low-resistance state (LRS) is enabled with the proposed SAB contact resistance as a novel entropy source. Concretely, by adding a photolithography mask of “SAB” that widely exists in standard CMOS process to the source/drain contact of the mainstream one-transistor-one-resistor (1T1R) RRAM cell's access transistor, an SAB contact featuring large resistance stochasticity can be formed with zero design overhead of silicon area. With the SAB contact resistance connected in series, both HRS and LRS can be well-exploited to generate much more challenge-response pairs (CRPs), leading to significantly extended CRP space. In addition, the proposed RRAM PUF with in-cell SAB contact is validated using 0.18- μm standard CMOS process plus postprocessing steps for RRAM devices, and the normalized bitcell area is reported to be 77 F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /bit. By varying the operating temperature from -50 °C to 150 °C, the worst case bit error rate (BER) is measured to be 0.13% at 150 °C. Moreover, the excellent randomness of the proposed implementation is verified by passing both the National Institute of Standards and Technology (NIST) test and the autocorrelation function (ACF) test.

A Wide-Range Variation-Resilient Physically Unclonable Function in 28 nm

This article presents a wide-range, variation-resilient physically unclonable function (PUF) to provide a reliable security primitive solution. The proposed ring oscillator-based PUF employs several stabilization techniques to maintain robustness under environmental variations. The proposed PUF design uses a delay cell topology with an adjusted signal slope to amplify the impact of device variability on delay mismatch. Moreover, an online calibration system that extracts in situ PUF delay information and re-configures stage interconnects is employed to further enlarge frequency mismatch and improve stability. Measurement results from a prototype fabricated in a 28-nm CMOS technology show that the proposed PUF design achieves a highly stable performance over a wide range of operating conditions, with a worst case bit error rate (BER) of 0.55% across 0.4–1.3 V and −40 to 125 °C. The measured BER sensitivities to supply voltage (0.0546%/0.1 V) and temperature (0.0052%/10 °C) demonstrate the stability improvements of 2.38 and 28.84 times, respectively, when compared with the state-of-the-art results.

Bit-Shuffle Coding for Flicker Mitigation in Visible Light Communication

Visible light communication (VLC) is a promising technology for both wireless communications and illumination via light-emitting diodes (LEDs). Although conventional run-length-limited (RLL) codes are employed to mitigate modulation-induced flickers, they can suffer from data rate reduction, worst-case bit sequences, and hardware overheads, resulting in a performance bottleneck. In this paper, we introduce a novel VLC data-encoding algorithm using bit shuffling to resolve these problems while alleviating light flickers. In contrast to existing RLL coding approaches, bit shuffling with an Omega network can generate codewords dynamically, which guarantees short runs of consecutive 0’s or 1’s, avoidance of worst-case bit sequences, and a relatively short code length. To illustrate the performance of hardware implementations, we discuss the hardware designs of the proposed bit-shuffle coding scheme. Our simulation results demonstrate the effectiveness of the bit-shuffle coding approach in terms of mitigation of flickering, transmission efficiency, and hardware overheads.

Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm

This paper presents a physically unclonable function (PUF) that can be designed with an automated digital design flow with a standard-cell approach. Compared to conventional PUFs designed in an analog or array style, the proposed PUF can be immersed in logic for inherent PUF obfuscation, and entails significantly lower design effort. The proposed PUF, belongs to the static monostable PUF class, is based on regulated cascode current mirrors (RCCM) and has hysteretic behavior to improve robustness against bit flips caused by noise, voltage, and temperature fluctuations. Hysteresis is achieved by inserting a Muller C-element in the PUF output stage and skewed inverters. The impact of temperature fluctuations on the stability is further reduced through a temperature compensation feedback loop. A 40-nm testchip was designed through a digital design flow based on the proposed PUF standard cell. Testchip measurements show native worst case bit error rate (BER) of 3.2% at 0.8–1.0-V voltage and 25 °C–85 °C temperature. A temperature sensitivity of 0.015%/°C in terms of PUF instability, an energy per bitcell of 1.02 fJ/b, and an autocorrelation function (ACF) of 0.00735 at 95% confidence are achieved, being the lowest reported to date. In view of the low design effort and low power consumption, the proposed PUF is amenable for low-cost and low-power systems on chip (SoC) (e. g., for Internet of Things applications).

End-to-End Error-Correcting Codes on Networks With Worst-Case Bit Errors

In highly dynamic wireless networks, communications face several challenges. In the first place, noise levels between nodes might be difficult to predict a priori . Besides, a Byzantine attacker hidden in the network, with knowledge of the network topology and observation of all transmissions, can choose arbitrary locations to inject corrupted packets. Considering that transmissions are usually in bits and hardware in wireless networks usually use modulation schemes with the size of modulation alphabet being powers of two, e.g. BPSK, QPSK, 16-QAM, 64-QAM, and so on, to address the above problem, we study coding for networks experiencing worst case bit errors, and with network codes over binary extension fields. We demonstrate that in this setup prior network error-correcting schemes can be arbitrarily far from achieving the optimal network throughput. A new transform metric for errors under the considered model is proposed. Using this metric, we replicate many of the classical results from coding theory. Specifically, new Hamming-type , Plotkin-type , and Elias-Bassalygo-type upper bounds on the network capacity are derived. A commensurate lower bound is shown based on Gilbert–Varshamov (GV)-type codes for error-correction. The GV codes used to attain the lower bound can be non-coherent, that is, they require neither prior knowledge of the network topology nor network coding kernels. We also propose a computationally efficient concatenation scheme. The rate achieved by our concatenated codes is characterized by a Zyablov-type lower bound. We provide a generalized minimum-distance decoding algorithm which decodes up to half the minimum distance of the concatenated codes. The end-to-end nature of our design enables our codes to be overlaid on the classical distributed random linear network codes. The other advantage of the end-to-end strategy over the link-by-link error-correction is that it reduces the computational cost at the internal nodes for performing error-correction.

Belated Analyses of Three Credit-Based Adaptive Polling Algorithms

We study the problem of credit-based adaptive polling in undirected arbitrary point-to-point asynchronous networks. Polling consists of two rounds, namely propagation (broadcast) and feedback (confirmation, response) rounds. By adaptive polling, a spanning tree of unknown topology is built dynamically during the propagation round, and feedback messages are free to choose their paths back to the initiator — a specific node who initiates the polling algorithm. The freedom in the feedback round relies on the use of credits in the propagation round. We re-visit three existing algorithms and analyse their average case communication bit complexities incurred by the credits in the propagation round, and these analyses match with the numerical results. We also give an optimal lower bound on the worst case bit message complexity for the case when the number of nodes in the network is unknown.

Solving bivariate systems using Rational Univariate Representations

Given two coprime polynomials P and Q in Z[x,y] of degree bounded by d and bitsize bounded by τ, we address the problem of solving the system {P,Q}. We are interested in certified numerical approximations or, more precisely, isolating boxes of the solutions. We are also interested in computing, as intermediate symbolic objects, rational parameterizations of the solutions, and in particular Rational Univariate Representations (RURs), which can easily turn many queries on the system into queries on univariate polynomials. Such representations require the computation of a separating form for the system, that is a linear combination of the variables that takes different values when evaluated at the distinct solutions of the system.We present new algorithms for computing linear separating forms, RUR decompositions and isolating boxes of the solutions. We show that these three algorithms have worst-case bit complexity O˜B(d6+d5τ), where O˜ refers to the complexity where polylogarithmic factors are omitted and OB refers to the bit complexity. We also present probabilistic Las Vegas variants of our two first algorithms, which have expected bit complexity O˜B(d5+d4τ). A key ingredient of our proofs of complexity is an amortized analysis of the triangular decomposition algorithm via subresultants, which is of independent interest.

An Integrated LVDS Transmitter–Receiver System With Increased Self-Immunity to EMI in 0.18-um CMOS

This paper presents the design of an integrated low-voltage differential signaling (LVDS) transmitter–receiver system with a superior immunity to electromagnetic interference (EMI). The effects of injected RF interference on the differential communication bus between the proposed and typical LVDS transmitter and receiver front-ends are presented and explained mathematically. The design of a proposed wide input common-mode range LVDS receiver with an increased noise margin is discussed in detail. Transverse electromagnetic (TEM) cell measurements confirm that the proposed LVDS transmitter–receiver yields a worst-case bit error rate (BER) of 0.1 for an injected 30-dBm EMI signal at 840 MHz, while the typical transmitter–receiver pair fails with a BER of 0.5 for EMI levels as low as 23 dBm at frequencies ranging from 650 to 800 MHz, 820 to 860 MHz, and at 560 MHz. The discussed LVDS transmitter–receiver circuits were designed using the UMC 0.18- $\mu \text{}$ m CMOS process with a supply voltage of 1.8 V.

Improved Generation of Identifiers, Secret Keys, and Random Numbers From SRAMs

This paper presents a method to simultaneously improve the quality of the identifiers, secret keys, and random numbers that can be generated from the start-up values of standard static random access memories (SRAMs). The method is based on classifying memory cells after evaluating their start-up values at multiple measurements in a registration phase. The registration can be done without unplugging the device from its application context, and with no need for a complex laboratory setup. The method has been validated experimentally with standard low-power SRAM modules in two different application specific integrated circuits (ASICs) fabricated with the 90-nm TSMC technology. The results show that with a simple registration the length of the identifiers can be reduced by 45%, the worst case bit error probability (which defines the complexity of the error correcting code needed to recover a secret key) can be reduced by 64%, and the worst case minimum entropy value is improved, thus reducing the number of bits that have to be processed to obtain full entropy by 81%. The method can be applied to standard digital designs by controlling the external power supply to the SRAM using software or by incorporating simple circuitry in the design. In the latter case, a module for implementing the method in an ASIC designed in the 90-nm TSMC technology occupies an active area of 42, $025~\mu \text{m}^{\mathrm {\mathbf {2}}}$ .

Computing separating linear forms for bivariate systems

A fundamental problem in computational geometry is the computation of the topology of a real algebraic plane curve given by its implicit equation, that is, the computation of a set of polygonal lines that approximates the curve while preserving its topology. A critical step in many algorithms computing the topology of a plane curve is the computation of the set of singular and extreme points (wrt x) of this curve, which is equivalent to the computation of the solutions of bivariate systems defined by the curve and some of its partial derivatives. In this presentation, we address the problem of computing a linear separating form of a system of two bivariate polynomials with integer coefficients, that is a linear combination of the variables that takes different values when evaluated at the distinct solutions of the system. In other words, a separating linear form defines a shear of the coordinate system that sends the algebraic system in generic position, in the sense that no two distinct solutions are vertically aligned. The computation of such linear forms is at the core of most algorithms that solve algebraic systems by computing rational parameterizations of the solutions and this is the bottleneck of these algorithms in terms of worst-case bit complexity. We first present for this problem, an algorithm of worst-case bit complexity OB(d 8 +dτ) where d and τ denote respectively the maximum degree and bitsize of the input polynomials (and where O refers to the complexity where polylogarithmic factors are omitted and OB refers to the bit complexity). This complexity improves by a factor d the best known complexity bound for this problem (in OB(d 10 + dτ)). Then, we show how, using a similar approach, we can obtain an algorithm that simplifies the previous one while decreasing its complexity to OB(d 7 + dτ) bit operations in the worst-case. This new algorithm also yields a probabilistic Las-Vegas algorithm of expected bit complexity OB(d 5 + dτ).

Separating linear forms and Rational Univariate Representations of bivariate systems

We address the problem of solving systems of bivariate polynomials with integer coefficients. We first present an algorithm for computing a separating linear form of such systems, that is a linear combination of the variables that takes different values when evaluated at distinct (complex) solutions of the system. In other words, a separating linear form defines a shear of the coordinate system that sends the algebraic system in generic position, in the sense that no two distinct solutions are vertically aligned. The computation of such linear forms is at the core of most algorithms that solve algebraic systems by computing rational parameterizations of the solutions and, moreover, the computation of a separating linear form is the bottleneck of these algorithms, in terms of worst-case bit complexity.Given two bivariate polynomials of total degree at most d with integer coefficients of bitsize at most τ, our algorithm computes a separating linear form of bitsize O(log⁡d) in O˜B(d8+d7τ) bit operations in the worst case, which decreases by a factor d2 the best known complexity for this problem (where O˜ refers to the complexity where polylogarithmic factors are omitted and OB refers to the bit complexity).We then present simple polynomial formulas for the Rational Univariate Representations (RURs) of such systems. This yields that, given a separating linear form of bitsize O(log⁡d), the corresponding RUR can be computed in worst-case bit complexity O˜B(d7+d6τ) and that its coefficients have bitsize O˜(d2+dτ). We show in addition that isolating boxes of the solutions of the system can be computed from the RUR with O˜B(d8+d7τ) bit operations in the worst case. Finally, we show how a RUR can be used to evaluate the sign of a bivariate polynomial (of degree at most d and bitsize at most τ) at one real solution of the system in O˜B(d8+d7τ) bit operations and at all the Θ(d2) real solutions in only O(d) times that for one solution.

Airgap Interconnects: Modeling, Optimization, and Benchmarking for Backplane, PCB, and Interposer Applications

Frequency and time domain models are developed for backplane (BP), printed circuit board (PCB), and silicon interposer (SI) links using six-port transfer matrices (ABCD matrices) for bumps, vias and connectors, and coupled multiconductor transmission lines for traces. The six-port transfer matrix approach enables easy computation of the transfer function, as well as near-end and far-end crosstalk. The intersymbol interference is accounted for by computing the pulse response for the worst case bit pattern. Furthermore, the models developed here are used to optimize the data-rate and trace width for each of the links, so that the aggregate bandwidth obtained per joule of energy supplied to the link is maximized. The modeling and optimization approach developed here serves as a good platform to compare the air-gap interconnects against BP, PCB, and SI interconnects on lossy dielectrics. It is shown that air-gap interconnects can provide an aggregate bandwidth improvement of 3x-4x for BP links at a comparable energy per bit, and a 5x-9x improvement in aggregate bandwidth of PCB links at the expense of 20% higher energy per bit. For SI links, airgap interconnects are shown to provide a 2x-3x improvement in aggregate bandwidth and a 1x-1.5x improvement in energy per bit.

A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS

An 8T SRAM fabricated in 45 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,$</tex> </formula> nm SOI CMOS exhibits voltage scalable operation from 1.2 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,$</tex></formula> V down to 0.57 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,$</tex></formula> V with access times from 400 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,$</tex> </formula> ps to 3.4 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,$</tex> </formula> ns. Timing variation and the challenge of low voltage operation are addressed with an AC-coupled sense amplifier. An area efficient data path is achieved with a regenerative global bitline scheme. Finally, a data retention voltage sensor has been developed to predict the mismatch-limited minimum standby voltage without corrupting the contents of the memory.

A programmable full clock rectifier and sample-and-hold amplifier for biomedical applications

Post-layout Monte Carlo analysis and characterization as function of temperature, process, and mismatch variations of a rail-to-rail full clock fully programmable differential rectifier and sample-and-hold amplifier (RSHA) for biomedical applications are presented in this paper. The RSHA is based on a class AB fully differential two-stage operational amplifier. It uses the Miller compensation capacitor to hold the output and a duplicate of the output stage to ensure proper offset cancellation and common-mode control. The circuit is designed and implemented using a 0.35 μm CMOS technology. Results show that the total harmonic distortion, for an almost rail-to-rail input swing at 10 kHz and at 100 kS/s is equivalent to more than 9 bits in worst case. The dc output offset is below 140 μV and the error introduced by the rectification with respect to the non rectified signal is less than ?100 dB. The power consumption is 3 mW with ±1.25 V supplies. The RSHA provides an output valid for more than 85% of the clock cycle.

Two-Dimensional Coding for Probe Recording on Magnetic Patterned Media

The effect of intertrack intersymbol interference in a magnetic patterned medium is studied. A 2-D channel code is proposed, dedicated to perpendicularly magnetized media without soft underlayer, which exhibit read pulses showing overshoot. Read pulse shapes were investigated using a magnetic-force microscope tip scanning the patterned medium row by row. To test different codes, a bit-detection simulation program was developed to generate large amounts of data on which bit error rates can be measured. Application of the 2-D channel code, which implies recording of particular dot positions with fixed bits (ones, zeros) resulted in the elimination of 2-D worst case bit patterns and a subsequent reduction of detected-bit errors. The accompanying redundancy of 22% is inevitable for this type of 2-D code

Media background effect on the performance in perpendicular recording

The worst case bit error rate performance degradation due to the effect of stray fields from the recording layer on the reading and writing processes has been measured for a perpendicular recording system. The system consists of a single pole writer with a conventional spin-value reader and a double layer recording medium. A new method is developed to distinguish the reading and writing effects separately by adjusting the write current time asymmetry. Both effects have also been measured by using the dipulse extraction method. The data show that the measured writing effect is correlated to the value which one gets from adjusting write current time asymmetry.