Wormhole Routing Research Articles

Hardware Compression Method for On-Chip and Interprocessor Networks with Wide Channels and Wormhole Flow Control Policy

Increasing the number of processing cores is currently a common way to boost processor performance. However, the load on the memory subsystem consequently increases as the number of its agents grows. Hardware data compression is an unconventional approach to improving memory subsystem performance by reducing, firstly, the main memory access rate by increasing the cache capacity and, secondly, data traffic by packing the data more densely. The paper describes the implementation of hardware data compression in the on-chip network and interprocessor links of a configuration with wide data transmission channels and a wormhole flow control policy. The existing solutions cannot be applied to such configurations because they are essentially based on using narrow data channels and flow control policies implying uninterrupted packet transmission, which is not maintained with the wormhole flow control. The method proposed in this paper enables the use of hardware compression in the aforementioned configuration by moving data compression and decompression from networks to the connected devices, as well as by using a number of optimizations to hide the data processing delays. Optimizations of some specific cases, such as the transmission of large data packets with several cache lines or the transmission of zero data, are considered. Special attention is given to data transmission via interprocessor links, where, due to their lower bandwidth compared to the on-chip network, data compression can be the most beneficial. The increase in memory subsystem bandwidth from using hardware data compression was confirmed in the experiments showing the relative IPC increase in SPEC CPU2017 benchmarks up to 14 percent.

DAG-Order: An Order-Based Dynamic DAG Scheduling for Real-Time Networks-on-Chip

With the high-performance requirement of safety-critical real-time tasks, the platforms of many-core processors with high parallelism are widely utilized, where network-on-chip (NoC) is generally employed for inter-core communication due to its scalability and high efficiency. Unfortunately, large uncertainties are suffered on NoCs from both the overly parallel architecture and the distributed scheduling strategy (e.g., wormhole flow control), which complicates the response time upper bounds estimation (i.e., either unsafe or pessimistic). For DAG-based real-time parallel tasks, to solve this problem, we propose DAG-Order, an order-based dynamic DAG scheduling approach, which strictly guarantees NoC real-time services. First, rather than build the new analysis to fit the widely used best-effort wormhole NoC, DAG-Order is built upon a kind of advanced low-latency NoC with SLT ( S ingle-cycle L ong-range T raversal) to avoid the unpredictable parallel transmission on the shared source-destination link of wormhole NoCs. Second, DAG-Order is a non-preemptive dynamic scheduling strategy, which jointly considers communication as well as computation workloads, and fits SLT NoC. With such an order-based dynamic scheduling strategy, the provably bound safety is ensured by enforcing certain order constraints among DAG edges/vertices that eliminate the execution-timing anomaly at runtime. Third, the order constraints are further relaxed for higher average-case runtime performance without compromising bound safety. Finally, an effective heuristic algorithm seeking a proper schedule order is developed to tighten the bounds. Experiments on synthetic and realistic benchmarks demonstrate that DAG-Order performs better than the state-of-the-art related scheduling methods.

Design and Analysis of Four Port Router for Network-On-Chip Applications

System-On-Chip (SoC) is a popular VLSI technology that integrates multiple devices onto a single chip. The Network-On-Chip (NOC) concept, which is a novel paradigm in sophisticated System-On-Chip designs that offers efficient communication throughout the on-chip networks, is used to communicate amongst various devices. The router is the main component in an NoC architecture that is responsible for routing information. Packets are sent through a network by an NoC made up of routers. A routing algorithm divides packets into flow control digits (flits) and determines their paths. The placement of routers is determined by the network topology. In the present work, the main target is to design and analyse the router, which is primarily based on a number of critical factors, including topology, routing algorithm, and packet format. The performance of the suggested router is evaluated and compared to that of the Conventional Wormhole Router (CWHR) with respect to power and slack time (ST). When compared to a traditional wormhole router, the proposed router architecture has 18% less slack. As a result, total power consumption is reduced by 29.3% as compared to traditional wormhole architecture. The architecture is synthesized using Cadence Encounter RTL Compiler using standard 65nm technology.

Omega multistage interconnection network manages double-pattern traffic with a regulator and high-speed forwarding method

This study proposes a flexible and effective solution for developing high-performance multistage interconnection networks to maximize the performance of parallel computer systems, cloud computing infrastructure, grids, etc. An omega-type multistage interconnection network, consisting of regulated switchboxes, is used as a testbed to handle flexible two-class load patterns. The wormhole routing method and a special forwarding technique controlled by a global regulator are adopted to alleviate internal ‘tree saturation’ caused by periodic hotspot traffic combined with uniform traffic. Simulation experiments prove that this concept reduces packet latency, and an additional layer inserted in the final stage further improves the network’s architecture.

Design of a high speed router for NOC

The complexity of System on Chip (SoC) is increasing with the scale of ICs, and Network on Chip (NoC) has become one of the most important solutions for SoC communication. As a significant point of NoC, research of routers and routing algorithms is receiving more and more attention from researchers and research institutes. This paper proposes a high-speed router on-chip router, which adopts wormhole switching mechanism, output queuing caching strategy, Credit-based flow control mechanism and Round-Robin arbitration mechanism, and the entire operation of the router is a two-stage flow. The selection of adaptive and deterministic routing algorithms can be done automatically, and finally, the performance parameters are evaluated.

MMNNN: A tree-based Multicast Mechanism for NoC-based deep Neural Network accelerators

Network-on-Chip (NoC) devices have been widely used in multiprocessor systems. In recent years, NoC-based Deep Neural Network (DNN) accelerators have been proposed to connect neural computing devices using NoCs. Such designs dramatically reduce off-chip memory accesses of these platforms. However, the large number of one-to-many packet transfers significantly degrade performance with traditional unicast channels. We propose a multicast mechanism for a NoC-based DNN accelerator called Multicast Mechanism for NoC-based Neural Network accelerator (MMNNN). To do so, we propose a tree-based multicast routing algorithm with excellent scalability and the ability to minimize the number of packets in the network. We also propose a router architecture for single-flit packets. Our proposed router transfers flits to multiple destinations in a single process and has no head-of-line blocking issue, offering higher throughput and lower latency than traditional wormhole router architectures. Simulation results show that our proposed multicast mechanism offers excellent performance in classification latency, average packet latency, and energy consumption.

Fully Reliable Dynamic Routing Logic for a Fault-Tolerant NoC Architecture

A fault-tolerant adaptive wormhole routing function for Networks-on-Chips (NoCs) is presented. The novelty of this routing logic is that it is capable of using runtime information on availability of links to dynamically bypass faulty channels. When faults occur, no offline reconfiguration or dropping of packets is necessary. Instead, dynamic routes are suggested on-the-fly. Routing decisions are based only on local knowledge, which allows for fast switching. Our approach does not use any costly virtual channels. As we do not prohibit cyclic dependencies, the routing function provides minimal routing from source to destination even in the presence of faults. We have implemented the architecture design using synthesizable HDL. Using simulations, we have assessed the overhead of our approach in terms of latency, power and area. On average, even with 40% of the links faulty our routing logic is capable performing correctly. Using formal verification, we have proven 100% reliability up to three faults, i.e., for any combination of three faults our routing logic remains connected, deadlock-free and livelock-free.

Transport study of the wormhole effect in three-dimensional topological insulators

Inside a three-dimensional strong topological insulator, a tube with $h/2e$ magnetic flux carries a pair of protected one-dimensional linear fermionic modes. This phenomenon is known as the "wormhole effect". In this work, we find that the "wormhole effect", as a unique degree of freedom, introduces exotic transport phenomena and thus manipulates the transport properties of topological insulators. Our numerical results demonstrate that the transport properties of a double-wormhole system can be manipulated by the wormhole interference. Specifically, the conductance and local density of states both oscillate with the Fermi energy due to the interference between the wormholes. Furthermore, by studying the multi-wormhole systems, we find that the number of wormholes can also modulate the differential conductance through a $\mathbb{Z}$$_{2}$ mechanism. Finally, we propose two types of topological devices in real applications, the "wormhole switch" device and the "traversable wormhole" device, which can be finely tuned by controlling the wormhole degree of freedom.

Advance Virtual Channel Reservation

We present a smart communication service called Advance Virtual Channel Reservation (AVCR) to provide a highway to target packets, which can greatly reduce their contention delay in NoC. AVCR takes advantage of the fact that we can know or predict the destination of some packets ahead of their arrival at the network interface (NI). Exploiting the time interval before a packet is ready, AVCR establishes an end-to-end highway from the source NI to the destination NI. This highway is built up by reserving the virtual channel (VC) resources ahead of the target packet transmission and offering priority service to flits in the reserved VC in the wormhole router, which can avoid the target packets’ VC allocation and switch arbitration delay. Additionally, optimization schemes are proposed to increase resources utilization and system performance. We evaluate AVCR with GEM5 full-system simulations by using 24 benchmarks in PARSEC and OMP2012. Compared to the state-of-art mechanisms and the priority-based mechanism, experimental results show that our mechanism can significantly reduce the target packets’ transfer latency and thus effectively decrease the average region-of-interest (ROI) time by 18.1 percent (maximally by 29.4 percent) across all benchmarks.

A study of multistage interconnection networks operating with wormhole routing and equipped with multi-lane storage

Multistage interconnection networks (MINs) provide critical communication resources between network components with an attractive cost/performance relation. In this paper, a novel architecture for a MIN is proposed. In contrast to other existing networks, this new architecture operates via wormhole routing using a multi-lane equivalent-weighted fair queuing system. Associating the lane storage with each physical channel for movement of the flits allows for high levels of packet flow and makes the system more robust. The resulting flit scheduling schema has been studied thoroughly, and the results are presented in this manuscript. In addition to performance metrics, additional factors such as complexity, cost and reliability are investigated. Since a basic aim of the design of MINs is to achieve a good data flow control mechanism, this proposal is an extremely effective and robust solution. The rationale behind this innovative scheme is to introduce a more efficient network technology, thus providing a better quality of service (i.e. streaming media vs. file transfer).

LBNoC

An FPGA-based Network-on-Chip (NoC) using a low-latency router with a look-ahead bypass (LBNoC) is discussed in this article. The proposed design targets the optimized area with improved network performance. The techniques such as single-cycle router bypass, adaptive routing module, parallel Virtual Channel (VC), and Switch allocation, combined virtual cut through and wormhole switching, have been employed in the design of the LBNoC router. The LBNoC router is parameterizable with the network topology, traffic patterns, routing algorithms, buffer depth, buffer width, number of VCs, and I/O ports being configurable. A table-based routing algorithm has been employed to support the design of custom topologies. The input buffer modules of NoC router have been mapped on the FPGA Block RAM hard blocks to utilize resources efficiently. The LBNoC architecture consumes 4.5% and 27.1% fewer hardware resources than the ProNoC and CONNECT NoC architectures. The average packet latency of the LBNoC NoC architecture is 30% and 15% lower than the CONNECT and ProNoC architectures. The LBNoC architecture is 1.15× and 1.18× faster than the ProNoC and CONNECT NoC frameworks.

HP-DCFNoC: High Performance Distributed Dynamic TDM Scheduler Based on DCFNoC Theory

The need for increasing the performance of critical real-time embedded systems pushes the industry to adopt complex multi-core processor designs with embedded networks-on-chip. In this paper we present hp-DCFNoC, a distributed dynamic scheduler design that by relying on the key properties of a delayed conflict-free NoC (DCFNoC) is able to achieve peak performance numbers very close to a wormhole-based NoC design without compromising its real-time guarantees. In particular, our results show that the proposed scheduler achieves an overall throughput improvement of 6.9× and 14.4× over a baseline DCFNoC for 16 and 64-node meshes, respectively. When compared against a standard wormhole router 95% of its network throughput is preserved while strict timing predictability as property is kept. This achievement opens the door to new high performance time predictable NoC designs.

A novel reconfigurable router for QoS guarantees in real-time NoC-based MPSoCs

Abstract This paper presents a proposal and implementation of a multi-mode full-reconfigurable router for Network-on-Chip (NoC). First, the router supports a hybrid packet-switching architecture that is dynamically reconfigurable to exchange between wormhole and virtual cut-through switching schemes at run-time. Therefore, it reaches a higher average performance than wormhole switching, while decreasing the implementation cost in comparison with the virtual cut-through switching. Second, the router is equipped a Quality-of-Services (QoS)-driven arbiter. Therefore, the proposed solution not only guarantees the guaranteed-throughput service without reserving resources but also enhances the average performance for the best-effort service by using network resources efficiently based on the priority inheritance arbitration mechanism. Third, the router is enhanced with the dynamically deadline-aware rerouting mechanism. In contention situation, the router can configure the routing computation unit to reroute the packet to another path so as to reduce the waiting interval of the blocked packets. The router was designed at the Register Transfer Level and modeled using VHDL language and then synthesized with Xilinx Virtex-7 FPGA technology. The experimental results prove that the proposed router is reliable and can improve the average performance of different QoS loads significantly compared with the generic routers while the area and power overhead are acceptable.

Virtual Channel aware Scheduling for Real Time Data-Flows on Network on-Chip

The increasing complexity of real-time applications presents a challenge to researchers and software designers. The tasks of these applications usually exchange large volume of data-flows and often need to satisfy real-time constraints. Although the Network on-Chip (NoC) paradigm offers an underlying communication infrastructure that gives more hardware resources, it is unable to safe tasks and data-flows deadlines. In recent works, preemptive wormhole switching with fixed priority has been introduced to meet real-time constraints of real-time applications. However, it suffers some bottleneck such as hardware requirement where none of these works takes account of the number of implemented virtual channels on the router. To alleviate this problem, we propose a novel scheduler for soft real-time data-flows application that takes into account the lack on resource in routers in term of Virtual channels. Experimental results obtained on a benchmark of synthetic and soft real applications have shown the efficiency of our approach in term of real-time constraints satisfaction for data-flow traffics and hardware requirements.

NoC-DPR: A new simulation tool exploiting the Dynamic Partial Reconfiguration (DPR) on Network-on-Chip (NoC) based FPGA

Due to the ability of Dynamic Partial Reconfiguration (DPR) of SRAM-based Field Programmable Gate Arrays (FPGAs) to add more flexibility over runtime phase, DPR is attracting more interest. Recently, FPGA manufacturers are facilitating the design of applications that utilize DPR. One of the main issues in our knowledge of DPR's current techniques (i.e., ICAP and JTAG) is a performance bottleneck; only one DPR is allowed at a time. In this paper, a state-of-art NoC-based FPGA simulator which supports DPR simulation is proposed. The proposed NoC-DPR simulator is used to investigate design limitations and performance degradation of using DPR on NoC-based FPGA. To estimate the reconfiguration time overhead, which results from increasing the number of simultaneous DPRs on FPGA fabric, some experimental investigations are carried out using NoC-DPR simulator. These investigations revealed that the overhead of reconfiguration time increases exponentially with increasing the number of simultaneous DPRs. However, further investigations show that the network of wormhole routers with virtual channels optimizes the reconfiguration time with a factor up to 4x than that of the network of wormhole routers without virtual channels.

A Multi-core architecture for a hybrid information system

This paper demonstrates our proposed Multi-core architecture for a hybrid information system (HIS) with the related work, system design, theories, experiments, analysis and discussion presented. Different designs on clusters, communication between different types of chips and clusters and network queuing methods have been described. Our aim is to achieve quality, reliability and resilience and to demonstrate it, our emphasis is on latency with messages communicated in our system – understand how it happens, what can trigger its increase, and then experiment with different types of focuses, including under Store-and-Forward Flow Control method, Wormhole flow control method, cluster size and message size to get a better understanding. Our analysis allows us to reduce latency and avoid its sharp increase. We justify our research contributions, particularly in the area of “traffic analysis and management” and “performance analysis of transmission control” of the HIS systems.

Improving system performance in non-contiguous processor allocation for mesh interconnection networks

Contiguous allocation of parallel jobs in multicomputers usually suffers from the degrading effects of fragmentation, because it requires that the allocated processors be contiguous and have the same topology as that of the multicomputer's interconnection network. Fragmentation can be avoided by adopting non-contiguous allocation. However, non-contiguous allocation can increase the distances among processors allocated to a job, which can increase the interference among messages of different jobs and increases message contention and delays. This paper suggests a new non-contiguous processor allocation strategy, referred to as Minimum Interference Paging (MIP), for the 2D mesh network. MIP attempts to reduce the distances among processors allocated using a paging variant that chooses a set of processors with the lowest distance between the first and last allocated processors, where the distance is the number of processors between the first allocated node and last allocated node. Using software simulation, we compared the performance of MIP against that of several well-known non-contiguous allocation strategies: paging (0), Multiple Buddy System (MBS) and Adaptive Non-contiguous Allocation (ANCA). The comparative evaluation was conducted using First-Come-First-Served (FCFS) job scheduling, wormhole routing and six communication patterns. These are the one-to-all, all-to-all, Near Neighbour, Ring, Divide and Conquer Binomial Tree (DQBT), and Random communication patterns. The results show that MIP exhibits superior performance in terms of average turnaround time of jobs.

HRC: A 3D NoC Architecture with Genuine Support for Runtime Thermal-Aware Task Management

In spite of escalating thermal challenges imposed by high power consumption, most reported 3D Network-on-chip (NoC) systems that adopt classic 3D cube (mesh) topology are unable to tackle the thermal management issues directly at the architectural level. Rather, to avoid chip being overheated, tasks running in a “hot” node have to be migrated to a “cooler” one, resulting in increased distance between communicating nodes and ultimately poor performance. In this paper, we propose a new 3D NoC architecture that genuinely supports runtime thermal-aware task management. Dubbed Hierarchical Ring Cluster (HRC), this new hierarchical 3D NoC architecture has three levels across its entire network hierarchy: 1) nodes are grouped as rings, 2) rings are then grouped into cubes, and 3) multiple cubes are connected to form the whole network. Routing in a HRC system is also performed in a hierarchical manner: Paths are set up within rings using low latency circuit switching, and data that need to cross the rings or cubes are routed following dimension-order routing supported by wormhole switching. In this organization, “hot” tasks that need to migrate can move along the rings without incurring increased communication distances. Our experimental results have confirmed that the proposed HRC architecture has a much lower network latency than other known 3D NoC architectures. When working with runtime thermal-aware task migration approaches, HRC can help reduce latency by as much as 80 percent compared to thermal-aware task migration approaches applied to 3D mesh NoC topologies.

AnyNoC: new network on a chip switching using the shared-memory and output-queue techniques for complex Internet of things systems

Recently, the Internet of things (IoT) has attracted a lot of attention owing to its versatile applications by enabling numerous things/objects to collect and exchange data via Internet. Despite the promising role of IoT, there exists the problem of integrating many heterogeneous functions into an embedded and complex IoT system. Meanwhile, in the past decade, we have also envisioned a paradigm shift in the embedded system market toward the system on a chip (SoC) by integrating all components into a single chip. But the on-chip communications of IoT systems remain an important and challenging issue. This work proposes a new network on a chip (NoC) switching, AnyNoC, employing the shared-memory and output-queue techniques implemented using the efficient dynamic link list, particularly suitable for the IoT SoC. The proposed high-level design can achieve the optimal performance by sharing the data buffer among all ports and eliminating the head-of-line blocking problem, resulting in a virtual point-to-point characteristic without the interruption of slow devices or congestion conditions in other ports. Moreover, the proposed architecture can minimize the required memory size by virtually sharing all buffers among all ports, resulting in one queue needed for each outbound port and totally N queues are required, where N denotes the number of ports. Therefore, compared to the famous wormhole switching, the proposed NoC architecture features lower cost and higher performance, which can approach the theoretical upper bound. Moreover, for a \(16\times 16\) network, the performance gain of the throughput of the proposed switching compared to the popular wormhole switching is about \(40\%\).

PERFORMANCE ENHANCEMENT IN IRREGULAR NETWORK USING MULTIPLE ROOT

Irregular network is one of cheaper option for high-parallel performance computing from chip level to large workstation. Irregular networks provide wire flexibility as well as scalable system. But Irregular network always have problem of deadlock in routing and channel utilization. Different solution has been already proposed such as Prefix Routing [1], Up/Down Routing [1], L-turn routing [2], cut Through Switching [9],Wormhole switching [3]. But all these algorithms have different performance in different networks means their performance is depended on network topology and root that is selected during routing in directional routing and prefix routing. In this paper we have proposed a methodology by which we can select a better root for spanning tree, some solution to improve over all utilization of channel for Up/down algorithms and prefix Routing [1].