Word-level Parallelism Research Articles

Top Tree Compression of Tries

We present a compressed representation of tries based on top tree compression [ICALP 2013] that works on a standard, comparison-based, pointer machine model of computation and supports efficient prefix search queries. Namely, we show how to preprocess a set of strings of total length n over an alphabet of size \(\sigma\) into a compressed data structure of worst-case optimal size \(O(n/\log _\sigma n)\) that given a pattern string P of length m determines if P is a prefix of one of the strings in time \(O(\min (m\log \sigma ,m + \log n))\). We show that this query time is in fact optimal regardless of the size of the data structure. Existing solutions either use \(\Omega (n)\) space or rely on word RAM techniques, such as tabulation, hashing, address arithmetic, or word-level parallelism, and hence do not work on a pointer machine. Our result is the first solution on a pointer machine that achieves worst-case o(n) space. Along the way, we develop several interesting data structures that work on a pointer machine and are of independent interest. These include an optimal data structures for random access to a grammar-compressed string and an optimal data structure for a variant of the level ancestor problem.

Fast Convolutions of Packed Strings and Pattern Matching with Wildcards

We give faster methods to compute discrete convolutions. We assume that all the inputs are packed, that is, strings are packed into words such that each word is packed with [Formula: see text] characters, where w is the length of a machine word and ∑ is the alphabet. The output of our methods is also packed, that is, each word of the output contains more than one element of the result. The approach is based on the word-level parallelism and the FFT. Given two strings with m and n ( n ≥ m ) characters that are packed into [Formula: see text] and [Formula: see text] words respectively, the convolution of them can be computed in [Formula: see text] time, where [Formula: see text] by the FFT. Experiments show that our method is three times faster than the convolution using the standard trick. We consider the problem of pattern matching with wildcards on packed strings. It finds all the occurrences of a pattern in a text, both of which may contain wildcards. By the convolution of packed strings, we present algorithms that are faster than the previous [Formula: see text]-time algorithm, where m is the length of the pattern and n the length of the text. The algorithm runs in [Formula: see text] time, where occ is the number of occurrences of the pattern in the input. Experiments show that the method is faster than the bit-parallel wildcard matching algorithm for long patterns.

Accelerating Irregular Computation in Massive Short Reads Mapping on FPGA Co-Processor

Because there is an enormous amount of genomic data, next-generation sequencing (NGS) applications pose significant challenges to current computing systems. In this study, we investigate both algorithmic and architectural strategies to accelerate an NGS data analysis algorithm—short read mapping on commodity multi-core platform and customizable field programmable gate array (FPGA) co-processor architecture, respectively. A workload analysis reveals that conventional memory optimization is limited in its irregular computation of low arithmetic intensity and non-contiguous memory access pattern. To mitigate the inherent irregular computation in mapping, we have developed a FPGA co-processor based on Convey computer, which employs a scatter-gather memory mechanism that exploits both bit-level and word-level parallelism. The customized FPGA co-processor achieves a throughput of $947$ Gbp per day, about $189$ times higher than that of current mapping tools on single CPU core. Moreover, the co-processor's power efficiency is $29$ times higher than that of a conventional 64-core multi-processor.

Engineering Parallel String Sorting

We discuss how string sorting algorithms can be parallelized on modern multi-core shared memory machines. As a synthesis of the best sequential string sorting algorithms and successful parallel sorting algorithms for atomic objects, we first propose string sample sort. The algorithm makes effective use of the memory hierarchy, uses additional word level parallelism, and largely avoids branch mispredictions. Then we focus on NUMA architectures, and develop parallel multiway LCP-merge and -mergesort to reduce the number of random memory accesses to remote nodes. Additionally, we parallelize variants of multikey quicksort and radix sort that are also useful in certain situations. As base-case sorter for LCP-aware string sorting we describe sequential LCP-insertion sort which calculates the LCP array and accelerates its insertions using it. Comprehensive experiments on five current multi-core platforms are then reported and discussed. The experiments show that our parallel string sorting implementations scale very well on real-world inputs and modern machines.

New algorithms for binary jumbled pattern matching

Given a pattern P and a text T, both strings over a binary alphabet, the binary jumbled string matching problem consists in telling whether any permutation of P occurs in T. The indexed version of this problem, i.e., preprocessing a string to efficiently answer such permutation queries, is hard and has been studied in the last few years. Currently the best bounds for this problem are O(n2/log2n) (with O(n) space and O(1) query time) (Moosa and Rahman (2012) [1]) and O(r2logr) (with O(|L|) space and O(log|L|) query time) (Badkobeh et al. (2012) [2]), where r is the length of the run-length encoding of T and |L|=O(n) is the size of the index. In this paper we present new results for this problem. Our first result is an alternative construction of the index by Badkobeh et al. (2012) [2] that obtains a trade-off between the space and the time complexity. It has O(r2logk+n/k) complexity to build the index, O(logk) query time, and uses O(n/k+|L|) space, where k is a parameter. The second result is an O(n2log2w/w) algorithm (with O(n) space and O(1) query time), based on word-level parallelism where w is the word size in bits.

Exploiting word-level parallelism for fast convolutions and their applications in approximate string matching

We develop a method for performing convolutions efficiently in a word RAM model of computation, having a word size of w=Ω(logn) bits, where n is the input size. The basic idea is to pack several elements of the input vector into a single computer word, effectively enabling parallel computation of convolutions. The technique is applied to approximate string matching under Hamming distance. The obtained algorithms are the fastest known. In particular, we reduce the complexity of the Amir et al. (2000) algorithm for k-mismatches from O(nklogk) to O(n+nk/wlogk). Those algorithms impose some (not severe) limitation on the pattern length, m. We present another, less efficient however, technique based on word-level parallelism, which works without the pattern length limitation.

A Novel High Speed FPGA Architecture for FIR Filter Design

<em><strong> </strong></em>This paper presents the details of hardware implementation of linear phase FIR filter using merged MAC architecture. Speed of convolution operation of FIR filter is improved using merged MAC architecture. By exploiting the reduced complexity made possible by the use of sparse powers of two partial products terms coefficients, an FIR filter tap can be implemented with 2B full adders, and 2B latches, where B is intermediate wordlegnth. Word and bit level parallelism allows high sampling rates, limited only by the full adder delay. The proposed architecture is based on binary tree constructed using modified 4:2 and 5:2 compressor circuits. Increasing the speed of operation is achieved by using higher modified compressors in critical path. Our objective of work is, to increase the speed of multiplication and accumulation operation by minimizing the number of combinational gates using higher n: 2 compressors, which is required more for Array multiplier at the time of implementation of array architecture. This novel architecture allows the implementation of high sampling rate filters of significant length on FPGA Spartan-3 device (XC3S400 PQ-208). The simulation result shows convolution output of digital FIR filter which is done using Questa Sim 6.4c Mentor Graphics tool. The experimental test of the proposed digital FIR filter is done using Spartan-3 device (XC3S400 PQ-208)

Faster Approximate String Matching for Short Patterns

We study the classical approximate string matching problem, that is, given strings P and Q and an error threshold k, find all ending positions of substrings of Q whose edit distance to P is at most k. Let P and Q have lengths m and n, respectively. On a standard unit-cost word RAM with word size w≥log n we present an algorithm using time $$O\biggl(nk \cdot \min\biggl(\frac{\log^2 m}{\log n},\frac{\log^2 m\log w}{w}\biggr) + n\biggr)$$ When P is short, namely, $m = 2^{o(\sqrt{\log n}\,)}$ or $m =2^{o(\sqrt{w/\log w}\,)}$ this improves the previously best known time bounds for the problem. The result is achieved using a novel implementation of the Landau-Vishkin algorithm based on tabulation and word-level parallelism.