Wire Routing Research Articles

CMOS EIGHT-TRANSISTOR MEMORY CELL FOR LOW-DYNAMIC-POWER HIGH-SPEED EMBEDDED SRAM

Embedded SRAM design with high noise margin between read and write, low power, low supply voltages, and high speed become essential features in VLSI embedded applications. The complete embedded SRAM design of self-timing synchronization is proposed based on the CMOS eight-transistor (8T-Cell) memory cell circuit. The cell is based on the traditional six-transistor (6T-Cell) cross-coupled invertors with the addition of two NMOS transistors for separate read buffer circuit. The read buffer structure is based on pre-charging the read bit-line during the low value of read clock and evaluating the read bit-line during the high value of read clock, thereby maintaining one active line per column and eliminating the use of traditional sense amplifier with all its synchronization schemes. The simulation results show that the embedded SRAM of size 128-bit × 128-bit is operating at a maximum frequency of 200 MHz for Write and Read clock cycles with 1.62 V power supply, and measures a total average power consumption of 22.60 mW. All simulation results were conducted on 0.18 μm TSMC single poly and three layers of metals measuring a cell area of 2.2 × 3.0 μ m 2. The circuit is not meant to replace the SRAM with 6T-Cell transistor structure; however, it is attractive for applications related to high density with automation road-map design, such as graphic and network processor chips. In these applications, memory sizes are introduced in many different irregular geometries and uses all over the chip with storage sizes less than 20 k-bit, in addition, it is susceptible to large substrate noise as well as large coupling wire routing.

Vibration Response of 3-D Space Accessible Sandwich Composite

A 3-D sandwich composite comprising of E-glass core piles which are woven to the facesheets is considered in this work. This arrangement creates interstitial spaces in the core which can be used for foam infusion for sound/vibration damping, fluid storage, or for routing wires or inserts, in addition to providing strength. The vibroacoustic response of such multi-functional materials has received little attention and is an important issue when the structure witnesses mechanical vibrations. This article presents the vibration related studies carried out on the 3-D sandwich composite, infused with SC-15 resin. The frequency response function (FRF) and the damping ratios are the parameters of interest for this study. In this study the experimental data is presented for the unfoamed (as received) core configuration and the core filled with the polyurethane (PUR) foam. The average damping ratio of the unfoamed sandwich panel was found to be 0.55%. An increase of 150% in the damping ratio was observed for the PUR foam filled panels for a 77% increase in weight when compared to an unfoamed sandwich panel. Use of vibration as a non-destructive damage detection technique is demonstrated for beam specimens damaged by flexural loading. A reduction of 35% in the resonant frequency and 193% increase in the damping ratio was observed for approximately 6% core damage of the sandwich composite.

Evaluation of natural gas supply options for Southeast and Central Europe: Part 2. Multi-criteria assessment

Decision making methods are used as a tool for the selection of alternatives to be evaluated on the basis of several criteria. Evaluation of the potential routes for natural gas supply to the Southeast and Central European countries is studied using single and multi-criteria evaluation. The potential options included in this analysis are the: Yamal Route; Nabucco Route; West Balkan Route; LNG Neum Route; and Gas by Wire Route. In part 1, the paper was devoted to the definition of the indicators and to single indicator analysis. In part 2, the analysis is based on multi-criteria evaluation, which comprises the possibility to assess the options under predefined constraints amongst indicators. The paper also describes different methods used for multi-criteria evaluation. This analysis focuses on cases with different priorities defined among individual weighting coefficients with the others having the same value. It was shown that all options under specific constraints can be qualified as promising in the decision making process. It is also concluded that favourite indicator constraints may exaggerate some options.

Forward Kinematics of One-Link Tendon Robot Using Approximate Models of a Belt-Formed Pulley

The control of joint stiffness of a robot is extremely important to guarantee safe and dexterous motion, especially for the collaborative operation between a human and a robot. Some devices to vary the joint stiffness have been proposed for a tendon-manipulator so far. However, the previous devices have problems such as a complex structure, increase of friction, increase of inertia and so on. In order to overcome these problems, we proposed a belt-formed pulley to vary the joint stiffness. Inserting the belt-formed pulleys into routes of wires, the joint stiffness of a tendon-driven robot can be varied depending on internal force among wires. The system using belt-formed pulleys has many advantages such as a simple structure, low friction, lightness in weight and low cost. However, little is known about kinematic issues of the tendon-manipulator using belt-formed pulleys. In this paper, we propose a numerical solving method of forward kinematics (to obtain joint angles from wire length) using approximate models of a belt-formed pulley. First, we propose three approximate models of a belt-formed pulley, and investigate usefulness of each model. Secondly, we present the numerical solving method of forward kinematics for a 1-DOF manipulator. Lastly, the usefulness of the proposed method is demonstrated through experimental result.

Placement and Routing in VLSI design Problem Using Single Row Routing Technique

Two major problems are involved in VLSI design, namely, the placement of components and routing between these components. Single row routing problem is a combinatorial optimization problem of significant importance for the design of complex VLSI multi layer printed circuit boards (PCB's). The design involves conductor routing that makes all the necessary wiring and interconnections between the PCB modules, such as pins, vias, and backplanes. In very large systems, the number of interconnections may exceed tens of thousands. Therefore, we have to optimize the wire routing and interconnections and thus determine the efficient designs. Kernighan-Lin algorithm, traveling salesman problem, simulated annealing algorithm and single row routing problem are used to find the best design. Included here are some simple examples to find the results. A simulation program using Microsoft Visual C++ is developed to simulate the single row routing problem using the simulated annealing algorithm. Keywords: Placement and Routing in VLSI; Single Row Routing; Kernighan-Lin Algorithm; Simulated Annealing

Multi-frequency EIT system with radially symmetric architecture: KHU Mark1

We describe the development of a multi-frequency electrical impedance tomography (EIT) system (KHU Mark1) with a single balanced current source and multiple voltmeters. It was primarily designed for imaging brain function with a flexible strategy for addressing electrodes and a frequency range from 10 Hz–500 kHz. The maximal number of voltmeters is 64, and all of them can simultaneously acquire and demodulate voltage signals. Each voltmeter measures a differential voltage between a pair of electrodes. All voltmeters are configured in a radially symmetric architecture in order to optimize the routing of wires and minimize cross-talk. We adopted several techniques from existing EIT systems including digital waveform generation, a Howland current generator with a generalized impedance converter (GIC), digital phase-sensitive demodulation and tri-axial cables. New features of the KHU Mark1 system include multiple GIC circuits to maximize the output impedance of the current source at multiple frequencies. The voltmeter employs contact impedance measurements, data overflow detection, spike noise rejection, automatic gain control and programmable data averaging. The KHU Mark1 system measures both in-phase and quadrature components of trans-impedances. By using a script file describing an operating mode, the system setup can be easily changed. The performance of the developed multi-frequency EIT system was evaluated in terms of a common-mode rejection ratio, signal-to-noise ratio, linearity error and reciprocity error. Time-difference and frequency-difference images of a saline phantom with a banana object are presented showing a frequency-dependent complex conductivity of the banana. Future design of a more innovative system is suggested including miniaturization and wireless techniques.

Evaluation of natural gas supply options for south east and central Europe. Part 1: Indicator definitions and single indicator analysis

The need for diversification of energy sources is an immanent goal in long term energy strategy. In particular, this is of great importance for the natural gas supply. In this respect, evaluation and assessment of potential natural gas resources and their relation to consumers is of great importance. The natural gas supply in Europe is one of the main issues of European energy strategy to be followed in the future. In particular, the natural gas supply in the southeast countries is important. This paper provides a framework for understanding how much natural gas is available for use in south east and central Europe as well as the links to the recent supply of natural gas and its transport. The analysis is focused on evaluation of the potential routes for natural gas supply to the south east and central European countries. The potential options included in this analysis are the Yamal Route; Nabucco Route; West Balkan Route; LNG NEUM Route and Gas by Wire Route. In this analysis, attention is focused on the following indicators for assessment of potential options: environmental indicator; NG cost indicator; NG transport and royalty indicator; investment indicator; and NG demand indicator. The first part of this paper is devoted to the definition of the indicators and to single indicator analysis.

Mathematical methods for physical layout of printed circuit boards: an overview

This article surveys mathematical models and methods used for the physical layout of printed circuit boards, in particular component placement and wire routing. The main concepts are briefly described together with relevant references.

Reed-Muller 전개식에 의한 다치 논리회로의 구성에 관한 연구

In this paper, we present a method on the construction of multiple-valued circuits using Reed-Muller Expansions(RME). First, we discussed the input output interconnection of multiple valued function using Perfect Shuffle techniques and Kronecker product and designed the basic cells of performing the transform matrix and the reverse transform matrix of multiple valued RME using addition circuit and multiplication circuit of GF(4). Using these basic cells and the input-output interconnection technique based on Perfect Shuffle and Kronecker product, we implemented the multiple valued logic circuit based on RME. The proposed design method of multiple valued RME is simple and very efficient to reduce addition circuits and multiplication circuits as compared with other methods for same function because of using matrix transform based on modular structures. The proposed design method of multiple valued logic circuits is simple and regular for wire routing and possess the properties of concurrency and modularity of array.

DRAWING WITH FAT EDGES

Traditionally, graph drawing algorithms represent vertices as circles and edges as curves connecting the vertices. We introduce the problem of drawing with "fat" edges, i.e., with edges of variable thickness. The thickness of an edge is often used as a visualization cue, to indicate importance, or to convey some additional information. We present a model for drawing with fat edges and a corresponding efficient polynomial time algorithm that uses the model. We first focus on a restricted class of graphs that occur in VLSI wire routing and then show how to extend the algorithm to general planar graphs. We show how to convert an arbitrary wire routing into a homotopically equivalent routing that maximizes the distance between any two wires, which is a desired property in VLSI design. Among such, we obtain the routing with minimum total wire length. A homotopically equivalent routing that maximizes the distance between any two wires yields a graph drawing which maximizes edge thickness. Our algorithm does not require unit edge thickness but can be applied as well in the presence of different edge weights.

Flexibility of Steiner trees in uniform orientation metrics

AbstractWe present some fundamental flexibility properties for minimum length networks (known as Steiner minimum trees) interconnecting a given set of points in an environment in which edge segments are restricted to λ uniformly oriented directions. These networks are referred to as λ‐SMTs. They promise to play an increasingly important role in the future of optimal wire routing in VLSI physical design, particularly for the next generation of VLSI circuits. In this article we develop the concept of a flexibility polygon for a λ‐SMT, which is a region representing the union of all λ‐SMTs with the same topology on a given set of points. We show that this polygon can be constructed, for a given point set and given topology, in linear time. We discuss some of the future applications of this polygon, which can be thought of as a geometric representation of the amount of flexibility inherent in a given λ‐SMT. © 2005 Wiley Periodicals, Inc. NETWORKS, Vol. 46(3), 142–153 2005

Spanning graph-based nonrectilinear steiner tree algorithms

With advances in fabrication technology of very/ultra large scale integrated circuit (VLSI/ULSI), we must face many new challenges. One of them is the interconnect effects, which may cause longer delay and heavier crosstalk. To solve this problem, many interconnect performance optimization algorithms have been proposed. However, when these algorithms are designed based on rectilinear interconnect architecture, the optimization capability is limited. Therefore, nonrectilinear interconnect architectures become a field of active research in which the octilinear interconnect architecture is the most promising one since it extends from the rectilinear case and greatly shortens the wire length. Meanwhile, an interconnect with less length is helpful to reduce wire capacitance, congestion, and routing area. In an interconnect architecture, the Steiner minimal tree (SMT) construction is one of the key problems. In this paper, we give two practical octilinear Steiner minimal tree (OSMT) construction algorithms based on octilinear spanning graphs (OSGs). The one with edge substitution (OST-E) has a worst-case running time of O(nlogn) and a similar performance as the recent work using batched greedy. The other one with triangle contraction (OST-T) has a small increase in the constant factor of running time and a better performance. These two are the fastest algorithms for octilinear Steiner tree construction so far. Experiments on both industrial and random test cases are conducted to compare with other programs. We also proposed the extension of our algorithms to any /spl lambda/ geometry.

An embedding debugging architecture for SOCs

Multiple cores embedded debugging architecture for system on chip design (SOC) is presented. It presents an asymmetrical functional test problem. To analyze the problem and optimize performance in multicore operation, debug tools with interfaces are exercised for several cores. HyperJTAG (joint test action group) interface reduces the IO pin interfaces required for debugging several cores. To overcome the wiring problem in hyperJTAG, wire routing and debugging synchronization is proposed. Hyper debug action nodes at each core initiate global or local control actions that synchronously reset the cores. To provide a virtual connection between the processor core in the SoC and its corresponding probe control, MED (multicore embedded debugging) software tool is proposed. This allows a contiguous analysis flow from the system level simulation models of SoC systems through FPGA and emulation prototyping and finally it debug the silicon hardware.

Line-addressable digital-deflection programmable micromirror array

We report a novel digital-deflection programmable micromirror array driven by micromechanical digital-to-analog converters that eliminates the need for electrical digital-to-analog converters for analog displacement control, thus simplifying the driving circuitry and reducing the overall system cost. Furthermore, owing to the bistable and hysteretic characteristics of parallel-plate electrostatic actuators, an array of micromirrors can be controlled by means of row- and column-addressing lines, which drastically reduce the number of routing wires and allow array sizes to increase while they maintain high array quality.

Innovative Circuit Board Level Routing Designs for BGA Packages

Advances in the performance of electronic devices have resulted in high input/output counts both at the chip and the package level, which has led to the development of new packaging technologies that can accommodate these high counts. This paper presents and analyzes a novel method for the placement of ball grid array (BGA) bonding pads and routing wires on printed circuit boards to maximize signal density, which ultimately reduces the number of circuit board layers for routing. This method has been termed as the shifted as needed method and all the ball placement/trace routing designs shown in this paper are based on this method. We also present a performance metric defined as the number of balls routed out divided by the area of package footprint on the circuit board, and we compare various placement/routing schemes using this method.

ON FINDING A STAIRCASE CHANNEL WITH MINIMUM CROSSING NETS IN A VLSI FLOORPLAN

A VLSI chip is fabricated by integrating several rectangular circuit blocks on a 2D silicon floor. The circuit blocks are assumed to be placed isothetically and the netlist attached to each block is given. For wire routing, the terminals belonging to the same net are to be electrically interconnected using conducting paths. A staircase channel is an empty polygonal region on the silicon floor bounded by two monotonically increasing (or decreasing) staircase paths from one corner of the floor to its diagonally opposite corner. The staircase paths are defined by the boundaries of the blocks. In this paper, the problem of determining a monotone staircase channel on the floorplan is considered such that the number of distinct nets whose terminals lie on both sides of the channel, is minimized. Two polynomial-time algorithms are presented based on the network flow paradigm. First, the simple two-terminal net model is considered, i.e., each net is assumed to connect exactly two blocks, for which an O(n×k) time algorithm is proposed, where n and k are respectively the number of blocks and nets on the floor. Next, the algorithm is extended to the more realistic case of multi-terminal net problem. The time complexity of the latter algorithm is O((n+k)×T), where T is the total number of terminals attached to all nets in the floorplan. Solutions to these problems are useful in modeling the repeater block placement that arises in interconnect-driven floorplanning for deep-submicron VLSI physical design. It is also an important problem in context to the classical global routing, where channels are used as routing space on silicon.

Sequential and Parallel Meta-Heuristics for Solving the Single Row Routing Problem

The design of multi-layer printed circuit boards is vital in the construction of complex electronic systems. Wire routing is a crucial step in the overall design process, which can be decomposed into a number of single row routing (SRR) problems. This paper proposes an approach to solve the SRR problem based on parallel meta-heuristics. The development of this technique involves the design of an encoding strategy that allows all possible routings to be uniquely represented and the derivation of cost functions that maximizes the quality of the developed solutions. Further, parallelization of the proposed approach is attempted to improve the computational efficiency. The different stages of the development are backed by experiments to show the pros and cons of the sequential and parallel implementations.

전류모드 CMOS에 의한 다치 가산기 및 승산기의 구현

본 논문에서는 전류모드 CMOS를 사용하여 다치 가산기 및 다치 승산기를 구현하였으며, 먼저 효과적인 집적회로 설계 이용성을 갖는 전류모드 CMOS를 사용하여 3치 T-게이트와 4치 T-게이트를 구현하였다. 구현된 다치 T-게이트를 조합하여 유한체 <TEX>$GF(3^2)$</TEX>의 2변수 3치 가산표와 승산표를 실현하는 회로를 구현하였으며, 이들 다치 T-게이트를 사용하여 유한체 <TEX>$GF(4^2)$</TEX>의 2변수 4치 가산표와 승산표를 실현하는 회로를 구현하였다. 또한, Spice 시뮬레이션을 통하여 이 회로들에 대한 동자특성을 보였다. 다치 가산기 및 승산기들은 <TEX>$1.5\mutextrm{m}$</TEX> CMOS 표준 기술의 MOSFET 모델 LEVEL 3을 사용하였고, 단위전류는 <TEX>$15\mutextrm{A}$</TEX>로 하였으며, 전원전압은 3.3V를 사용하였다. 본 논문에서 구현한 전류모드 CMOS의 3치 가산기와 승산기, 4치 가산기와 승산기는 일정한 회선경로 선택의 규칙성, 간단성, 셀 배열에 의한 모듈성의 이점을 가지며 특히 차수 m이 증가하는 유한체의 두 다항식의 가산 및 승산에서 확장성을 가지므로 VLSI화 실현에 적합한 것으로 생각된다. In this paper, the multiple-valued adders and multipliers are implemented by current-mode CMOS. First, we implement the 3-valued T-gate and the 4-valued T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second we implement the circuits to be realized 2-variable 3-valued addition table and multiplication table over finite fields <TEX>$GF(3^2)$</TEX>, and 2-variable 4-valued addition table and multiplication table over finite fields <TEX>$GF(4^2)$</TEX> with the multiple-valued T-gates. Finally, these operation circuits are simulated under <TEX>$1.5\mutextrm{m}$</TEX> CMOS standard technology, <TEX>$15\mutextrm{A}$</TEX> unit current, and 3.3V VDD voltage Spice. The simulation results have shown the satisfying current characteristics. The 3-valued adder and multiplier, and the 4-valued adder and multiplier implemented by current-mode CMOS is simple and regular for wire routing and possesses the property of modularity with cell array. Also, since it is expansible for the addition and multiplication of two polynomials in the finite field with very large m, it is suitable for VLSI implementation.

유한체 GF(2m)상의 셀 배열 병렬 승산기의 설계

본 논문에서는 유한체 GF<TEX>$(2^m)$</TEX>상에서 두 다항식의 승산을 실현하는 병렬-입력 및 병렬-출력을 갖는 셀 배열 병렬 승산기를 제시한다 이 승산기는 승산연산부, 기약다항식연산부. MOD연산부로 구성한다. 승산연산부는 AND 게이트와 XOR 게이트로 설계한 기본 셀의 배열로 이루어지며, 기약다항식연산부는 XOR 게이트와 D 플림플롭회로를 사용하여 구성하며, MOD연산부는 AND 게이트와 XOR 게이트에 의한 기본 셀을 배열하여 구성하였다. 제시한 승산기는 PSpice 시뮬레이션을 통하여 동작특성을 보였으며, 클럭신호의 주기를 l<TEX>${\mu}\textrm{s}$</TEX>로 하였다. 제시한 셀 배열 병렬 승산기는 m=4인 경우에 AND 게이트의 수가 24개, XOR 게이트의 수가 32개 필요하며, D 플립플롭회로가 4개 필요하다. 또한, AOP 기약 다항식을 사용하면 AND 게이트와 XOR 게이트의 수가 24개 필요하며 D 플립플롭은 사용되지 않는다. 셀 배열 병렬 승산기의 승산연산부의 동작시간은 1 단위시간(클럭시간)이 소비되고, 기약다항식연산부에 의한 MOD연산부의 동작시간은 m 단위시간(클럭시간)이 소비되어 전체 동작시간은 m+1 단위시간(클럭시간)이 소비된다. 본 논문에서 제시한 셀 병렬 승산기는 회선경로 선택의 규칙성, 간단성, 배열의 모듈성과 병렬동작의 특징을 가지며, 특히 차수 m이 매우 큰 유한체강의 두 다항식의 승산에서 확장성을 갖는다. A cellular array parallel multiplier with parallel-inputs and parallel-outputs for performing the multiplication of two polynomials in the finite fields GF<TEX>$(2^m)$</TEX> is presented in this paper. The presented cellular way parallel multiplier consists of three operation parts: the multiplicative operation part (MULOP), the irreducible polynomial operation part (IPOP), and the modular operation part (MODOP). The MULOP and the MODOP are composed if the basic cells which are designed with AND Bates and XOR Bates. The IPOP is constructed by XOR gates and D flip-flops. This multiplier is simulated by clock period l<TEX>${\mu}\textrm{s}$</TEX> using PSpice. The proposed multiplier is designed by 24 AND gates, 32 XOR gates and 4 D flip-flops when degree m is 4. In case of using AOP irreducible polynomial, this multiplier requires 24 AND gates and XOR fates respectively. and not use D flip-flop. The operating time of MULOP in the presented multiplier requires one unit time(clock time), and the operating time of MODOP using IPOP requires m unit times(clock times). Therefore total operating time is m+1 unit times(clock times). The cellular array parallel multiplier is simple and regular for the wire routing and have the properties of concurrency and modularity. Also, it is expansible for the multiplication of two polynomials in the finite fields with very large m.

Crystalline silicon tilting mirrors for optical cross-connect switches

This paper discusses a two-piece approach for fabricating two-dimensional (2-D) arrays of tilting MEMS mirrors with application in very-large optical cross-connect switches. In the new process, a two-sided etching of silicon-on-insulator (SOI) wafers is used to create crystalline mirrors on a first wafer that is later aligned and bonded to a separate wafer containing the activation electrodes, traces, and bond pads. The approach allows a very close spacing of mirror elements and a very simple design for the mechanical structures, and also greatly simplifies wire routing.