Wire Inductance Research Articles

Suppression Method for Harmonic Magnification of DC Circuit in Large-Scale Inverter System

In a large-scale inverter system that uses a semiconductor switching device, a rectifier and an inverter are connected through a DC circuit. In this circuit, the harmonic magnification phenomenon is often induced by the inductance of distribution wires and the condenser to absorb the harmonic voltage and current. To suppress this harmonic magnification phenomenon, we propose a new suppression method to use the initial phase of the carrier wave. When some inverters operate in parallel at the same frequency, such as the inverters to drive LSM, it is possible to reduce the specific harmonic component of the total inverter input current due to PWM control by changing the phase of the carrier wave of each inverter. We studied a method of suppressing the magnification phenomenon of the specific harmonic near the resonant frequency of the DC circuit by using this principle and confirmed its performance by the digital simulation.

A Fast Macro-Model for Substrate Coupling and Ground Bounce Induced Substrate Noise Simulation in Mixed Signal VLSI

This paper discusses a novel substrate modeling technique for the simulation of substrate noise in mixed signal VLSI systems. This model yields to easy merger with the SPICE simulation netlist for the complete pre and post layout estimation of substrate noise effects in large mixed signal VLSI chips. Compared to previous numerous efforts in substrate noise modeling ranging from finite element methods (FEM) to boundary elements methods (BEM), this model, based on a finite sheet resistor slicing scheme also incorporates the effect of supply rail bounce due to bonding wire inductances, and, provides realistic estimates of substrate noise effects with a high degree of computational efficiency. Substrate noise simulations were done using a 0.18 μm TSMC CMOS process technology using typical process parameters. A differential switched capacitor sample and hold circuit and a linear differential transconductor stage was used for the performance evaluation of this novel substrate model. Simulation results indicate a typical increase in Total Harmonic Distortion (THD) by atleast 6 dB due to the substrate noise effects, which corresponds to a performance loss by around 1-b precision. Also, the substrate noise effects are found to be proportional to the oversampling ratio (i.e., the digital clocking rate with respect to the input signal) and the net number of logic transitions at each register transfer instance in the mixed signal chip.

Parasitic-aware design and optimisation of RF power amplifiers

Design considerations using parasitic-aware synthesis and optimisation techniques are presented for a three-stage 30 dBm 900 MHz class-E power amplifier implemented in a 0.35 μm standard digital CMOS process. Using both bond wire and on-chip square spiral inductors, the PA achieves 49% drain efficiency η and 25 dB power gain using a single 3.3 V power supply. Experience shows that the class-E PA design space is complex with many local minima. Thus, simulated annealing optimisation is chosen because of its inherent hill climbing ability that allows it to avoid being trapped in sub-optimum local minima. The paper first demonstrates the severe effects of parasitics by comparing results of switching power amplifier designs with both parasitic-free and parasitic-laden on-chip inductors. The results of parasitic-aware synthesis are then presented, including an illustration of its potential for power amplifier topology selection.

Characterisation of substrate noise in flash A/D converters

A method for modelling electromagnetically coupled substrate noise in mixed signal integrated circuits was developed. This method was then used to characterise the substrate noise issues in FLASH analogue to digital (A/D) converters. The model was also used to study the addition of the P+ guards around the input devices of the comparators in order to assess their effectiveness in reducing the substrate noise. Finally, the effect of variations in the package's bond wire inductances in the net injected current noise was modelled.

Analysis of on-chip inductance effects for distributed RLC interconnects

This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC interconnects that takes the effect of both the series resistance and the output parasitic capacitance of the driver into account. Using rigorous first principle calculations, accurate expressions for the transfer function of these lines and their time-domain response have been presented for the first time. Using these, a new and computationally efficient performance optimization techniques for distributed RLC interconnects has been introduced. The new optimization technique has been employed to analyze the impact of line inductance on the circuit behavior and to illustrate the implications of technology scaling on wire inductance. It is shown that reduction in driver output resistance and input capacitance with scaling can make deep submicron designs increasingly susceptible to inductance effects if global interconnects are not scaled. For scaled global interconnects with increasing line resistance per unit length, as prescribed by the International Technology Roadmap for Semiconductors, the effect of inductance on interconnect performance actually diminishes.

Mathematical approach to current sharing problem of superconducting triple strands

Current sharing between insulated strands in a superconducting cable is one of the important problems for its utilization. From the view points of the inverse problem, the sensitivity of current sharing between the insulated strands is determined by the condition number of the inductance matrix. For triple strands with self similar structure, we derive the analytic form of the inductance matrix which only includes two parameters; the self inductance of a unit wire and the ratio of mutual to self inductance for unit wires. Since the matrix elements also have self similar structure, we can analytically obtain the eigenvalues, eigenvectors and condition number, which is the ratio of maximum and minimum eigenvalues. Next, we derive the formula to estimate the sensitivity of the current distribution against the displacement of inductance from the ideal case by use of the condition number. This formula shows that the sensitivity is inversely proportional to the difference of self and mutual inductances of unit wires. Moreover, we estimate the condition number of very thin wire to check our formula. Finally, we verify our analytic form by numerical calculations.

Resonance phenomenon in the DC circuit of large-scale inverter system

In a large-scale inverter system, a DC circuit connects the rectifier and the inverter. A harmonic resonance phenomenon is often induced by the DC capacitor to stabilize the voltage and the inductance of distribution wires. When the harmonic resonance is induced, the DC circuit is interfered with by the magnified harmonic component of the inverter input current. Therefore, it is necessary to analyze the harmonic resonance phenomenon and the inverter input current. To absorb the harmonic current and voltage, the DC capacitor is connected to the rectifier and the inverter sides in the DC circuit. Moreover, to restrain the voltage fluctuation by sudden changes in the load, it is necessary to connect more DC capacitors. We clarified the relation between the harmonic resonance phenomenon and the capacitor distribution on both sides, examined the input harmonic current of the multiple stages PWM inverter that is used to drive the LSM and has different configurations depending on train speed, and confirmed the above by simulation.

Development of a flexible cardiorespiratory monitor based on induction plethysmography

Induction plethysmography (IP) utilizes changes in the inductance of sinusoidal wires embedded in elastic bands placed around the chest and abdomen to detect volume changes in the two compartments. These changes can be attributed to respiration or heart beat. To date, most applications have been tailored to an investigation of respiration. More sensitive systems have been employed for the detection of cardiac activity. The wires within the bands, which function as the coil in a resonant circuit, are excited by an oscillator. Among other factors, the inductance of the coil depends on the cross-sectional area of the coie, and changes with respiration in coils placed around the chest and abdomen. Using LabView software, the biosignals obtained undergo an analog-to-digital conversion prior to processing. The system was calibrated using the isovolume method. In 10 adults, IP was tested against a pneumotachograph (PNT) in different body positions (standing, sitting, supine, prone). Correlation between tidal volumes measured with IP and PNT was of r > or = 0.96 on average, recalibration being done after each change in position. The absolute mean error ranged between 3.7 and 8.5%, depending on body position. The smallest error (3.7%) and greatest agreement between the two methods was found in the supine position (93.3% of the IP measurements within +/- 10% of the PNT measurements). An IP application that could be used to collect data over the long term and which is in good agreement with PNT was developed by employing a "virtual instrument" (VI, LabView) for flexible data acquisition and data processing. Agreement was best when the volunteer adopted a supine position. A smaller correlation was found in standing or seated subjects. This might be due to the fact that in the latter two positions, the respiratory system may have more than 2 degrees of freedom, and thus cannot be adequately monitored by only two bands around the thorax and abdomen. Signals produced by cardiac activity were detectable on the surface of the body.

A 1.9-GHz CMOS VCO with micromachined electromechanically tunable capacitors

This paper presents a 1.9-GHz CMOS voltage-controlled oscillator (VCO) where the resonant circuit consists of micromachined electromechnically tunable capacitors and a bonding wire inductor. The tunable capacitors were implemented in a MUMP's polysilicon surface micromachining process. These devices have a nominal capacitance of 2.1 pF and a quality factor (Q-factor) of 9.3 at 1.9 GHz. The capacitance is variable from 2.1 pF to 2.9 pF within a 4-V control, voltage range. The active circuits were fabricated in a 0.5-/spl mu/m CMOS process. The VCO was assembled in a ceramic package where the MUMP's and CMOS dice were bonded together. The experimental VCO achieves a phase noise of -98 dBc/Hz and -126 dBc/Hz at 100 kHz and 600 kHz offsets from the carrier, respectively. The tuning range of the VCO is 9%. The VCO circuit and the output buffer consume 15 mW and 30 mW from a 2.7-V power supply, respectively.

Minimization of wiring inductance in high power IGBT inverter

The wiring inductance is one of main causes limiting the use of the inverter in hard commutation mode, particularly when voltage, current and switching frequency are increased. The busbar technology is the means that allows one to reach low wiring inductance between DC source and power switches in spite of relatively long connections. This paper deals with studies of busbar structure applied to the high power inverters in order to improve their performances. Two structures of wiring are tested; the traditional one and busbar technology. Experimental and simulation results show that this last technique permits to obtain very low wiring inductance so that no snubber circuits are needed.

Microwave MEMS-based voltage-controlled oscillators

A microwave voltage-controlled oscillator (VCO) based on coupled bonding wire inductors and microelectromechanical system (MEMS)-based variable capacitors for frequency tuning is demonstrated in this paper. The MEMS-based variable capacitors were fabricated in a standard polysilicon surface micromachining technology. The variable capacitors have a nominal capacitance of 1.4 pF and have a Q factor of 23 at 1 GHz and 14 at 2 GHz. The capacitance is variable from 1.4 to 1.9 pF as the tuning voltage is swept from 0 to 5 V. The VCO, fabricated in a 0.5 /spl mu/m CMOS technology, was assembled in a ceramic package where MEMS and CMOS dice were bonded together. The oscillator operates at 2.4 GHz, achieves a phase noise of -122 dBc/Hz at 1 MHz offset from the carrier, and exhibits a tuning range of 3.4%.

Fully Integrated Low Phase-Noise VCOs: From Special Processing to Standard CMOS

An overview is given on the several options for and problems associated with creating high-quality integrated inductors for VCOs. Special processing techniques are reported that can enhance the performance of a normal planar inductor coil. Bonding Wire inductors are presented as an alternative, that allows state-of-the-art phase noise performance at no extra cost. Finally, it is shown that by thorough analysis of standard planar inductors with finite-element simulations, performances can be achieved that are even better than structures requiring extra processing cost. This is done despite a low-ohmic substrate with only two metal layers.

A novel GaAs flip-chip power MODFET with high gain and efficiency

A novel GaAs flip-chip power MODFET with a spike-gate structure has been developed for high-gain and high-efficiency operation under extremely low supply voltages. The spike-gate MODFET is featured by a unique gate structure that has almost zero effective gate length. The spike gate provides both a low on-resistance of 1.5 Ω mm and a high transconductance of 280 mS/mm without increasing the drain conductance. The flip-chip bonding, with an Au–Sn alloy system, has been used for mounting of the spike-gate power MODFET on an AlN substrate. The thermal resistance of the flip-chip power MODFET is 12°C/W which is lower than that of a conventional wire-bonded MODFET. The power-added efficiency (PAE) of 71% at the output power of 30.0 dBm can be obtained even when the supply voltage is reduced to 1.5 V. By eliminating parasitic wire inductance, the linear gain of the MODFET is 2 dB higher and the PAE is 5% higher than that of the conventional wire-bonded MODFET.

Equivalent-circuit modeling and verification of metal-ceramic packages for RF and microwave power transistors

A modeling procedure was developed to generate electrical package models for metal-ceramic packages. These models are capable of accounting for package effects associated with the package lead capacitance, the self and mutual inductances of the bond wires, and the coupling between the input and output of the package. A combination of full-wave electromagnetic simulation and equivalent-circuit model extraction allows accurate model generation and efficient circuit simulation. Measured S-parameters were used to verify the overall modeling methodology. It has been demonstrated that the package effects play an important role in the accurate prediction of the packaged transistor performance.

Determination of characteristics of the discharge current by the human charge model ESD simulator

This paper aims at improved reproducibility of the electrostatic discharge current in the electrostatic tester that simulates the electrostatic discharge from the charged human body. The variation of the electrostatic discharge current due to changed testing conditions, including the position relation, is analyzed. The derivation method, where the components of the electrostatic tester, such as the discharge gun and the ground wire, are replaced by electrical parameters, is combined with the method of circuit analysis by simulation. The characteristics of the electrostatic tester are analyzed, and the following situations are revealed. Even though the inductance of the ground wire varies greatly with the testing condition, the main discharge current satisfies the rated value. The initial current is generated depending on the switch structure of the tester, and is caused by the stray capacitance around the discharge current limiting resistor. The proposed circuit model exactly represents those characteristics of the electrostatic tester. By combining the proposed circuit model into the EDA (electronic circuit design automation) system, the circuit designer can simulate the electrostatic discharge at the design stage. This makes it easy for the designer to interpret the characteristics in the electrostatic testing, and can reduce the trial-and-error effort. © 1997 Scripta Technica, Inc. Electron Comm Jpn Pt 1, 80(10): 49–57, 1997

Determination of characteristics of the discharge current by the human charge model ESD simulator

This paper aims at improved reproducibility of the electrostatic discharge current in the electrostatic tester that simulates the electrostatic discharge from the charged human body. The variation of the electrostatic discharge current due to changed testing conditions, including the position relation, is analyzed. The derivation method, where the components of the electrostatic tester, such as the discharge gun and the ground wire, are replaced by electrical parameters, is combined with the method of circuit analysis by simulation. The characteristics of the electrostatic tester are analyzed, and the following situations are revealed. Even though the inductance of the ground wire varies greatly with the testing condition, the main discharge current satisfies the rated value. The initial current is generated depending on the switch structure of the tester, and is caused by the stray capacitance around the discharge current limiting resistor. The proposed circuit model exactly represents those characteristics of the electrostatic tester. By combining the proposed circuit model into the EDA (electronic circuit design automation) system, the circuit designer can simulate the electrostatic discharge at the design stage. This makes it easy for the designer to interpret the characteristics in the electrostatic testing, and can reduce the trial-and-error effort. © 1997 Scripta Technica, Inc. Electron Comm Jpn Pt 1, 80(10): 49–57, 1997

Josephson-junction arrays with long-range interactions

We calculate the current-voltage $(\mathrm{IV})$ characteristics of a Josephson-junction array with long-range interactions. The array consists of two sets of equally spaced parallel superconducting wires placed at right angles. A Josephson junction is formed at every point wherever the wires cross. We treat each such junction as an overdamped resistively shunted junction, and each wire segment between two junctions as a similar resistively shunted junction with a much higher critical current. The $\mathrm{IV}$ characteristics are obtained by solving the coupled Josephson equations numerically. We find that, for a sufficiently large number of wires, the critical current saturates at a finite value because of the wire inductance, in excellent agreement with experiment. The calculated $\mathrm{IV}$ characteristics also show a striking hysteresis, even though each of the individual junctions is nonhysteretic. The hysteresis results from a global redistribution of current flow on the upper and lower voltage branches, and is also in excellent agreement with experiment.

An improved NbN integrated circuit process featuring thick NbN ground plane and lower parasitic circuit inductances

We report on the development of a 10 K, NbN superconductive integrated circuit (IC) technology that utilizes an improved SiO/sub 2/ interlevel dielectric (ILD) deposition process and a thick NbN ground plane layer to reduce parasitic circuit inductances. The ILD process uses a novel low frequency (40 kHz) substrate bias during sputter deposition of SiO/sub 2/, which produces very smooth oxide films having a roughness less than 0.1 nm (rms) as measured by atomic force microscopy (AFM). Bias-sputtered SiO/sub 2/ is used to planarize and to smooth the surface of the NbN ground plane layer in preparation for fabrication of NbN/MgO/NbN tunnel junctions. High current density tunnel junctions ranging from 1000 A/cm/sup 2/ to 5000 A/cm/sup 2/, fabricated over NbN ground planes up to 1 /spl mu/m thick, exhibit low subgap leakage (V/sub m//spl sim/15 mV at 10 K) and high subgap voltage (V/sub g/=4.4 mV at 10 K). Typical wiring inductance over ground plane has been reduced by 25% compared to our present NbN foundry process.

Silicon MOSFET distributed amplifier

The first reported integrated silicon MOSFET distributed amplifier is presented. A three stage distributed amplifier was fabricated on a standard 0.8 µm silicon CMOS foundry process and packaged in a SSO-24 plastic surface mount package. The required inductance needed for distributed amplification is realised by the parasitic inductance of the bond wires and lead frame inductance inside the plastic surface mount package. The distributed amplifier has a unity gain cutoff frequency of 4.7 GHz, a gain of 5 dB and an input referred third order intercept point of +15 dBm.

Wideband characterization of a typical bonding wire for microwave and millimeter-wave integrated circuits

A typical grounded bonding wire with a minimum total length of 480 /spl mu/m for MMIC's and OEIC's is characterized using the method of moments with the incorporation of the ohmic loss as well as the radiation loss over a wide range of frequencies. The distributed ohmic resistance is calculated by an application of the Phenomenological Loss Equivalence Method. The simulated results show the wire resistance and the inductance increase greatly at frequencies above 30 GHz due to the high radiation effect enhanced by the slow-wave effect of the ohmic loss. The bonding wire is highly inductive in most of the frequency range and the maximum quality factor is mostly limited by the ohmic resistance. The results also show the simple static modeling of computer-aided design software that considers only the free-space wire inductance and the shin-effect resistance, overestimates the wire inductance at low frequencies, and is inappropriate at high frequencies due to the high radiation effect. This approach can be applied to many arbitrarily shaped interconnection wires for wideband design and characterization of high-frequency integrated circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>