Wire Delay Research Articles

Experience from a regional percutaneous coronary intervention center: Aiming to assess and improve quality of care

Introduction and ObjectivesIschemic heart disease is the single most common cause of death in Europe. Mortality in patients presenting with ST-elevation myocardial infarction (STEMI) is associated with many factors, one of which is the time delay to treatment. The purpose of this work is to analyze the coronary pathway in our region in terms of timing, taking into consideration the place of first medical contact (FMC). MethodsConsecutive patients admitted to our center with STEMI to undergo percutaneous coronary intervention (PCI) between 2013 and 2022 were analyzed. Age, gender, and time delays were collected. Analysis was performed with IBM SPSS version 28 for a significance level of 0.05. ResultsWe found that non-PCI centers had a significantly greater FMC to diagnosis delay and diagnosis to wire delay compared to other places of origin. Only 2.2% of patients met the 10-min FMC to diagnosis target; 44.8% met the target of 90 min from diagnosis to wire in transferred patients, while 40.6% met the 60-min target for patients admitted to a PCI center. Median patient, electrocardiogram (ECG) and logistic delays are 92.0±146.0 min, 19.0±146.0 min and 15.5±46.3 min, respectively. ConclusionA significant difference between state-of-the-art targets and reality was found, depending on the place of FMC, with the worst delays in non-PCI centers. Patient delay, ECG delay, FMC to diagnosis and logistic delay are identified as key areas in which to intervene.

TNT: A Modular Approach to Traversing Physically Heterogeneous NOCs at Bare-wire Latency

The ideal latency for on-chip network traversal would be the delay incurred from wire traversal alone. Unfortunately, in a realistic modular network, the latency for a packet to traverse the network is significantly higher than this wire delay. The main limiter to achieving lower latency is the modular quantization of network traversal into hops. Beyond this, the physical heterogeneity in real-world systems further complicate the ability to reach ideal wire-only delay. In this work, we propose TNT or Transparent Network Traversal . TNT targets ideal network latency by attempting source to destination network traversal as a single multi-cycle ‘long-hop’, bypassing the quantization effects of intermediate routers via transparent data/information flow. TNT is built in a modular tile-scalable manner via a novel control path performing neighbor-to-neighbor interactions but enabling end-to-end transparent flit traversal. Further, TNT’s fine grained on-the-fly delay tracking allows it to cope with physical NOC heterogeneity across the chip. Analysis on Ligra graph workloads shows that TNT can reduce NOC latency by as much as 43% compared to the state of the art and allows efficiency gains up to 38%. Further, it can achieve more than 3x the benefits of the best/closest alternative research proposal, SMART [ 43 ].

Enabling circuit-switching in modern on-chip networks

Contemporary flow control mechanisms, especially virtual channels, are employed by modern on-chip networks to allow better utilization of the link bandwidth through buffering and packet switching. Despite of being the de facto option in designs, they are also the sources of large energy footprint and long per-hop latency. On the other hand, dated and simpler flow controls such as circuit switching can draw far less power while offering an end-to-end latency analogous to wire delay. In this paper, we therefore take a further step from utilizing a single flow control mechanism within the network to allowing circuit-switching to work alongside virtual channels, which provides latency-competitive and energy-efficient on-chip network designs. Furthermore, to enable circuit switching in modern networks-on-chip, we present two independent proposals so that circuits can be formed in a network either temporally or spatially. In our evaluations, we find that both of our proposals can help achieve a very competitive latency per flit, for up to 30% lower with the temporal approach and for up to 10% lower with the spatial approach, while also dramatically suppressing the energy footprint with either approach by up to 27% and 25%, respectively.

A Novel Design for Low-Power, High Performance and Space Efficient Address Decoder for SRAM

Abstract: We discover the optimum decoder structure for fast low-power SRAMS. The results are ideal when the decoder is designed as a binary tree without the precoder. We find that skewed circuits with self-resetting gates work well, and we explore some basic scaling algorithms for minimal delay and power in the SRAM data path. Signal oscillations on high capacitance nodes like bit lines and data lines are decreased, resulting in low power operation. Clocked voltage sense amplifiers are required for low sensing power, and accurate construction of their sense clock is required for high-speed operation. By restricting bit line and NO line swings, we examine tracking circuits to aid in the development of the sense clock and allow timed sense amplifiers. The tracking circuits successfully use a replica memory cell and a replica bit line to track the memory cell's delay throughout a wide variety of manufacturing and operating conditions. The results of two different prototypes' experiments are reported. Finally, we investigate the speed and power development trends of SRAMs as a function of size and technology, discovering that if the connection delay is negligible, the SRAM delay grows as the logarithm of its size. Wire delay becomes increasingly important for SRAMs after the fifth generation. The wire delay worsens as the process shrinks, requiring wire redesign to keep the wire delay proportionate to the gate delay. Hierarchical SRAM topologies provide enough of array space for fat Wires and may be used to control time. Throughout the procedure, the wire delay for 4Mb and smaller designs diminishes. Keywords: SRAMs, High Performance, Delay, Clock, Decoder

UP-Down OLC: New One-Lambda Crosstalk Avoidance Code Design Based on 5-Wire Model

Crosstalk fault avoidance codings (CACs) is extensively utilized. Among promising existing CACs methods, the one which has attracted much attention due to worst-case crosstalk fault delay prevention is One-Lambda Codes (OLCs). Unfortunately, two challenging issues are coming their way: 1- Exact model is required to estimate an exact delay of wires to provide accurate OLCs. 2- OLCs codec suffers from high energy consumption and overhead caused by critical path and area occupation. In this research, an accurate probability model is introduced to overcome these problems by Accurate Crosstalk Model (ACM) prediction. If crosstalk faults show up, ACM can estimate the communication channels delay by using 5- wire delay. It can help to improve the recently proposed analytical model that suffers from a lack of accuracy. Next, we present an accurate UP-Down OLC (UD-OLC) based on the numeral system and can eliminate transition patterns, including OLC-induced patterns, completely. In comparison with the other state-of-the-art OLCs, the UD-OLC mapping algorithm effectively alleviates wires energy consumption and average latency by up to 61% and 27%. Experimental results also reveal that this an overhead efficient numeral-based method benefits from the overhead degradation in terms of dynamic power, area, and critical path by up to 52%, 45%, and 20%, respectively when we compared it to the others.

The Root Tile Design for Level 1 Cache for Non Uniform Architecture

NUCA has become solution for wire delay problems, where wire delay problems increases on chip latency in multiprocessor system. Non uniform architecture is used for cache memory. Here cache is divided into tiles ,each tiled cache is accessed with different latency. Hence it is called non uniform. Access data defines search algorithm across architecture. This paper involves design of root tiles which accepts request from processor and forward request to child cache tiles. Here we have used Xilinx simulation tool to analyze the performance.

ST-CAC: a low-cost crosstalk avoidance coding mechanism based on three-valued numerical system

Appearances of specific transition patterns during data transfer in bus lines of modern high-performance computing systems, such as communicating structures of accelerators for deep convolutional neural networks, commercial Network on Chips, and memories, can lead to crosstalk faults. With the shrinkage of technology size, crosstalk faults occurrence boosts and leads to degradation of reliability and performance, as well as the increasing power consumption of lines. One effective way to alleviate crosstalk faults is to avoid the appearance of these specific transition patterns by using numerical-based crosstalk avoidance codes (CACs). However, a serious problem with numerical-based CACs is their overheads in terms of required additional bus lines for representing code words. To solve this problem, in this paper we present a novel CAC that is based on the use of three symbols (three-value) to represent the code words in the bus lines, rather than classical binary CACs based on binary, i.e., 0 and 1 symbols. Our proposed CAC, named summation-based tri-value crosstalk avoidance code (ST-CAC), reduces the worst-case delay in bus lines with respect to binary CACs, and it can efficiently be applied to any arbitrary channel width of lines. The use of three symbols to represent code words in ST-CAC enables to increase the number of code words of a numerical system without increasing the number of required bus lines significantly. The experimental results show that CACs based on the use of three symbols can reduce the number of additional lines compared to binary CACs by 33%. Moreover, we show in the paper, that the delay of wires in the presence our ST-CAC can reduce by 33% with respect to state-of-the-art binary value CACs.

QSTA: A Static Timing Analysis Tool for Superconducting Single-Flux-Quantum Circuits

Superconducting single-flux-quantum (SFQ) technology is a beyond-complementary metal–oxide–semiconductor (CMOS) technology, promising ultrahigh processing speed and low power consumption. A timing analysis tool for SFQ circuits should check circuit timing behavior, including working frequencies and hold time violations to determine the circuit performance. Unlike CMOS gates, generic SFQ gates are clocked gates, which produce their output pulses in response to a clock pulse and have a fan-out capability of one. An SFQ splitter, a special clockless gate that has a fan-out capability of two, is used to address the fan-out limitation. This gate is also utilized in the clock tree, which distributes clock pulses to various SFQ gates. The delay of a clock path in a clock tree is determined by the wire delays of connection nets and gate delays of splitters. However, the splitter delays in a clock path are significantly affected by process variations, resulting in a challenging skew problem. Furthermore, existing timing analysis tools of SFQ circuits are developed based on the timing definitions, rules, and constraints from CMOS technology with very few modifications. This article demonstrates the incompleteness of the existing SFQ technology timing definitions. Precisely, it presents a novel static timing analysis (STA) tool, qSTA, which checks the timing behavior of SFQ circuits based on revised definitions of the setup time and hold times. qSTA encompasses the common path pessimism removal technique, which removes the delays of the shared path segments between two clock paths to achieve a better approximation of real skew values. qSTA takes only 5.33 s to check the timing behavior of a 16-bit integer divider with 36 732 gates and 55 939 nets.

Boundary scan based interconnect testing design for silicon interposer in 2.5D ICs

Interposer-based 2.5-dimensional integrated circuit (2.5D IC) is considered as a promising solution to problems like wire delay and power consumption faced by the semiconductor industry today. Since the interconnect wires in the silicon interposer may be defective during fabrication and assembly, they must be adequately tested to ensure product qualification. This paper presents an efficient interconnect test architecture to detect open, short and delay faults, which is compatible with the IEEE 1149.1 standard. It provides a new boundary scan structure with low test power consumption. To reduce the overall test cost, a data-package based test structure is proposed to match the test data transfer volume between TSVs and scan chains. Interconnects of multiple dies can be tested simultaneously under constrains of test power with minimum external test pins. The simulation results validate the effectiveness of the proposed test method. We also present synthesis results to evaluate the area overhead.

Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell Delay

Satisfying timing requirements is the most challenging phase of the modern complex system-on-chip (SOC) design. The timing closure of the static timing analysis (STA) is a necessary but time-consuming stage before tapeout. Physical design tools are normally ineffective in obtaining accurate timing estimates, so the accurate timing calculation must be conducted in the signoff level timer after each physical modification on designs. This paper proposes a way to reduce the number of iterations between the signoff timer and the physical implementation procedures. Approximate timing models for extracting the signoff timer information and the nonlinear library are used in the optimization of the timing-driven placement (TDP). The accurate estimation of net and cell delays is integrated into TDP, so the optimal positions of cell movement can be obtained. This postoptimization algorithm was entered into the benchmark of the ICCAD15 incremental timing-driven contest, and the embodiments were obtained from the top three teams. Under the same design constraints, the proposed method yielded significant improvements in all kinds of default design chip.

Reconfigurable Clock Networks for Wide Voltage Scaling

In this paper, reconfigurable clock networks for adaptation from nominal voltage down to sub-threshold voltages are presented. Indeed, clock network design tradeoffs at near- and sub-threshold voltages substantially differ from above-threshold voltages, due to the very different balance between clock repeater and wire delay. In the proposed reconfigurable clock network scheme, the number of repeater levels is dynamically adapted to the supply voltage to mitigate the clock skew degradation across a wide voltage range. At nominal voltage, the number of repeater levels is adjusted to a higher value to mitigate the important clock skew contribution of wires. At lower voltages, it is progressively lowered to mitigate the dominant clock skew contribution of clock buffers. The proposed approach is demonstrated on a 256-point complex fast Fourier transform (FFT) processor test chip in 40 nm, and a standalone clock tree to statistically characterize the skew. Measurements show that the proposed reconfigurable clock network reduces clock skew by up to 3.3 $\times $ , enabling 110-mV $V_{\mathrm {min}}$ reduction and 31% minimum energy reduction at 1.8% area penalty, compared to traditional fixed clock networks.

Leakier Wires

In complex FPGA designs, implementations of algorithms and protocols from third-party sources are common. However, the monolithic nature of FPGAs means that all sub-circuits share common on-chip infrastructure, such as routing resources. This presents an attack vector for all FPGAs that contain designs from multiple vendors, especially for FPGAs used in multi-tenant cloud environments, or integrated into multi-core processors. In this article, we show that “long” routing wires present a new source of information leakage on FPGAs, by influencing the delay of adjacent long wires. We show that the effect is measurable for both static and dynamic signals and that it can be detected using small on-board circuits. We characterize the channel in detail and show that it is measurable even when multiple competing circuits (including multiple long-wire transmitters) are present and can be replicated on different generations and families of Xilinx devices (Virtex 5, Virtex 6, Artix 7, and Spartan 7). We exploit the leakage to create a covert channel with 6kbps of bandwidth and 99.9% accuracy, and a side channel, which can recover signals kept constant for only 1.3sμs, with an accuracy of more than 98.4%. Finally, we propose countermeasures to reduce the impact of this leakage. 1

Effects of Dummy Thermal Vias on Interconnect Delay and Power Dissipation of Very Large Scale Integration Circuits

The interconnect temperature of very large scale integration (VLSI) circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.

An efficient and low power one-lambda crosstalk avoidance code design for network on chips

Crosstalk faults occurring in wires of Networks on Chip (NoCs) can seriously threaten the reliability of data transfer. One efficient way to tackle crosstalk faults is numeral-based Crosstalk Avoidance Codes (CACs). Numeral-based CACs reduce crosstalk faults by preventing specific transition patterns to occur. One-Lambda Codes (OLCs) are the most efficient types of CACs. However, the codec of OLCs imposes overheads including power consumption, critical path and area occupation to the routers of NoCs. To find overhead-efficient OLCs, this paper proposes an Algorithm for Generating OLC Numeral systems (AGON). AGON provides a tradeoff for designers in selecting overhead-efficient OLCs. Using AGON, an efficient numeral-based OLC called Subtraction-based-Numeral (Sub-Num) is proposed that benefits the Numeral system that can omit OLC-induced transition patterns completely. In addition, the mapping algorithm of Sub-Num can reduce the overheads of codec more efficiently than the other state-of-the art OLCs. Evaluation results using SPICE and VHDL simulations show that Sub-Num reduces power consumption and average delay of wires by 10% and 9%, and also overheads of codecs including dynamic power consumption, critical path and area occupation by 52%, 51% and 21%, respectively as compared to the state-of-the-art numeral-based OLC.

A Static Timing Analysis Tool for RSFQ and ERSFQ Superconducting Digital Circuit Applications

Static timing analysis in the rapid-single-flux-quantum and energy-efficient RSFQ superconducting digital circuit domain is yet to be achieved in a generic sense. A static timing analysis tool is proposed here for preplacement designs as well as postplaced and routed designs. Preplaced static timing analysis attempts to find a general gauge for the performance of a JSIM/SPICE netlist in the absence of information on wiring delays. The postplaced and routed static timing analysis provides a more accurate analysis of a design in the cadence design exchange format. This design file should include all the wire lengths as well as a complete clocking scheme. Results of this postplaced and routed static timing analysis are then used to determine the maximum clock speed that the design can be run at to prevent timing violations. Results for both methods of analysis are presented and then incorporated in an hardware description language representation of the design to show that there are no timing violations at the presented clock speed. We show the implementation of a static timing analysis method developed as a precursor to the IARPA SuperTools project, and how it applies to circuits with H-tree and HL-tree clocking schemes.

Low power NoC architecture based dynamic reconfigurable system

The on chip communication intention is difficult due to communication necessities and the difficulty of the objective application is great. Notably, different communication areas might be actualized utilizing a similar chip range, for example, to enable various parallel applications to be stacked onto the device. So the system on chip (SoC) deployed in different topologies with different design parameters to achieve the requirements of the target application. Classical communication methods such as point to point, the bus is not an appropriate solution for future SoCs. That is difficult to send signals starting with one end then onto the next term of a clock cycle. Issues, for example, global wire delay and global synchronization will restrict us. With a specific end goal to beat these problems, architect utilizes new models, procedures, and tools from network design field and apply them to SoCs plan that prompts modern worldview called network on a chip. In this paper, the design components used and the operation of the proposed architecture is same with network on chip (NoC) approach. But it differs in the communication architecture with the introduction of the on-chip peripheral bus. And it differs from the NoC by its switching networks. We modified the switching system that is developed to support dynamically reconfigurable network. Due to this modification in the switching system restrict the area and the power use of the NoC.

Thread Criticality Assisted Replication and Migration for Chip Multiprocessor Caches

Non-Uniform Cache Architecture (NUCA) is a viable solution to mitigate the problem of large on-chip wire delay due to the rapid increase in the cache capacity of chip multiprocessors (CMPs). Through partitioning the last-level cache (LLC) into smaller banks connected by on-chip network, the access latency will exhibit non-uniform distribution. Various works have well explored the NUCA design, including block migration, block replication and block searching. However, all of the previous mechanisms designed for NUCA are thread-oblivious when multi-threaded applications are deployed on CMP systems. Due to the interference on shared resources, threads often demonstrate unbalanced progress wherein the lagging threads with slow progress are more critical to overall performance. In this paper, we propose a novel NUCA design called thread C riticality A ssisted R eplication and M igration (CARM). CARM exploits the runtime thread criticality information as hints to adjust the block replication and migration in NUCA. Specifically, CARM aims at boosting parallel application execution through prioritizing block replication and migration for critical threads. Full-system experimental results show that CARM reduces the execution time of a set of PARSEC workloads by 13.7 and 6.8 percent on average compared with the tradition D-NUCA and Re-NUCA respectively. Moreover, CARM also consumes much less energy compared with the evaluated schemes.

Wire Optimization and Delay Reduction for High-Performance on-Chip Interconnection in GALS Systems

To address the wire complexity problem in large-scale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using 0.25-μm CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.

Redressing fork constraints in nanoscale quasi-delay-insensitive asynchronous pipelines

The class of quasi-delay-insensitive (QDI) asynchronous circuits provides a promising approach toward tolerating process variations. However, the fundamental assumption of QDI circuits is that some wires in such circuits are isochronic; this assumption is more and more challenged by the shrinking technology. This paper redresses the weakest fork timing constraints for QDI asynchronous pipelines to work correctly under arbitrary wire and gate delay variability. We model a QDI circuit using the signal transition graph and propose a method to detect isochronic fork candidates. Extensive analysis is exploited to justify the necessary and sufficient isochronic fork selections of a QDI template. The proposed method works for many QDI templates, and it provides some necessary information about the constraint on any wire fork required for an asynchronous EDA tool in nanotechnology era. Experimental results demonstrate that the proposed method results in more robust QDI circuits in the expense of the least design overheads comparing to the similar method suggested in the current literature.

Performance Scalability of Adaptive Processor Architecture

In this article, we evaluate the performance scalability of architectures called adaptive processors, which dynamically configure an application-specific pipelined datapath and perform a data-flow streaming execution. Previous works have examined the basics of the following: (1) a computational model that supports the swap-in/out of a partial datapath—namely, a virtual hardware is realized by hardware, without a host processor and its software; (2) an architecture that has shown a minimum pipeline requirement and a minimum component requirement; and (3) the characteristics of the execution phase and a stack shift that realizes the swap-in/out. However, these works did not explore the design space, particularly with respect to the following: (1) the clock cycle time on the adaptive processor, which must depend on a wire delay that is primarily used for the global communication of requests, acknowledgments, acquirements, releases, and so forth, and (2) a revised control system that can handle the out-of-order acknowledgment and in-order acquirement that guarantee the correct datapath configuration with a conditional branch for the configurations. This article explores the scaling of the ALU resources versus pipelining of the wires.