Wideband Frequency Synthesizer Research Articles

Radar hybrid signal generators based on high-speed digital-to-analog converters

Wideband frequency synthesizers are used in many different applications, such as radars, telecommunications and others. Radar parameters are dependent on the synthesizers phase noise. A general flow-chart of a hybrid frequency synthesizer based on direct digital and direct analog synthesis methods that uses a high-speed digital-to-analog converter (DAC) in special operating modes to increase the operating frequency is presented in this paper. The noise characteristics of a hybrid synthesizer with a DAC operating in two modes are simulated.

A 0.045- to 2.5-GHz Frequency Synthesizer With TDC-Based AFC and Phase Switching Multi-Modulus Divider

A 0.045- to 2.5- GHz wideband frequency synthesizer (FS) employing time-to-digital converter (TDC) based automatic frequency calibration (AFC) method and phase switching (PS) multi-modulus divider (MMD) is presented in this paper. The traditional counter-based AFC method takes several reference cycles to calculate the instantaneous voltage-controlled oscillator (VCO) frequency, while the proposed TDC-based technique consumes only 2 cycles. In order to suppress the quantization noise caused by the sigma-delta modulator (SDM) in the MMD, the loop division step is reduced from 2 to 0.5 by adopting the PS technique. The FS is designed and implemented using TSMC 180nm RF CMOS process and provides the phase noise performance of −99.5 / −123.5 dBc/Hz at 10kHz/1MHz offsets under 2.4 GHz carrier frequency. The AFC time measurement results for a 6-bit cap-array are 1.25-, 2.5- and 5- $\mathrm {\mu s}$ when employing 48-, 24- and 12-MHz reference frequencies respectively. The chip area including pads and I/Os is 2.31 mm $^{\mathbf {2}}$ and the total power consumption is 108 mW.

A 0.03- to 3.6-GHz Frequency Synthesizer With Self-Biased VCO and Quadrature-Input Quadrature-Output Frequency Divider

A 30 MHz–3.6 GHz wideband frequency synthesizer with a self-biased oscillator and quadrature-input quadrature-output (QIQO) dividers for software-defined radio applications is presented in this brief. The self-biased oscillator employs a novel cross-coupled negative-Gm pair that performs an equivalent linearized negative resistance, mitigating the noise folding process. The QIQO dividers are utilized to divide the quadrature signals and incorporate with a quadrature single sideband mixer for post synthesizing. The synthesizer is implemented in TSMC 180-nm RF CMOS process and provides a phase noise performance of −125.4 dBc/Hz and −122.9 dBc/Hz at 1 MHz offset under 1.8- and 2.7-GHz carriers, respectively. The maximum power consumption is 135 mW and the die size, including pads and I/O is 2.9 mm $^{{2}}$ .

Electronic Amplifier for Modern Acousto-Optical Spectrometers

The paper presents an analysis of electronic amplifiers for modern acousto-optical spectrometers, based on two-crystal sequential diffraction of incident radiation by acoustic waves propagating in each acousto-optical (AO) cell. Such a diffraction scheme has a higher spectral resolution, retaining all the other advantages of traditional AO spectrometers. A description of the functional block diagram of a two-crystal AO spectrometer is given, and the necessary requirements for electronic units are indicated. The results of joint use of the signal power amplification device and a previously developed wideband frequency synthesizer for exciting sound waves in AO cells are presented; output amplitudes of amplified signals are obtained.

Wireless Power Transfer Solutions and Their Effectiveness [Georgia Institute of Technology

My research focuses on the problems related to the creation of a wireless power transfer system designed for energy transmission at a distance of at least one meter. The project was created to provide data for the advancement of wireless power, specifically via radio frequency transmission. Previous research efforts that attempted to develop this technology have run into unforeseen obstacles that have hindered its consumer and commercial adoption. This research will yield more information into those barriers and what can be done to assist wireless power in its future development as an applied technology. To begin producing data, a wireless power system first must be created. The central design element of the transmitter was a Texas Instruments PLL and integrated VCO wideband frequency synthesizer programmed to output a 3.6GHz sine wave. That signal was then passed into a GaN amplifier integrated circuit from Analog Devices and finally transmitted via a wideband Molex antenna. The receiver circuit was much simpler, simply consisting of a second Molex antenna and a bridge rectifier circuit to convert the AC signal to DC. A multipurpose ATmega328 programs the frequency synthesizer on the transmitter and reads the voltage and current from the receiver with its integrated ADC. The research is currently still in progress, but the data that has been accumulated shows that transmission is possible but with lower power yields than initially expected. The maximum range of received power was one meter, but because the transmitted voltage and current did not meet the calculated values, the project must have reached one or more of the unknown obstacles in wireless power design. To isolate and learn more about them, the project will be revised to gather more data. It will change into different models of power transfer and be tested for their effectiveness for the benefit of future research in this topic.

A Quadrature Single Side-Band Mixer with Passive Negative Resistance in Software-Defined Frequency Synthesizer.

Software-defined radio (SDR) is a good solution for complying with the existing and incoming protocols for emerging wireless sensor networks (WSN) and internet of things (IoT) applications. The frequency synthesizer in a SDR tranceiver usually consists of a phase locked loop (PLL) and a post synthesizer. The PLL is the narrow band signal source and the post synthesizer generates wideband outputs by mixing and dividing. Compared with a frequency synthesizer utilizing the wideband PLL, this synthesizer features relatively constant loop parameters and mitigates the requirement for the oscillator. In this paper, a quadrature single side-band (QSSB) mixer with the proposed passive negative resistance (PNR) for frequency mixing in a post synthesizer is presented. The PNR is achieved by biasing the Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFET) of the cross-coupled pair at the deep-triode region periodically and incorporates an inductor and a cap-array as the mixer load. Compared with the traditional single side-band mixers utilizing Inductor-Capacitor (LC) resonant loads or quality factor enhanced (Q-enhanced) LC resonant loads, which suffer from a selectivity versus working range trade-off, the mixer employing the proposed loading structure provides not only a wide operating range, but also a superior image side-band rejection ratio (ISRR). Moreover, the oscillating risk in conventional mixers adopting Q-enhanced LC resonant loads is eliminated. A wideband frequency synthesizer employing the proposed mixer was implemented in a TSMC 0.18 µm CMOS process and the mixer performed ISRR of 40–57 dB and 30–57 dB across 2.5–3 GHz and 2.3–3.2 GHz, respectively. The power consumption of the QSSB mixer, including buffer, is 18 mA from a 1.8 V supply and the active area is 0.445 mm2. The measurement results provide validation that the proposed QSSB mixer is suitable for wideband software-defined frequency synthesizers and other frequency generating systems.

Research on High Performance Frequency Synthesizer in Radio Frequency Integrated Circuits

With the popularization of broadcasting networks, telecommunication networks, and Internet triple play services, broadband requirements have been proposed for transceivers in wireless communication systems. Frequency source is an important part of the RF transceiver, which is usually chosen as the source of the transceiver frequency reference source. Therefore, the development of ultra-wideband, high stability, low phase noise, and low spurious performance of the frequency synthesizer is of great significance. This paper firstly analyzed the transmission process of noise in phase-locked loop by establishing a linear mathematical model of phase locking loop (PLL), and then studied the main factors affecting the phase noise and spurious performance in the application design. In order to meet the demand of triple-miniaturized RF front end, an integrated phase-locked chip is used to design a frequency synthesizer, where the output frequency of the two channels ranges from 137.5 MHz to 4.4 GHz. In order to meet the engineering application requirements, the frequency synthesizer is designed with a host computer to achieve the programmable control of the output frequency and output power. Finally, the optimized design of a wideband frequency synthesizer is provided to make up for the lack of performance of the integrated phase-locked chip design, of which the output frequency range is 31.25 MHz ~8 GHz, including basic PLL module circuit, power control module circuit, and frequency expansion module circuit.

A DDS-PLL hybrid based fast settling wideband frequency synthesizer for frequency hopping radios

The new generation software defined radios implement a wideband RF front-end which calls for a wideband frequency synthesizer for generating the local oscillator signal. Moreover military applications demands frequency hopping capability also. A single wideband synthesizer was developed based on a translation loop architecture using a DDS and two PLLs in conjunction with a frequency mixer. The highlights of this design include fast switching speed and narrow tuning resolution advantages of DDS combined with the very low phase noise and spurious performance of PLL. An exhaustive simulation of this design done in AWR VSS software is given in reference 1.

A broadband CMOS RF receiver for digital broadcasting systems

Nowadays digital radio systems are replacing analog radio systems. In this paper, a CMOS RF receiver with frequency synthesizer and analog baseband is introduced, which was fabricated with a 0.18-µm CMOS process for DRM/DAB wideband applications. In the system, a fully differential low noise amplifier with a noise cancelling technology is adopted It has achieved a gain of 11.69 dB. A harmonic rejection mixer was implemented to realize the rejections of 3rd- and 5th-order harmonics. As the local oscillator, a wide-band frequency synthesizer provides a phase noise of ?125 dBc/Hz at 1-MHz offset. The designed RF receiver has achieved a conversion gain of 90 dB. The IIP3 of the receiver is in the range of ?25 to ?12 dBm, and the noise figure of 5.44---14.72 dB. The core circuits draw a current of 78.35 mA from a 1.8-V power supply and the chip occupies 6.46-mm2 die area.

Design and Implementation of 2by3 Prescalerusing Different Logic in CMOS 45nm Technology

Frequency division is one of the important applications of flip-flops. A wide-band frequency synthesizer implemented by phase-locked loop (PLL) uses prescaler (also called N/N+1 counter) as fundamental block. In PLL high frequency output of VCO is coupled directly to the prescaler directly. As process technology is reducing, channel length and supply voltage is decreasing rapidly. Therefore prescaler has to work at high frequency as well as low operating voltage. Using pass transistor or CMOS Technology are the incorporation of additional logic gates between the flip-flops to achieve the two different division ratios, the speed of the prescaler is affected by creating another propagation delay and the increases the switching power.

DDS를 이용한 광대역 고속 주파수 합성기

Abstract In this paper, a 613 GHz ultra high speed frequency synthesizer having minimum 30 kHz step size and minimum 500 ns frequency settling time is proposed. In order to obtain fast settling time, fine resolution, and good phase noise performance, wideband output frequencies were synthesized based on DDS(Direct Digital Synthesizer) and analog direct frequency synthesis technology. The phase noise performance of wideband frequency synthesizer was estimated by the superposition theory and its results were compared with mea-sured ones. The measured frequency settling time was below 500 ns, phase noise was below 106 dBc @ 10 kHz at 13 GHz, and frequency accuracy was measured below ±2 kHz. Key words: Wideband Synthesizer, High Speed, Fine Resolution, DDS OPQRS(Agency for Defense Development) *TU QGVWQ(Department of Radio Science & Engineering, Chungnam National University)Manuscript received August 29, 2014 ; Revised September 29, 2014 ; Accepted November 7, 2014. (ID No. 20140829-066)Corresponding Author: Dong-Chul Park (e-mail: dcpark@cnu.ac.kr)

A multi-band CMOS PLL-based frequency synthesizer for DRM/DRM+/DAB systems

A wideband frequency synthesizer is designed and fabricated in a 0.18 μm CMOS technology. It is developed for DRM/DRM+/DAB systems and is based on a programmable integer-N phase-locked loop. Instead of using several synthesizers for different bands, only one synthesizer is used, which has three separated divider paths to provide quadrature 8-phase LO signals. A wideband VCO covers a frequency band from 2.0 to 2.9 GHz, generates LO signals from 32 to 72 MHz, and from 250 to 362 MHz. In cooperation with a programmable XTAL multi-divider at the PLL input and output dividers at the PLL output, the frequency step can be altered from 1 to 25 kHz. It provides an average output phase noise of ?80 dBc/Hz at 10 kHz offset, ?95 dBc/Hz at 100 kHz offset, and ?120 dBc/Hz at 1 MHz offset for all the supported channels. The output power of the LO signals is tunable from 0 dBm to +3 dBm, and the phase of quadrature signals can also be adjusted through a varactor in the output buffer. The power consumption of the frequency synthesizer is 45 mW from a 1.8 V supply.

A low-complexity low-spurs digital architecture for wideband PLL applications

This paper presents a non-ideality analysis of the wideband frequency synthesizer, and proposes a new digital architecture for signal modulation and quantization. Using error masking strategy, this method can offer smaller routing area and less power consumption without sacrificing any system performance. Simulation results confirm the theoretical predictions. Finally, the design guidelines are derived to fulfill the customized synthesizer specifications.

A time-to-digital converter based AFC for wideband frequency synthesizer

The automatic frequency calibration (AFC) technique is routinely used in wideband frequency synthesizers that contain multiple voltage-controlled oscillator (VCO) tuning curves. In this paper, a counter-based AFC that uses a time-to-digital converter (TDC) in the counting process is developed. The TDC is able to capture the fractional VCO cycle information within the counting window. This significantly improves the frequency detection accuracy over the existing counter-based AFC techniques. In addition, a quantitative model is developed to determine the minimally required error-free AFC calibration time for a given VCO tuning curve characteristic. An AFC circuit using the proposed TDC-based counter is designed in a 0.13-μm CMOS technology. Simulation results show that the proposed AFC significantly improves the frequency detection accuracy and consequently for a given frequency detection resolution reduces the AFC calibration time. The simulated error-free AFC time is <2.5 μs with a frequency resolution of 0.04 %.

YTO를 이용한 광대역 저 위상 잡음 주파수 합성기 설계 및 제작

The low phase noise and wideband frequency synthesizer has been designed by using YTO. Offset PLL structure is used for reducing a division ratio of feedback loop. The phase noise modeling is applied to optimize loop filter of PLL and YTO module. And DDS is used as reference signal of frequency synthesizer for fine resolution. The fabricated wideband frequency synthesizer has the output frequency of 3.2 GHz to 6.8 GHz, phase noise of -107 dBc/Hz at 10 kHz offset from the carrier and frequency resolution of 1 Hz. The measured phase noise is well agreed with the simulated one.

A Wideband Frequency Synthesizer with High Frequency Resolution

ABSTRACTThis article presents the design and implementation of a wideband frequency synthesizer which uses a direct digital synthesis as a fractional divider in the phase‐locked loop. The frequency resolution is 7.1 × 10−5 Hz. A phase‐domain model of this synthesizer is analyzed and simulated. A formula of output phase noise is derived. The output phase noise of synthesizer is −124 dBc/Hz (10 kHz offset) at the frequency of 1 GHz. The frequency synthesizer model has been designed with advantages of wide bandwidth, low phase noise, high‐frequency resolution, low spurious, high frequency stability, and simple structure. With frequency multiplier and divider module, the frequency band of synthesizer can be extended from 250 MHz to 8 GHz. The module is suitable for communication instrument. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2454–2457, 2013

Enhancement of Frequency Synthesizer Operating Range Using a Novel Frequency-Offset Technique for LTE-A and CR Applications

This paper presents a novel frequency-offset technique to enhance operating range of frequency synthesizers for long-term evolution-advanced and cognitive-radio applications. Conventional wideband frequency synthesizers typically have complex architectures, such as multiple phase-locked loops (PLLs), multiple voltage-controlled oscillators, and multiple mixers, to increase operating range. These complex architectures have high cost and power consumption. In this study, the proposed technique substantially increases the operating range of the frequency synthesizer by using only a single PLL to simultaneously lock two mixing oscillators. The presented frequency synthesizer is implemented using <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\hbox {0.18-}}\mu{\hbox {m}}$</tex></formula> CMOS technology. Performance tests demonstrate that the frequency synthesizer achieves a very wide operating frequency range from 50 MHz to 4.8 GHz with a phase noise lower than <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$-{{\hbox {100 dBc/Hz}}}$</tex></formula> at a frequency offset of 100 kHz. The period of stability for a switching frequency of 40 MHz is shorter than <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\hbox {40}}~\mu{\hbox {s}}$</tex></formula> .

A 0.4–6-GHz Frequency Synthesizer Using Dual-Mode VCO for Software-Defined Radio

This paper presents a dual-mode voltage-controlled oscillator (DMVCO) and a DMVCO-based wideband frequency synthesizer for software-defined radio applications. The DMVCO allows the synthesizer to leverage single-sideband (SSB) mixing, a power efficient approach, for high-frequency local oscillator (LO) signal generation, without the need of poly-phase filter or quadrature voltage-controlled oscillator (QVCO). When compared to the QVCO approach, the DMVCO solution allows the synthesizer to provide continuous LO signals without frequency gaps. The synthesizer is implemented in a 0.13-μm CMOS technology, occupying an active area of 2.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consuming 34-77 mW of power. It provides in-phase and quadrature-phase LO signals over the frequency bands of 0.4-3- and 5-6 GHz and differential LO signals from 0.4 to 6 GHz, supporting major wireless standards including DVB-T, GSM, WCDMA, TD-SCDMA, WLAN802.11 a/b/g, and Bluetooth. The measured phase noises are -135 and -124 dBc/Hz at 3-MHz offset under 1.8- and 5.15-GHz carriers, respectively. The measured spurious tones are less than - 42 dBc at the SSB mixer output.

A wideband frequency synthesizer with VCO and AFC co-design for fast calibration

A wideband fractional-N frequency synthesizer is implemented in a 65 nm CMOS process. It employs a wideband LC voltage-controlled oscillator (VCO) with optimized VCO gain (KVCO) and a sub-band step to improve automatic frequency calibration (AFC) efficiency at negligible expense of phase noise performance. An agile AFC is realized by direct mapping based on the division ratio, and optional redundant counting and comparing calibration is introduced accommodating PVT variations, which samples the reference clock using the prescaled VCO output as a discriminating clock. A charge pump with switched charging current is adopted to compensate for the loop bandwidth variation. Measurement results show this directly-mapped AFC locates the target sub-band in 100 ns and only needs 1.2 μs for redundant calibration. The frequency synthesizer spans a frequency range from 0.62 to 1.52 GHz, with phase noise of −86 dBc/Hz at 10 kHz offset and −122 dBc/Hz at 1 MHz offset while consuming 9.76 mA from a 1.2 V supply.

A High-Linearity WCDMA/GSM Reconfigurable Transceiver in 0.13-$\mu\hbox{m}$ CMOS

This paper presents a dual-mode multiband transceiver with DigRF interface implemented in a 0.13-μm CMOS technology. Based on direct conversion architecture, blocks in the transceiver can be configured to simultaneously support wavelength code-division multiple access (WCDMA) band I and four Global System for Mobile Communications (GSM) bands (PCS/DCS/GSM900/GSM850). In the receiver path, the narrowband radio-frequency front-end is comprised of multiple-gated low-noise amplifiers with capacitive desensitization and current-mode passive mixers with the proposed second-order input intercept point (IIP2) calibration to comply for surface-acoustic-wave-less application. In the transmitter path, a high-linearity mixer and parallel Class-AB PA driver are adopted. Low-noise wideband frequency synthesizers with adaptive frequency calibration are proposed to cover all modes and bands. This reconfigurable transceiver achieves -5.6/-2/-6 dBm in-band third-order intercept point for WCDMA/GSM HB/GSM LB respectively, and >;65 dBm IIP2. At the maximum output power, the transmitter achieves 2.3% rms error vector magnitude for WCDMA I and 1.67° phase error for a GSM system.