Wide Input Dynamic Range Research Articles

위상 검출 방식 레이저 스캐너의 APD bias 전압 특성을 이용한 검출신호세기 제어 방법

In the phase-shift measurement method, the distance light travels can be obtained based on the phase difference between the reference signal and the measured signal. When the object having various colors is measured, the intensity of the measured signal much varies even at the same distance, and it causes different phase delay due to wide dynamic range input to a signal processing circuit. In this work, an measured intensity control method is proposed to solve this phase delay problem.

Wide Dynamic Range CMOS Pseudo-differential Current Conveyors: CMOS Realizations and Applications

This paper presents two new CMOS realization circuits of the pseudo-differential current conveyor (PDCC) in which the second realization is a modified version of the first one. The modified PDCC has a wide dynamic input and output ranges with low distortion. The PDCC CMOS circuits are formed from two stages, input stage and output stage, and operating under a supply voltage of ±1.5 V. The input stage of the PDCC is realized using two wide linear range transconductors, and the output stage consists of a class AB push-pull network, which guarantees high current driving capability and low standby current. The first realization of PDCC exhibits dynamic input range of ±1.4 V with a total standby power dissipation of 4.08 mW, while the second realization of the PDCC exhibits a wide dynamic input range of ±2.1 V with a total standby power dissipation of 3.68 mW. The PDCC is used to realize mixed-mode fully differential VGA and a differential-mode bandpass filter. PSPICE simulations of the proposed PDCC and its based applications are given using 0.25-μm CMOS technology from TMSC MOSIS.

ALC Burst-Mode Optical Fiber Amplifiers for 10 Gb/s-Class Long-Reach PONs

This paper proposes a burst-mode optical fiber amplifier (OFA) that consists of a combination of an automatic gain controlled praseodymium-doped fiber amplifier (AGC-PDFA), a fast automatic level controlled circuit (ALC), and a PDFA with just forward pumping. The second PDFA is used as a booster to achieve high gain, over 20 dB. The combination of AGC and ALC techniques suppresses optical surge generation against strong burst signal inputs and also prevents overloading of the burst-mode receivers; it provides OFA-based passive optical network (PON) repeaters with wide input dynamic range and solves the near–far problem in upstream transmission in long-reach PONs. We experimentally compare the operating range of the proposed burst-mode PDFA with that of a conventional burst-mode PDFA. Experiments show that the proposed PDFA achieves a much wider operating area than a conventional PDFA; a wide dynamic range in an access span of 17.5 dB, which is equivalent to the input dynamic range of the burst-mode receiver used in 10 gigabit Ethernet PON (10G-EPON), is obtained with an allowable loss margin of 14 dB in a trunk span. A maximum link budget of 55 dB is achievable.

Low cost front-end readout electronic for instrumentation used in neutron experiments

In the field of material characterization, the neutron scattering technique is found to be useful in so many applications. This technique requires a position sensitive neutron detector (PSND) and their front-end readouts (FER) electronic to detect the position of neutron interactions. Normally, the PSND is designed for specific applications and has unique technical specifications. Therefore, it requires a customised electronic FER to match its specifications. Furthermore, a large active area requires a large number of FER electronic and, therefore, there is, also, an increased development cost. This paper presents a simple and low-cost design for FER electronic which consists of an eight channels preamplifier-shaper suitable for instrumentation used in neutron experiments. This FER was built entirely with low-noise FET-input operational amplifier (Op-amp) and passive components. The development cost is around U.S. $50/channel. Results have shown that it is capable of accepting a wide dynamic range input charge (20 to 600 fC) with an excellent output linearity (nonlinearity < 1%). It has a good equivalent noise charge (ENC) with a performance average of 2113e- and is less sensitive to input capacitance variation (24e-/pF). Key words: Low-cost, front-end readout, preamplifier, shaper, neutron experiments.

A New Two-Quadrant Squarer/Divider Circuit for true RMS-to-DC converters in MOS technology

In this paper, a new log-domain two-quadrant squarer/divider circuit for current mode RMS-to-DC converters is presented. The proposed circuit has been realized using MOSFET transistors that are operating in weak inverted saturation region. It features very low supply voltage (1V), low power consumption (<3μW), two-quadrant input current, wide input dynamic range, immune from body effect and low circuit complexity. Simulation results by HSPICE show high performance of the circuit and confirm the validity of the proposed design technique.

Note: Intensity control of a phase-shift based laser scanner for reducing distance errors caused by varying surface reflectivity

In the phase-shift measurement method, the distance traveled by light can be obtained on the basis of the phase difference between the reference signal and the measured signal. When a different colored object is measured, the intensity of the measured signal varies greatly, even at the same distance, which causes a different phase delay owing to the wide dynamic range input into the signal processing circuit. In this study, an intensity control method is proposed to solve this phase delay problem.

Design and characterization of CMOS multichannel front-end electronics for silicon photomultipliers

Abstract CMOS multichannel front-end electronics suitable for Silicon Photomultiplier detectors has been developed, mainly intended for medical imaging applications. The architecture of the analog channel, DC coupled to the detector, is based on a full current-mode approach, which allows to achieve a wide input dynamic range of about 70 pC while retaining very fast self-triggering capabilities. An 8-channel ASIC with on-chip ADC and a 32-channel prototype have been designed and manufactured, both featuring serial and sparse readout capabilities and a fast-OR circuit, able to generate a high-speed trigger signal from the discriminator outputs of the analog channels. Measurements obtained by coupling the 8-channel prototypes to an injection capacitance have been carried out for characterization purposes. The circuit has been also used to read-out SiPMs coupled to different kinds of light sources, such as a blue LED and a small LYSO scintillation crystal excited by gamma photons with different energies. The results obtained from these tests are presented and discussed, confirming the effectiveness of the proposed front-end architecture.

A Single-Chip 2.5-Gb/s CMOS Burst-Mode Optical Receiver

This paper describes the design of a 2.5-Gb/s burst-mode optical receiver in a 0.18-mum CMOS process. A dual-gain-mode transimpedance amplifier (TIA) with constant damping factor control is proposed to tolerate a wide dynamic range input signal. By incorporating an automatic threshold tracking circuit (ATC), the TIA and limiting amplifier (LA) are dc coupled with feedforward offset cancellation. Dual-band filters are adopted in the ATC for a rapid response time while keeping the tracking error small. By integrating both a TIA and a post-LA in a single chip, the burst-mode receiver provides a conversion gain of 106 dBmiddotOmega in the high gain mode, 97 dBmiddotOmega in the low gain mode, and a -3-dB bandwidth of 1.85 GHz. The measured input sensitivity, overload level, and dynamic range of the optical receiver are -19 dBm, -2 dBm, and 17 dB, respectively. The response time is less than 50 ns. Operating under a single 1.8-V supply, this chip dissipates only 122 mW.

New CMOS DVCC realization and applications to instrumentation amplifier and active-RC filters

This paper presents a novel CMOS differential voltage current conveyor (DVCC) based on a wide linear range transconductor with common mode detection. The DVCC exhibits a wide dynamic input range of ± 0.9 V . It is used to realize an instrumentation amplifier, a multiple input single output filter, and a single input multiple output universal filter. PSPICE simulations of the proposed DVCC and its based applications are given using 0.25 μ m CMOS technology from TMSC MOSIS and dual supply voltages ± 1.5 V .

A 1.2 V current-mode true RMS–DC converter based on the floating gate MOS translinear principle

A current-mode true RMS–DC converter based on a novel synthesis of translinear loop squarer/divider and simplified current-mode low-pass filter is presented. The circuit employs floating gate MOSFETs that operate in strong inverted saturation region for electronically simulated translinear loop. The converter features very low supply voltage (1.2V), two-quadrant input current, immunity from body effect, low circuit complexity, and wide input dynamic range. Simulation results by HSPICE show high performance of the circuit and confirm the validity of the proposed design technique.

Highly sensitive wide-dynamic range optical burst-mode receivers for ultra fast gain switching

Highly sensitive optical receivers in BiCMOS, sub-micron and deep-sub-micron CMOS technology are compared. Special attention is paid to burst-mode receivers with a wide-dynamic input range and with fast gain switching. A new burst-mode receiver design in 0.12?m CMOS technology for a data rate of 2.5 Gb/s and very fast gain switching is presented. Handling a wide dynamic range leads to stability problems when the transimpedance gain of the preamplifier is decreased. These stability problems could be solved by decreasing the open-loop gain of the transimpedance amplifier. Stability analysis of this solution is presented here.

ATSC DTV Receiver Implementation

Receivers of broadcast digital television (DTV) service operate in an often difficult environment of electrical interference, multiple other TV signals in close frequency proximity, multipath, wide dynamic range input signals, and uncertain antenna choice and installation. Receivers must demodulate and decode the signal and optimize its processing for different display technologies-a process that can include format conversion between progressive and interlaced scanning and different screen pixel counts. Data that supports the new services enabled by digital transmission must be decoded and processed. Receiver designers must implement the required functions cost-effectively even as they strive to provide performance and feature differentiation from their competitors' products. This paper describes all of the DTV receiver functions and references the associated standards. Emphasis is given to the difficult areas of signal reception and demodulation and to sections of the receiver that enable attractive and recognizable consumer features.

New Four-Quadrant CMOS Current-Mode and Voltage-Mode Multipliers

In this paper, a four-quadrant current-mode multiplier based on a new squarer cell is proposed. The multiplier has a simple core, wide input current range with low power consumption, and it can easily be converted to a voltage-mode by using a balanced output transconductor (BOTA) [1]. The proposed four-quadrant current-mode and voltage-mode multipliers were confirmed by using PSPICE simulation and found to have good linearity with wide input dynamic range. For the proposed current-mode multiplier, the static power consumption is 0.671 mW, the maximum power consumption is 0.72 mW, the input current range is ±60 µA, the bandwidth is 31 MHz, the input referred noise current is 46 pA/√Hz, and the maximum linearity error is 3.9%. For the proposed voltage-mode multiplier, the static power consumption is 1.6 mW, the maximum power consumption is 1.85 mW, the input voltage range is ±1V from ±1.5V supply, the bandwidth is 25.34 MHz, the input referred noise voltage is 0.85 µV/√Hz, and the maximum linearity error is 4.1%.

Output-level control of semiconductor optical amplifier by external light injection

A method of controlling the output level of semiconductor optical amplifiers (SOAs) that accepts a wide range of input power and delivers constant output power was experimentally studied. It is demonstrated that external light injection into SOAs could change the signal gain by varying the depth of gain saturation while retaining their saturation output power. This feature is very important in SOAs when amplifying signals modulated in the gigabit-per-second (Gb/s) range because the average output level of SOAs must be limited to a value several decibels lower than the saturation output power to prevent signal distortions due to the pattern effect. For signals modulated at 10 Gb/s in the nonreturn-to-zero (NRZ) format, the upper limit for allowable signal input power increased by > 13.5 dB, while retaining good eye patterns in a signal-wavelength range between 1530 and 1560 nm. Consequently, output-level control with a constant output power of +10 dBm was demonstrated for a wide input dynamic range of 13.5 dB in the signal-wavelength range. This method of controlling the output level of SOAs is promising for equalizing the signal power in future photonic network systems because the short carrier lifetime of SOAs can provide extremely fast gain control.

A Programmable CMOS Fuzzy Membership Function Generator

This paper presents the architecture and circuit-level details related to hardware implementation of a programmable analog Membership Function Circuit (MFC). Its new architecture and modular approach makes it flexible and easy to expand. The proposed circuit has a wide dynamic input range (3.5 V) and can be modified in a way that the output of the circuit may be in single-ended or differential mode. In addition width, height, position and slope of generated membership functions are easily tunable. Brief tutorials of the circuits introduced by other papers are presented here for comparison. Simulation results are also given using HSPICE software in 0.5μm CMOS technology.

High-gain SiGe transimpedance amplifier array for a 12×10 Gb/s parallel optical-fiber link

A transimpedance amplifier array for 12 parallel optical-fiber channels each operating at 10 Gb/s is presented, which is used in the receiver of short-distance links. It stands out for the following features: high gain (transimpedance 25 k/spl Omega/ in the limiting mode), high input sensitivity and wide input dynamic range (input current swing from 20 to 240 μA/sub p-p/), constant output voltage swing (differential 0.5 V/sub p-p/ at 50 /spl Omega/ load), and low power consumption (1.4 W) at a single supply voltage (5 V). Each channel has its own offset-current control circuit. To the best of the authors' knowledge, the total throughput of 12×10 Gb/s=120 Gb/s is the highest value reported for a single-chip amplifier array. The target specifications have been achieved with the first technological run without needing any redesign. This fact demonstrates that the inherent severe crosstalk problems of such high-gain amplifier arrays can reliably be solved by applying adequate decoupling measures and simulation tools.

A 0.9-V 0.5-μA rail-to-rail CMOS operational amplifier

A 0.9 V, 0.5 /spl mu/A, rail-to-rail CMOS operational amplifier designed with weak inversion techniques is presented. Depletion-mode NMOS transistors buffer a bulk-driven PMOS differential pair to realize wide input dynamic range, while the output stage architecture provides symmetric rail-to-rail output drive through the use of a low voltage translinear control circuit.

An auto-gain control transimpedance amplifier with low noise and wide input dynamic range for 10-Gb/s optical communication systems

This paper describes a 10-Gb/s transimpedance amplifier (TIA), fabricated in a 0.1-/spl mu/m-p-HEMT technology. To improve the optical overload characteristics, an automatic gain control (AGC) circuit is included. The measured results show excellent performance, transimpedance of 63.3 dB/spl Omega/ (1.46 k/spl Omega/), bandwidth of 8.0 GHz, and equivalent input noise current density of 6.5 pA/rtHz. When the bit error rate is 10/sup -9/, the minimum sensitivity and the optical overload are -21.2 dBm, +4.3 dBm, respectively, using a 0.8 A/W pin photodiode (PD). The power dissipation is about 0.5 W from a single -5-V supply. The die area is 1.3/spl times/1.6 mm/sup 2/.

A novel compensating light injection configuration for gain-clamped EDFA's

A novel compensating light injection configuration for gain-clamped erbium-doped fiber amplifier (EDFA's) is proposed. The compensating light is backward injected from the end of the first stage of the amplifier and then reflected by a grating at the amplifier input end. Very wide input dynamic range (0.5 /spl mu/W-500 /spl mu/W) with less than 1 mW of compensating light and low noise penalty (<0.5 dB) is demonstrated.

A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBT limiting amplifier

A limiting amplifier IC implemented in a silicon-germanium (SiGe) heterojunction bipolar transistor technology for low-cost 10-Gb/s applications is described. The IC employs 20 dB gain limiting cells, input overload protection, split analog-digital grounds, and on-chip isolation interface with transmission lines. A gain enhancement technique has been developed for a parallel-feedback limiting cell. The limiting amplifier sensitivity is less than 3.5 mV/sub pp/ at BER=10/sup -9/ with 2-V/sub pp/ maximum input (55-dB dynamic range). The total gain is over 60 dB, and S/sub 21/ bandwidth exceeds 15 GHz at 10-mV/sub pp/ input. Parameters S/sub 11/ and S/sub 22/ are better than -10 dB in the 10-GHz frequency range. The AM to PM conversion is less than 5 ps across input dynamic range. The output differential voltage can be set from 0.2 to 2 V/sub pp/ with IC power dissipation from 250 mW to 1.1 W. The chip area is 1.2/spl times/2.6 mm/sup 2/. A 10-Gb/s optical receiver, built with the packaged limiting amplifier, demonstrated -19.6-dBm sensitivity. The IC can be used in 10-Gb/s fiber-optic receivers requiring high sensitivity and wide input dynamic range.