Using ultraviolet (UV) annealing through wide energy bandgap HfO2/SiO2 gate dielectric, nanosheet SnO pFET achieved hole effective mobility (µeff) from 55 cm2/V-s at low hole density (Qh) to 13.38 cm2/V-s at 5 × 1012 cm-2 Qh, compared to that of 9.03 cm2/V-s at 5 × 1012 cm-2 Qh for SnO device without UV annealing. This is the highest µeff among oxide semiconductor pFETs at high Qh, which is required to realize low-power high-density monolithic 3D CMOS logic. This requires excellent surface roughness, good uniformity and free-from grain boundaries that is beyond the thermally-annealed poly-Si. Excellent on-current/off-current (ION/IOFF) value of 1.05 × 105 were measured simultaneously in the UV-annealed SnO pFET, which is due to the ultra-thin 8 nm thick SnO nanosheet channel to pinch off the channel leakage. From X-ray photoelectron spectroscopy (XPS) analysis, the 48% µeff improvement by UV irradiation is due to increased Sn2+ and decreased Sn0. Such high µeff at high Qh, large ION/IOFF, smooth surface, good uniformity and low thermal budget process are the enabling technologies for monolithic 3D CMOS.
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