Gallium Arsenide (GaAs) technology has shown a rapid increase in maturity over the past few years. The fast logic gate switching speeds of GaAs integrated circuits make them very attractive for high performance digital systems. However, low yield and large off-chip propagation delays reduce the ease by which fast GaAs circuits can be fully exploited. In this paper, wafer scale integration (WSI) concept is examined. WSI technique could be used to combat the problems associated with GaAs circuits. To achieve this goal a wholistic approach is needed, i.e. characteristic properties of technology, architecture, algorithms/arithmetic must all be taken into account. As an example, a systolic array WSI implementation is presented.