Wavefront Parallel Research Articles

Efficient VVC Encoding Using Hierarchical Parallelization: A Comprehensive Analysis

This paper presents and analyzes different parallelization strategies in VVenC, an open and optimized software encoder implementation of the Versatile Video Coding (VVC) standard. VVC has been developed to address the increasing demand for higher compression of digital video data, and it reduces the bitrate by around 50% for the same perceived quality compared to its predecessor, the High-Efficiency Video Coding (HEVC) standard. However, this increase in compression efficiency comes with an increase in computational complexity, particularly on the encoder side. VVenC integrates algorithmic optimizations for each coding tool in VVC and defines a set of five presets from faster to slower that provide Pareto-optimal tradeoffs between runtime and efficiency. Multithreading is employed to further reduce runtime while preserving most of the compression efficiency of each preset. With a hierarchical combination of pre-processing, picture-level and in-picture parallelization, VVenC achieves a 4× speedup for four threads. Further speedup using a higher number of threads depends on the video resolution and used encoder preset. For 16 threads, it ranges from 6 to 9 for high definition to 10-12 for ultra-high-definition video. Compared to previous work, the usage of temporal prediction for the adaptive loop filter reduces the associated coding efficiency loss from 0.4% to almost zero. A better scaling for higher numbers of threads can be achieved at the cost of a higher coding efficiency loss. In the presented framework, increased speedup by smaller block Coding Tree Unit (CTU) sizes, a combination of wavefront parallel processing and various tiles picture partitioning configurations is examined. Furthermore, results on a 20-core ARM-based Apple M1 computer indicate a better scaling for multithreading compared to × 86-based architectures. The analysis is complemented by profiling, which exhibits the overhead by idle threads and identifies the mode estimation as the main bottleneck of the presented framework.

Lensless Wavefront Parallel Processing of Vector Beams by Self‐Images of a Self‐Organized Q‐Plates Microarray

Wavefront shaping of structured light beams is attracting considerable attention in optics and related technologies. Due to the potential benefits, it is crucial to develop versatile methods for controlling the wavefront in a compact space with the capacity for high‐throughput parallel processing. Herein, a unique concept is introduced for converting the wavefront of multiple structured light beams, which are periodically packed in a microscopic area. An experimental demonstration is provided by using transmissive planar optical elements consisting of a microarray of geometric phase based on nematic liquid crystals. The periodic microstructure is fabricated by the directed self‐organization of topological defects present in a nanoscale relief obtained by area‐selective surface modification. The conversion of multiple wavefronts is realized by using the Talbot self‐imaging effect of the microarray. The integrated geometric phase microarray has potential applications in vortex beam emitters to harness structured light, such as for optical manipulation and lithography.

Construction of Dynamic Multiparallel Foreign Language Teaching Model Based on Multicore Processor

Heterogeneous multicore processor systems, as one of the highlights of multicore processor systems, are widely loved by people for their high efficiency and low cost, and they have also become the most commonly used processor systems in embedded systems. In the process of research on heterogeneous multicore processor systems, system task scheduling is particularly important. A good task scheduling algorithm can give full play to system performance. In this paper, the intelligent approximation algorithm is applied to the task scheduling problem of heterogeneous multicore processor system, and the heterogeneous multicore processor system is obtained as a highlight in the multicore processor system. Relying on the characteristics of high efficiency and low cost, it is widely loved by people, and at the same time, it has become the most commonly used processor system in embedded systems. In the process of research on heterogeneous multicore processor systems, the system task scheduling problem is particularly important. A good task scheduling algorithm can give full play to system performance. Some commonly used heuristic task scheduling algorithms are insufficient in solving such problems. This paper combines the granularity-based wavefront parallel decoding algorithm and the fast fusion loop filter algorithm to apply pipeline parallel technology between pixels. Decoding reconstruction module and fast loop filter module realize the fusion of multilevel parallel decoding. Based on the multicore platform, a dynamic multiparallel scheduling algorithm is designed to realize two-way video real-time parallel high-speed decoding, which improves the core resource utilization rate and decoding execution efficiency of the multicore processing platform. This paper also designs an indicator collector, a read-write hit collector, and a cache block priority determiner to implement a dynamic generation strategy with low hardware overhead. Multimodal teaching has certain feasibility and effectiveness and can have a positive impact on the English reading motivation and English reading comprehension ability of university students. Multimodal teaching improves students’ English reading comprehension ability, deepens students’ understanding and memory of words, and broadens the scope of knowledge, which has a significant promoting effect. The research results show that multimodality can be applied to college English teaching, and it can achieve better results than traditional teaching methods. By comparing the test results before and after the test, there are obvious differences between the experimental class and the control class. Whether it is the paired sample T-test of the experimental class or the independent sample T-test of two teaching methods in two classes, it proves that the scores under the multimodal English teaching mode are higher than the traditional teaching mode. Multimodal classrooms provide students with many opportunities to participate in classroom activities and form a competitive learning atmosphere. This competitive learning atmosphere has become a driving force to promote student learning. Multimodal teaching methods help to cultivate students’ independent and cooperative learning. In a multimodal classroom, many activities require cooperation and discussion among students. When they encounter difficulties, they can help each other, discuss with each other, and cooperate to complete tasks. Therefore, the multimodal teaching method will stimulate students’ interest in learning, give full play to students’ initiative, and improve students’ English ability.

High-efficiency parallelism solution for a Multiview High-Efficiency Video Coding decoder

Thus far, Multiview High-Efficiency Video Coding (MV-HEVC) can only use a central processing unit (CPU) to perform decompression on a personal computer (PC) or workstation. Because MV-HEVC is much more complex than High-Efficiency Video Coding (HEVC), decompressors need higher parallelism to decompress in real time. Therefore, this study presents a parallel method based on MV-HEVC. Inter-view complete parallelism is realized according to the dependent relationship between other MV-HEVC views, and a search range is not required to avoid the data dependence between frames. Based on the dependencies of each task in MV-HEVC, an advanced wavefront parallel processing method is proposed to achieve higher intra-frame parallelism. The parallel structure of the proposed method is compatible with that of the single-instruction multiple-data acceleration method. The results showed that the proposed method can decompress MV-HEVC with 20 threads in real time for 1088p video with three views.

Memory-Optimized Wavefront Parallelism on GPUs

Wavefront parallelism is a well-known technique for exploiting the concurrency of applications that execute nested loops with uniform data dependencies. Recent research of such applications, which range from sequence alignment tools to partial differential equation solvers, has used GPUs to benefit from the massively parallel computing resources. To achieve optimal performance, tiling has been introduced as a popular solution to achieve a balanced workload. However, the use of hyperplane tiles increases the cost of synchronization and leads to poor data locality. In this paper, we present a highly optimized implementation of the wavefront parallelism technique that harnesses the GPU architecture. A balanced workload and maximum resource utilization are achieved with an extremely low synchronization overhead. We design the kernel configuration to significantly reduce the minimum number of synchronizations required and also introduce an inter-block lock to minimize the overhead of each synchronization. In addition, shared memory is used in place of the L1 cache. The well-tailored mapping of the operations to the shared memory improves both spatial and temporal locality. We evaluate the performance of our proposed technique for four different applications: sequence alignment, edit distance, summed-area table, and 2D-SOR. The performance results demonstrate that our method achieves speedups of up to six times compared to the previous best-known hyperplane tiling-based GPU implementation.

Scalable Wavefront Parallel Streaming Deblocking Filter Hardware for HEVC Decoder

The proposed work aims to design a Wavefront Parallel Processing (WPP) based streaming Deblocking Filter (DBF) architecture for High-Efficiency Video Coding (HEVC). This architecture supports scalable pipeline stages such as 1, 2, 4 and 8 with Coding Unit (CU) sizes, i.e., $8\times 8$ , $16\times 16$ , $32\times 32$ and $64\times 64$ Largest Coding Unit (LCU) processing respectively. Based on the requirements of speed and area of a consumer electronic application, one of the aforementioned sizes of CU or LCU is selected. The hardware uses an intelligent Memory Organization (MO) based on WPP technique with restructured CUs/LCU size without having any neighboring block dependencies. The proposed designs are implemented on an Application-Specific Integrated Circuit (ASIC) using 180-nm technology and Field Programmable Gate Array (FPGA). Experimental results show that the $32\times 32$ and $64\times 64$ block processing hardware decreases the processing cycles (128, 96) with the gate count of 286.47K and 744.13K respectively. Similarly, CUs $8\times 8$ , $16\times 16$ consume 512 and 176 processing clock cycles with an equivalent gate count of 90.72K and 194.97K respectively. The performance of proposed hardware compared with the previous works in terms of area and speed. The results show that the proposed hardware can process 4K Ultra High Definition (UHD) video frames at the rate of 50 fps at 300 MHz.

Flextended Tiles

Loop tiling to exploit data locality and parallelism plays an essential role in a variety of general-purpose and domain-specific compilers. Affine transformations in polyhedral frameworks implement classical forms of rectangular and parallelogram tiling, but these lead to pipelined start with rather inefficient wavefront parallelism. Multiple extensions to polyhedral compilers evaluated sophisticated shapes such as trapezoid or diamond tiles, enabling concurrent start along the axes of the iteration space; yet these resort to custom schedulers and code generators insufficiently integrated within the general framework. One of these modified shapes referred to as overlapped tiling also lacks a unifying framework to reason about its composition with affine transformations; this prevents its application in general-purpose loop-nest optimizers and the fair comparison with other techniques. We revisit overlapped tiling, recasting it as an affine transformation on schedule trees composable with any affine scheduling algorithm. We demonstrate how to derive tighter tile shapes with less redundant computations. Our method models the traditional “scalene trapezoid” shapes and novel “right-rectangle” variants. It goes beyond the state of the art by avoiding the restriction to a domain-specific language or introducing post-pass rescheduling and custom code generation. We conduct experiments on the PolyMage benchmarks and iterated stencils, validating the effectiveness and applicability of our technique on both general-purpose multicores and GPU accelerators.

A Multi-Grained Parallel Solution for HEVC Encoding on Heterogeneous Platforms

To improve the parallel processing capability of video coding, the emerging high efficiency video coding (HEVC) standard introduces two parallel techniques, i.e., Wavefront Parallel Processing (WPP) and Tiles , to make it much more parallel-friendly than its predecessors. However, these two techniques are designed to explore coarse-grained parallelism in HEVC encoding on multicore Central Processing Unit (CPU) platforms. As the computing architecture undergoes a trend toward heterogeneity in the last decade, multi-grained parallel computing methods can be designed to accelerate HEVC encoding on heterogeneous systems. In this paper, a multi-grained parallel solution (MPS) is proposed to optimize HEVC encoding on a typical heterogeneous platform. A massively parallel motion estimation algorithm is employed by MPS to parallelize part of HEVC encoding on Graphic Processing Unit (GPU). Meanwhile, several other HEVC encoding modules are accelerated on CPU through the cooperation of WPP and an adaptive parallel mode decision algorithm. The parallelism between CPU and GPU is well designed and implemented to guarantee an efficient concurrent execution of HEVC encoding on multi-grained parallel levels. The effectiveness of the proposed MPS for HEVC encoding is verified on a number of experiments.

Variations of acoustic noise intensity accompanying internal wave solitons

In this paper, acoustical noise intensity fluctuations recorded by single hydrophones (SHRUs) in the Shallow Water 2006 experiment are studied. The area of experiment (New Jersey Atlantic shelf) is characterized by a remarkable activity of internal waves, in particular, approximately twice per day trains of nonlinear internal waves (NIW) consisting of up to ten separate peaks with the amplitudes about 10–15 m and wave front parallel to the coastal line move toward the beach. During its motion trains of NIW cross positions of five SHRUs, located about 5–8 km to each other along line perpendicular to the coast as well as thermistor’s strings which allow us to estimate the shape and evolution of trains while they are propagating. It is shown that the appearance of irregular wideband sound field (amplitude by up to 20–40 dB greater than noise background) takes place when the train of NIW is passing through the location of the corresponding SHRUs. The nature of these signals is discussed, and the spectrum and specific temporal variations as well as other characteristics are analyzed. [Work was supported by ONRG, NSF, and BSF.] In this paper, acoustical noise intensity fluctuations recorded by single hydrophones (SHRUs) in the Shallow Water 2006 experiment are studied. The area of experiment (New Jersey Atlantic shelf) is characterized by a remarkable activity of internal waves, in particular, approximately twice per day trains of nonlinear internal waves (NIW) consisting of up to ten separate peaks with the amplitudes about 10–15 m and wave front parallel to the coastal line move toward the beach. During its motion trains of NIW cross positions of five SHRUs, located about 5–8 km to each other along line perpendicular to the coast as well as thermistor’s strings which allow us to estimate the shape and evolution of trains while they are propagating. It is shown that the appearance of irregular wideband sound field (amplitude by up to 20–40 dB greater than noise background) takes place when the train of NIW is passing through the location of the corresponding SHRUs. The nature of these signals is discussed, and the spectrum and...

Revisiting the Parallel Strategy for DOACROSS Loops

DOACROSS loops are significant parts in many important scientific and engineering applications, which are generally exploited pipeline/wave-front parallelism by loop transformations. However, previous work almost statically performs iterations in parallel threads, thus causing a waste of computing resources in thread synchronization. This paper proposes a brand-new parallel strategy for DOACROSS loops that provides a dynamic task assignment with reduced dependences to achieve wave-front parallelism through loop tiling. The proposed strategy uses a master-slave parallel mode and some customized structures to realize dynamic and flexible parallelization, which effectively avoids threads from waiting in communication. An efficient tile size selection (TSS) approach is also proposed to preserve data reuse in cache for tiled codes. The experimental results show that the proposed parallel strategy obtains good and stable speedups over six typical benchmarks with different problem sizes and different numbers of threads on an Intel® Xeon® 32-core server. And it outperforms two static strategies, a barrier-based strategy and a post/wait-based strategy, by 32% and 20% in average performance, respectively. This strategy also yields a better performance than a mutex-based dynamic strategy. Besides, it has been demonstrated that the proposed TSS approach can achieve a near-optimal performance and is comparable with a state-of-the-art TSS approach.

A Collaborative Scheduling-Based Parallel Solution for HEVC Encoding on Multicore Platforms

In order to meet the high computational demand to achieve superior coding efficiency and to explore the parallelism of parallel processing architectures, the emerging high efficiency video coding (HEVC) standard has been designed to be more parallelizable than previous video coding standards. However, it is still desirable to design an efficient parallel HEVC encoder to fully exploit the parallelism of the increasingly powerful multicore platforms, especially when considering the amount of parallelism, the scalability of parallelization, and the coding efficiency. In this work, a performance model of HEVC encoding is first introduced to investigate the speedup and the limitations of the technique of wavefront parallel processing (WPP) under various conditions. Then, a collaborative scheduling-based parallel solution (CSPS) for HEVC encoding is proposed, which includes adaptive parallel mode decision, asynchronous frame-level pixel interpolation, and multigrained task scheduling. The goal of the proposed CSPS is to defeat the disadvantages of WPP and further improve the parallelization of HEVC encoding on multicore platforms. Extensive experimental results demonstrate the efficiency of the proposed CSPS for parallelizing HEVC encoding as the computing resources of multicore architectures can be fully utilized.

Contents-aware partitioning algorithm for parallel high efficiency video coding

We introduce a new parallelization method for high-efficiency video coding (HEVC), which resolves the shortcomings of the existing tile-based parallel processing method. The parallel HEVC performs encoding by dividing a frame into numerous parallel units. This decreases the compression efficiency compared with sequential HEVC, because it artificially breaks the data correlation within a frame, which is called the parallelization overhead. The traditional parallel techniques such as Tiles and wavefront parallel processing (WPP) inherently introduce a high parallelization overhead because they simply divide a frame statically without considering the contents of the frame. The proposed new parallel encoding scheme resolves such problems by partitioning a frame based on the meaningful contents. In order to analyze the correlations within a frame and define the contents, the features within a frame are first extracted and clustered. In the feature clustering algorithm, two factors are considered to balance the workload between parallel units: (1) the number of features in each cluster and (2) the number of coding tree units (CTU) occupied by each cluster. The frame is partitioned based on the result of clustering, and the partitions are encoded in parallel. The proposed scheme achieves a bit-saving of up to 7.21%, with an average of 3.71%, along with an average time-saving of 20.50% compared to the Tiles technique.

Multi-level complexity reduction for HEVC multiview coding

Standardized in 2014, multiview extension of high efficiency video coding (MV-HEVC) offers significantly better compression performance of up to 50% for multiview and 3D videos compared to multiple independent single view HEVC coding. However, the extreme high computational complexity of MV-HEVC demands significant optimization of the encoder. In this work, we propose a series of optimization techniques at various levels of abstraction: non-aggregation massively parallel motion estimation (ME) and disparity estimation (DE) for prediction units, fractional and bidirectional ME/DE, quantization parameter-based early termination of coding tree unit (CTU), and optimized resource-scheduled wave front parallel processing for CTU. When evaluated over three views for all available official multiview video coding test sequences, proposed optimization outperforms the anchor encoder by average factor of 5.4 at the cost of 4.4% bitrate (DBR) increase at no loss in PSNR, or alternatively a PSNR degradation of 0.12 dB at no change to the DBR.

An efficient wavefront parallel algorithm for structured three dimensional LU-SGS

Parallel computing is a useful technology for scientific and engineering algorithms/applications. LU-SGS (lower-upper Symmetric-Gauss–Seidel method) is an efficient and robust scheme for CFD (Computational fluid dynamics) and has strong data dependence in its computation. In this paper, we present an efficient wavefront parallel algorithm for 3D (three dimensional) LU-SGS with structured meshes. The corresponding data structure and memory access method with better data locality and communication optimization is designed. The performances of the presented parallel algorithm are reported with different problem sizes. Some discussion and performance issues are also reported. The results show that the overall performance speedup of one Intel E5540 CPU (4 CPU cores) ranges from 2.23 to 2.95 compared with one E5540 core. The parallel efficiency of 1024, 128 processes are up to 35.68%, 72.69% compared with 32 processes on a distributed memory cluster system. The CFD simulation of M6 wing model shows the effect of the presented parallel algorithm.

A Parallel HEVC Intra Prediction Algorithm for Heterogeneous CPU+GPU Platforms

The high efficiency video coding standard provides excellent coding performance but is also very complex. Especially, the intra mode decision is very time-consuming due to the large number of available prediction modes and the flexible block partitioning scheme. In this paper, a highly parallel intra prediction algorithm for heterogeneous CPU+graphics processing unit (GPU) platforms is proposed, which accelerates the encoder dramatically. It is targeted toward high-quality high definition (HD) and ultra HD applications and utilizes prediction based on original samples (POSs), where the reference samples are generated from original pixels. This makes it possible to perform intramode prediction for all prediction blocks of a video frame concurrently. In addition, parallel-friendly cost functions are proposed which enable parallel rate distortion optimization with no synchronization overhead. A detailed statistical analysis of both POS and the proposed GPU intramethod is provided and the coding performance of the presented prototype is evaluated based on a large amount of experimental data. It is shown that the complexity of the intramode selection on the CPU is reduced by up to 78.03%. This translates to significant encoding time reductions of up to 64.52% for a single-threaded encoder and up to 94.82% in combination with wavefront parallel processing. In high bitrate ranges, average rate increases of only 2.11%–4.26% and 0.80%–2.34% are observed for the proposed high-speed and high-quality configurations, respectively. Furthermore, GPU intra is shown to be extremely efficient in lossless coding scenarios, where up to 53.37% time is saved with an average bitrate increase of only 0.55% among all test cases.

A Novel Wavefront-Based High Parallel Solution for HEVC Encoding

With a lot of enhanced coding tools introduced, High Efficiency Video Coding (HEVC) achieves significant improvement in coding efficiency at the cost of increased computational complexity. To efficiently reduce the encoding time of HEVC, a wavefront-based high parallel (WHP) solution integrating novel data-level and task-level methods is proposed in this paper. On data level, optimal single-instruction-multiple-data algorithms are designed for the enhanced coding tools, i.e., replacing the multiplication in motion compensation by add and shift operations with reduced instruction cycles, removing the transpose in transform via realignment of coefficients, and minimizing the memory access in sum of absolute difference/sum of squared differences calculation by fully reusing the registers. On task level, a novel inter-frame wavefront (IFW) method is developed by effectively decreasing the dependence of wavefront parallel processing (WPP). In addition, a coding tree block level parallelism analysis method is presented to prove the superior of IFW method compared with other HEVC representative parallel methods. Besides, a three-level thread management scheme is proposed to best exploit the parallelism of IFW method and achieve corresponding encoding speedup. Extensive experimental results show that, the overall WHP solution can bring up to $57.65\times $ , $65.55\times $ , and $88.17\times $ speedup for HEVC encoding of Wide Video Graphics Array, 720p and 1080p standard test sequences, while maintaining the same coding performance as with WPP. The proposed solution is also applied in several leading video companies in China, providing HEVC video service for more than 1.3 million users everyday.

4K Real-Time and Parallel Software Video Decoder for Multilayer HEVC Extensions

Two High Efficiency Video Coding (HEVC) extensions, namely, the scalable HEVC (SHVC) extension and multiview HEVC (MV-HEVC) extension, have been finalized in July 2014 by the Moving Picture Experts Group and Video Coding Experts Group. These two extensions enable additional features not covered in the first version of the HEVC standard such as spatial, fidelity, bitdepth, and color gamut scalability, as well as stereoscopic and multiview representations. In this paper, we propose a software parallel decoder architecture for the HEVC standard and its multilayer extensions, including SHVC and MV-HEVC extensions. The decoder consists of multiple instances of the OpenHEVC decoder, one instance to decode each layer with a communication between dependent layers to perform inter-layer predictions. The proposed multilayer HEVC decoder is parallel friendly and supports both wavefront parallelism to simultaneously process adjacent rows of the frame and frame-based parallelism to decode a set of temporal and spatial frames in parallel. Moreover, the most time-consuming operation introduced in the SHVC extension, namely, the resampling of the inter-layer reference picture in spatial scalability, is optimized in single instruction multiple data for x86 platform. We assess the complexity of the multilayer HEVC decoder with respect to the simulcast configuration. The multilayer decoder decoding two SHVC layers introduces in average 40%–71% additional complexity compared with the single layer HEVC decoder. Moreover, the low level optimizations with a hybrid parallel processing solution enable a real-time decoding of 4Kp60 enhancement layer on a 6-core Intel i7 processor running at 3.4 GHz.

Analysis of a Wave Front Parallel WEC Prototype

Nowadays, clean renewable energy extraction solutions are becoming a crucial practice in society. Many different sources are being developed including ocean energy and in specific, ocean waves. In deep water conditions, ocean waves can become very power dense, continuous, and forecastable. Wave height, velocity, and frequency are all variable wave characteristics making it challenging to capture wave power economically. The RTI F2 is a promising wave energy conversion device that is currently under research. Its method of power capture is a buoyant vessel oriented normal to oncoming waves. This paper discusses known control methods implemented on the RTI F2, the experimental setup used for control of the device, and wave tank testing done at the University of New Hampshire's Chase Laboratory. Experimental data was obtained across various wave conditions, plate angles, vessel weights, and control strategies. The results of these tests are presented in the subject matter.

Efficient Software H.264/AVC to HEVC Transcoding on Distributed Multicore Processors

The latest High Efficiency Video Coding (HEVC) standard achieves a significant compression efficiency improvement over the H.264/Advanced Video Coding (AVC) standard, but with a much higher computational complexity. In this paper, we propose a novel framework for software-based H.264/AVC to HEVC transcoding, integrated with tools such as wavefront parallel processing that are useful for achieving higher levels of parallelism on multicore processors and distributed systems. By utilizing information extracted from the input H.264/AVC bitstream, the transcoding process can be greatly accelerated with a visual quality loss that is modest for many applications. Based on the HEVC HM 14.0 reference software and using standard HEVC test bitstreams, the proposed transcoder can achieve up to $60\times $ speedup on a Quad Core 8-thread server over decoding–re-encoding based on FFMPEG and the HM software with a BD-rate loss of 15%–20%. By implementing a group of picture-level task distribution on a distributed system with nine processing units, the proposed software transcoder can achieve a speed for transcoding 720 p at 30 Hz in real time.

Efficient In-Loop Filtering Across Tile Boundaries for Multi-Core HEVC Hardware Decoders With 4 K/8 K-UHD Video Applications

HEVC is a next generation video coding standard designed with modern coding techniques to be especially efficient for coding high-resolution video such as 4 K/8 K-ultra high- definition (UHD) video. Among the advanced coding tools of HEVC, tiles and wavefront parallel processing (WPP) have been newly adopted for parallel processing of such high-resolution (4 K/8 K-UHD) video. To realize UHD video services over portable devices with limited battery power, it is essential to implement multi-core-based and dedicated HEVC hardware decoders that support the tile- and wavefront-based parallel processing. By doing so, each frame is divided into a multiple number of picture partitions which can then be processed by multiple hardware decoder cores in parallel. However, in-loop filtering (ILF) at tile boundaries cannot be easily parallelized by a multi-core HEVC hardware decoder because of the data dependency between samples in different tiles. In this paper, an efficient control method for ILF across tile boundaries is proposed for multi-core HEVC hardware decoders. The proposed method does not require additional in-loop filters for ILF across the tile boundaries and it allows a decoder core to continue to process the next coding tree unit (CTU) without waiting for other decoders until they finish their ILF processing for the neighboring CTUs in other tiles. From experiments, we show the effectiveness of our ILF control method via a quad-core HEVC decoder for 4 K-UHD video implemented on a prototyping FPGA board.