Wallace Tree Architecture Research Articles

Enhancement Of A 32-By-32-Bit Signed Digital Multiplier: A Multi-Dimensional Optimization Approach

In the pursuit of enhanced performance in a 32-by-32-bit signed digital multiplier, optimizations were enacted on three critical fronts. Initial efforts focused on the integration of an advanced Booth encoding technique for the generation of three-bit control signals, meticulously crafted in the Verilog programming language. This approach, characterized by its restricted symbol expansion methodology, strategically curtails hardware resource expenditures, and diminishes power utilization during computational tasks. Subsequently, a sophisticated hybrid Wallace tree architecture was employed, offering a notable decrement in the delay of two XOR gates in contrast to the exclusive application of 3-2 and 4-2 compressors. This refinement not only augments the aggregation efficacy of partial products but also substantially accelerates operational velocity. Furthermore, the incorporation of a 64-bit carry-lookahead adder was instrumental in mitigating the latency induced by lower-order carry anticipation. To ascertain the multiplier's computational precision, a Verilog-constructed testbench file facilitated the assembly of 100,000 test vectors, with simulations executed in ModelSim yielding a verifiable accuracy rate of 100%.

Implementation of High Speed Modulo (2 +1) Multiplier for IDEA Cipher

Abstract In this brief a new modulo 2n+1 multiplier is proposed for IDEA block cipher. A total of (n+1) partial products including a constant correction term are added using tree of Carry save adder with end around complemented carry followed by modulo adder. Wallace tree multiplier is adopted in order to improve the accumulation of partial products. Proposed modulo multiplier is compared with the other modulo multipliers available in the literature for IDEA block cipher. The VLSI implementation of proposed multiplier utilizing carry save tree architecture achieves (30 to 35%) improvement in the delay whereas Wallace tree architecture achieves (32 to 41.5%).

Performance Evaluation of High Speed Radix 8 Tree Based Multiplier

Multipliers are the basic building blocks of signal processing and arithmetic based systems. The objective of this paper is to design a high speed multiplier that significantly improves the performance of many high performance DSP, multimedia and communications systems. This paper proposes a high speed radix 8 Booth multiplier employing signed digit representation for recoding and radix 8 modified Booth algorithm that reduces the number of partial products to n/3. The design of the multiplier is based on Wallace tree architecture with considerable improvement in performance. This paper compares the performance of conventional multiplier with radix 4 tree based Booth multiplier and radix 8 tree based Booth multiplier. The radix 8 tree based Booth multiplier is synthesized using Quartus II simulation tool. The proposed radix 8 tree based multiplier exhibits better performance with respect to area and operating frequency when compared to conventional multiplier.

A chip set for pipeline and parallel pipeline FFT architectures

A chip set for pipelined and parallel pipelined FFT applications is presented. The set consists of two cascadeable chips with built-in self-test and a chip-interconnectivity test feature. The two ASICs are a 15k gate Complex-Butterfly and a 9k gate FFT Switch. The Complex-Butterfly uses redundant binary arithmetic (RBA), a modified Booth algorithm and a Wallace tree architecture to achieve a throughput of better than 25 Msamples/sec. The cascadeable FFT Switch is designed to support the implementation of radix-2, 2N point, pipeline FFTs. Both devices have been fabricated in 1.5μm CMOS gate array technology.