Wafer Volume Research Articles

What is driving the 3D TSV technologies business: Market update and technical trends

Through-silicon vias (TSVs) have now become the preferred interconnect choice for high-end memory. They are also an enabling technology for heterogeneous integration of logic circuits with CIS, MEMS, sensors, and RF filters. In the near future they will also enable photonics and LED function integration. The market for 3D TSV and 2.5D interconnect is expected to reach around 2.1 million wafers in 2021, expanding at an 18% CAGR. The growth is driven by increased adoption of 3D memory devices in high-end graphics, high-performance computing, networking and data centers, and penetration into new areas, including fingerprint and ambient light sensors, RF filters and LEDs. CIS still commanded more than 80% share of TSV market wafer volume in 2015, although this will decrease to around 56% by 2021. This is primarily due to the growth of the other TSV applications, led by 3D memories, RF filters and fingerprint sensors. However, hybrid stacked technology, which uses direct copper-copper bonding, not TSVs, will penetrate around 38% of CIS production by 2021. The presentation will explain the market's dynamics and give an overview of all segments and key markets of the TSV based 3D/2.5D IC packaging.

Guest Editorial Special Section on the 2016 International Conference on Compound Semiconductor Manufacturing Technology (CS MANTECH)

As guest editors for the special section on the 2016 International Conference on Compound Semiconductor Manufacturing Technology (CS MANTECH), we are pleased to present the readership of IEEE Transactions on Semiconductor Manufacturing with a selection of papers developed from presentations made at this year’s conference. While semiconductor wafer volume is dominated by technologies based on silicon, compound semiconductor devices and integrated circuits are important for a range of applications and markets. Compound semiconductors have traditionally found use in technological areas demanding maximum performance, often for high speed or high frequency applications. Examples include high-speed wired, fiber, and point-to-point communications infrastructure, defense-related sensing and communications, and high-efficiency RF power amplifiers in consumer mobile wireless applications. However, recent trends have been eroding these traditional distinctions, with emerging applications such as power control and commercial wireless infrastructure being increasingly addressed using GaN and related materials, while ultra-low-power analog–and even future CMOS nodes for logic–embracing narrow-band gap III-V materials.

Silicon-Embedding Approaches to 3-D Toroidal Inductor Fabrication

This paper presents complementary-metal-oxide-semiconductor-compatible silicon-embedding techniques for on-chip integration of microelectromechanical-system devices with 3-D complex structures. By taking advantage of the “dead volume” within the bulk of the silicon wafer, functional devices with large profile can be embedded into the substrate without consuming valuable die area on the wafer surface or increasing the packaging complexity. Furthermore, through-wafer interconnects can be implemented to connect the device to the circuitry on the wafer surface. The key challenge of embedding structures within the wafer volume is processing inside deep trenches. To achieve this goal in an area-efficient manner, straight-sidewall trenches are desired, adding additional difficulty to the embedding process. Two approaches to achieve this goal are presented in this paper, i.e., a lithography-based process and a shadow-mask-based process. The lithography-based process utilizes a spray-coating technique and proximity lithography in combination with thick epoxy processing and laminated dry-film lithography. The shadow-mask-based process employs a specially designed 3-D silicon shadow mask to enable simultaneous metal patterning on both the vertical sidewall and the bottom surface of the trench during deposition, eliminating multiple lithography steps and reducing the process time. Both techniques have been demonstrated through the embedding of the topologically complex 3-D toroidal inductors into the silicon substrate for power supply on-chip (PwrSoC) applications. Embedded 3-D inductors that possess 25 turns and a diameter of 6 mm in a silicon trench of 300-μm depth achieve overall inductances of 45-60 nH, dc resistances of 290-400 mΩ, and quality factors of 16-17.5 at 40-70 MHz.

Reduction of Greenhouse Gas Emissions by Metal Interconnect Etch Process Optimization

Fluorine containing dry etch processes have been a cornerstone of semiconductor manufacturing since inception of the industry. Greenhouse gases (GHG) commonly used in device fabrication are CF4, C2F6, SF6, CHF3 and NF3. Texas Instruments Incorporated has been voluntarily pursuing GHG priorities aligned with ISO14001:2004, World Semiconductor Council and United States Environmental Protection Agency (1,2). This paper details manufacturing and unit process optimization to eliminate CHF3 in metal interconnect dry etch of an aluminum - copper analog 180nm technology node process flow in 200mm wafer volume production.

A multi-layer electro-optic field probe

We present a novel design method and sensing scheme for an electro-optic field probe using multi-stratified layers of electro-optic wafers. A serial stack of cascaded layers is found to be capable of enhancing the performance of interferometric electro-optic light modulation that utilizes the slopes of interference fringe patterns and field-induced electro-optic phase retardations within wafers. The absolute sensitivity of the probe is also characterized with a micro-TEM cell that generates electric fields distributions with accurate, calculable strength for use in probe calibration. The sensitivity of a multi-layered probe-per unit electro-optic wafer volume--was enhanced by 6 dB compared to that of a single-layer one.

Effect of compensation and of metallic impurities on the electrical properties of Cz-grown solar grade silicon

In this work we present a study of a p-type Czochralski-grown Si ingot which was grown using 10% solar grade silicon (SoG-Si). As the SoG-Si contains a relatively high concentration of impurities including phosphorus, the electrical properties of the as-grown wafers from this ingot are affected by both the compensating dopants and other impurities. Measurements of the minority charge carrier lifetime in the as-grown material reveal very low values (4–8μs). The Hall mobilities at room temperature correspond to normal values for Czochralski silicon in the upper part of the ingot (which solidifies first) and decrease significantly toward the bottom of the ingot. Segregation leads to an accumulation of impurities toward the lower parts of the ingot as well as to a stronger increase in phosphorus than of boron, the latter of which results in a high compensation level (i.e., an increasing resistivity). A priori, both effects could be responsible for the degradation of the electrical properties in the lower parts of the ingot, whereas theoretical considerations show that the level of compensation should not cause a strong decrease in Hall mobility at room temperature. Untextured solar cells have been processed from wafers originating from different positions of the ingot. As expected, the phosphorus diffusion leads to a gettering effect: the recombination active impurities are removed out of the wafer volume. This results in relatively high efficiencies (>16%) of the solar cells but does not show a strong correlation between ingot height and cell efficiency. This observation is also confirmed by the high bulk lifetimes (>200μs) measured after the process even for samples originating from the last solidified (lower)part of the ingot. The Hall mobility of samples cut from finished solar cells has been measured and shows the same trend as the as-grown samples, the values for the bottom of the ingot still being very low. With the concentrations of boron and phosphorus studied up to this point, compensation showed no detrimental effect on the cell efficiency of industrial-like solar cells.

E-beam writing: a next-generation lithography approach for thin-film head critical features

Magnetic recording areal densities using magnetoresistive (MR) head technology are increasing at annual rates in excess of 60% per year and in some applications as great as 100% per year. Today, the critical features of the thin-film head can be patterned with the same optical lithography techniques used by the semiconductor industry. However, with the assumption that areal density increases in magnetic recording are maintained, within the next rive years, thin-film head lithography requirements will exceed semiconductor roadmap projections. This paper describes the use of e-beam lithography as an alternative to optical lithography for the fabrication of critical features in the thin-film head. In particular, the unique geometry of the head structure, the low density of critical head features on the wafer, and the relatively low wafer volume requirements for thin-film heads allow e-beam lithography to become a viable manufacturing alternative for thin-film head fabrication. More important, e-beam lithography is ideally suited for producing thin-film head structures at a development level prior to the optimization of manufacturable optical processing.

Copper precipitation in long‐time processed transistor samples

AbstractProcess‐induced crystal defects (point defects and extended defects) in completely processed transistor samples of floating zone silicon have been investigated by TEM analysis and DLTS measurements. It was possible to demonstrate that the lifetime of these samples is determined by the introduction of copper during the long‐time processing of the wafers. The predominant crystal defects within the wafer volume were found to be circular monolayers of copper silicide which due to their appearance could be easily confounded with stacking faults.