Surface Roughness Of Wafer Research Articles

Impact of Ar plasma bombardment on the composition and surface roughness of GaAs wafer

The surface property of GaAs has an important impact on device performance, so how to improve the surface quality in reactive ion etching process is one of the key issues. In this paper, the composition and roughness changes of GaAs surface subjected to Ar plasma bombardment were investigated. It was found that the relative contents of Ga2O3 and As2O3 of the surface decreased with the increase of RF power, and the distribution depths of the compositions were different. In addition, dielectric constant increased with the increase of RF power. It was found that the surface roughness can be reduced after the plasma bombardment. Furthermore, the surface roughness and Ga/As component ratio followed a certain trend with the RF power. When the RF power was lower than 150 W, the surface roughness and Ga/As component ratio had the same trend, and when the RF power was higher than 150 W, they had the opposite trend. These results are helpful for the improvement of GaAs-based wafer-bonding strength and the performance of optoelectronic structures.

Experimental study regarding the surface roughness of circular crystal wafers sliced by a multi-wire saw with reciprocating and rocking functions

Experimental study regarding the surface roughness of circular crystal wafers sliced by a multi-wire saw with reciprocating and rocking functions

Optimizing the diamond wire sawing of polycrystalline silicon: An experimental approach

This study aims to determine the optimized cutting conditions for diamond wire sawing of polycrystalline silicon (poly-Si) wafers using a laboratory machine-tool that employs continuous cutting movement and reach cutting conditions similar to those in the industry. The experimental cutting was carried out following a central composite design, varying the wire cutting speed (vc) and feed rate (vf). A response surface methodology was employed to find the optimized cutting conditions for minimum surface roughness and subsurface micro-crack depth of the as-sawn poly-Si wafer. The results showed that the as-sawn poly-Si exhibited ductile scratches and fragile fractures in its surface morphology, with high vc and low vf resulting in a smooth surface. The response surfaces indicated that increasing vf led to increased Ra and Rq values, while increasing vc reduced them. Median micro-cracks were slightly inclined in the subsurface region, with the response surface indicating that their depth reduced with increasing vc and decreasing vf. The vf/vc ratio significantly affected surface integrity, with a lower vf/vc ratio being more suitable for reaching a smoother surface and shallower subsurface damage. The following material removal mechanisms was identified: optimal ductile region, ductile-to-brittle transition, brittle-ductile mixture region, and brittle region. Simulations using the response surface models indicated minimum values of Ra = 0.35 μm, Rq = 0.48 μm and SSD = 3.29 μm. Thus, this study provides a processing parameter window for diamond wire sawing of poly-Si wafers, which could be useful for both the photovoltaic and microelectronic industries.

Simulation modeling of wafer grinding surface roughness considering grinding vibration

When using the workpiece rotation method to grind wafers, the grinding end vibration will deteriorate the surface roughness of the wafers. To study the impact law of vibration on the surface roughness of wafers during the grinding procedure, this paper presents a new approach to simulate and model the surface roughness of wafer grinding considering the grinding vibration. Firstly, the dynamics model under the consideration of grinding force was established for the grinding end of the grinding wheel and workpiece turntable. Secondly, using the iterative method to solve the dynamic equations that have been established, the vibration equation is obtained by fitting the displacement vibration curve of the end. Then, by reconstructing the surface grain of the gear teeth, a simulation model of wafer grinding surface roughness was established considering material removal, grain motion and grinding vibration. And then the grinding comparison test was conducted to compare the simulation and test surface roughness measurement results. The maximum deviation of the surface roughness Sz and Sa was 7.7 % and 5.4 %, respectively. The results indicate the accuracy of the modeling. Finally, based on the established wafer roughness model, explore the impact of vibration on wafer roughness during the grinding procedure. This model provides a reference for the research of wafer precision grinding technology.

Study on the polishing performance and mechanism of sapphire wafers by different types of degradable surfactants

Traditional chemical-mechanical polishing (CMP) slurry suffers from significant environmental pollution, and easy reaggregation of ultra-fine abrasives, all of which hinder its further application. In this study, the processing performance and mechanism of three different degradable surfactants to sapphire wafers were investigated, utilizing degradable aminomethylpropanol and xylitol as pH regulator and complexing agent of polishing slurry, respectively, which is aimed at solving the problem of the easy agglomeration of ultra-fine abrasives while achieving the super-precision and pollution-free process of sapphire wafers. After polishing, the surface roughness (Sa) of sapphire wafers decreases from 7.240 nm to 0.396 nm, which is 44.8 % lower than that without surfactant. Only <1 nm is the PV value, and there is a 12.9 % increase in the material removal rate. The action mechanism of biodegradable surfactants during CMP was revealed through TEM, XPS, electrochemical testing, contact angle measurement, and particle size analysis. The results showed that surfactants can effectively improve the wettability of the polishing slurry on the wafer and the dispersity of the ultra-fine abrasives in the slurry, thus facilitating the interfacial reaction between the sapphire surface and polishing slurry and the homogeneity of the material removal. This work truly realizes a green and pollution-free process that meets the requirements of ultra-smooth and efficient polishing of sapphire wafers.

(Dielectric Science and Technology Poster Award, 2nd Place) Activation of Amine Chemistries for the Enhanced Particle Removal Efficiency of CeO2 Nanoparticles Via Megasonic Processing Conditions

With the persistent advancement of semiconductor technology, the demand for high-efficiency device manufacturing processes has surged. Chemical Mechanical Planarization (CMP) is a cornerstone for achieving angstrom-scale surface uniformity crucial for integrated circuits (IC) and logic devices. Shallow Trench Isolation (STI) CMP involves the selective removal of bulk oxide to electrically isolate active components on wafer surfaces. The modulation of the Ce3+ to Ce4+ surface state is essential for improved performance in both CMP and post-CMP (p-CMP) applications. Ce3+ is ideal for oxide material polishing due to its strong adherence to oxide surfaces, while Ce4+ is optimal for p-CMP cleaning, given its weak bond to oxide surfaces. Current p-CMP industry-standard methods utilize mechanical approaches, such as polyvinyl alcohol (PVA) brush scrubbing. However, this process induces high levels of shear force (SF), leading to secondary defects on the wafer surface (i.e. scratches, corrosion, increased surface roughness). To address these limitations, non-contact cleaning methods utilizing megasonic energy have emerged, which rely on generating reactive oxygen species (ROS) to induce particle removal. Thus, this study focuses on enhancing ceria particle removal during post-CMP cleaning by employing amine-based chemistries coupled with megasonic energy. While preliminary results imply that the mechanical cavitations induced by megasonic waves improve cleaning efficiency, this method will be optimized via the introduction of amine-based chemistries. Specifically, this work aims to leverage the unique properties of amines coupled with megasonic energy to facilitate enhanced ceria removal through electron donation, inducing a reduction in the oxidation state of ceria from Ce³⁺ to Ce⁴⁺. This approach improves particle removal while limiting secondary defects, enhancing redox activity induced by megasonic waves and chemical interactions. The mechanisms behind this method will be validated with CeO2 oxidation state kinetics, interfacial frictional changes, wafer surface roughness analysis, and SEM validation of particle removal efficiency.

High-Quality 4H-SiC Homogeneous Epitaxy via Homemade Horizontal Hot-Wall Reactor

In this paper, using a self-developed silicon carbide epitaxial reactor, we obtained high-quality 6-inch epitaxial wafers with doping concentration uniformity less than 2%, thickness uniformity less than 1% and roughness less than 0.2 nm on domestic substrates, which meets the application requirements of high-quality Schottky Barrier Diode (SBD) and Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET) devices. We found that increasing the carrier gas flow rate can minimize source gas depletion and optimize the doping uniformity of the 6-inch epitaxial wafer from over 5% to less than 2%. Moreover, reducing the C/Si ratio significantly can suppress the “two-dimensional nucleation growth mode” and improve the wafer surface roughness Ra from 1.82 nm to 0.16 nm.

Laser Lithography of Monolithically‐Integrated Multi‐Level Microchannels in Silicon

AbstractThe trend toward ever‐increased speeds for microelectronics is challenged by the emergence of heat‐wall, leading to the faltering of Moore's Law. A potential solution may be integrating microfluidic channels into silicon (Si), to deliver controlled amounts of cooling fluid and regulate hot spots. Such meandering microfluidic channels within other transparent materials already played significant roles, including in biomedical and sensor applications; however, analogous channel architectures do not exist in Si. Here, a novel method is proposed to fabricate buried microchannel arrays monolithically integrated into Si, without altering the wafer surface. A two‐step, laser‐assisted subtractive removal method is exploited, enabling fully‐buried multi‐level architectures, with control on the channel port geometry, depth, curvature, and aspect ratio. The selective removal rate is 750 µm per h per channel, and the channel inner‐wall roughness is 230 nm. The method preserves top wafer surface roughness of 2 nm, with significant potential for 3D integrated systems.

Fabrication and Polishing Performance of Diamond Self-Sharpening Gel Polishing Disk.

A diamond gel polishing disk with self-sharpening ability is proposed to solve the problem of glazing phenomenon in the gel polishing disks. Aluminum nitride (AlN) powder with silica sol film coating (A/S powder) is added to the polishing disk, and a specific solution is used to dissolve the A/S powder during polishing, forming a pore structure on the polishing disk. To realize the self-sharpening process, the dissolution property of the A/S powder is analyzed. The effect of A/S powder content on the friction and wear performance and the polishing performance of 4H-SiC wafers are investigated. Results showed that the friction coefficient of the polishing disk with 9 wt% A/S powder content is the most stable. The surface roughness Ra of 2.25 nm can be achieved, and there is no obvious glazing phenomenon on the polishing disk after polishing. The surface roughness of the 4H-SiC wafer is reduced by 38.8% compared with that of the polishing disk with no A/S powder addition after rough polishing, and the 4H-SiC wafer then obtained a damage-free surface with a Ra less than 0.4 nm after fine polishing by chemical mechanical polishing (CMP).

The role of ammonium citrate and dodecyl pyridinium chloride on chemical mechanical polishing relevant to SiO2 dielectric layer

Silicon dioxide films are widely utilized in integrated circuit manufacturing for their excellent properties, including applications in shallow trench isolation and interlayer dielectrics. Chemical mechanical polishing (CMP) has a pivotal part in achieving material planarization across integrated circuit manufacturing process. This study delves into the mechanisms of ammonium citrate and dodecyl pyridinium chloride in the CMP of silicon dioxide dielectric layers, alongside optimizing the concentration ratios of the slurry components. The incorporation of ammonium citrate effectively mitigates electrostatic repulsion between the abrasive and the wafer surface, thereby augmenting the mechanical interactions during polishing. The introduction of dodecyl pyridinium chloride further enhances material removal rates while concurrently reducing surface roughness. Notably, employing the slurry with the optimized composition ratios yields a notable reduction in surface defects after CMP. Extensive characterization techniques, including X-ray photoelectron spectroscopy and scanning electron microscope, were devoted to elucidate the mechanisms of the additives and assess the stability of the slurry. This study substantiates that the incorporation of ammonium citrate and dodecyl pyridinium chloride in the slurry not only sustains a high material removal rate but also achieves superior outcomes in terms of lower wafer surface roughness and diminished wafer surface defects.

Cutting force modeling and control of single crystal silicon using wire saw velocity reciprocation

Single crystal silicon wafers are often used as substrate material for integrated circuits. Often the wafer is cut by a wire with fixed abrasive diamond owning to a narrow kerf and a low cutting force. The cutting force changes during the process as the direction of wire movement continuously reverses (i.e., reciprocates), which may cause the wire saw to break, the wafer to collapse, and the wafer surface roughness to decrease even if the wire saw tension and the contact length between the wire and the wafer are fixed. In this work, a cutting force model including both normal and tangential forces was established to determine the relationship between the normal and tangential forces and the commanded wire speed. Separate controllers were developed to regulate both the normal force and the tangential force by adjusting the wire velocity. Experimental studies were conducted for wire saw processing of single crystal silicon wafers. Compared with a process using constant wire velocity, regulating the normal force can significantly reduce the processing time and the wafer surface roughness. The average improvements in processing time and wafer surface roughness are approximately 11% and 56%, respectively, when using normal force control, and approximately 29% and 30%, respectively, when using tangential force control. The results show that the normal and tangential forces can be well regulated during the machining process. In addition, the wafer surface roughness and machining time were lower in both experiments where the forces were regulated than in the experiment where a constant wire velocity was used. This paper demonstrates that the novel concept of regulating process forces in wire saw machining by adjusting the wire velocity can be used to optimize the cutting process of single crystal silicon, making the process more productive while decreasing the part roughness.

Study on surface characteristics of as-sawn sapphire crystal wafer considering diamond saw wire wear

Sapphire crystal is widely used as Light Emitting Diode (LED) substrate and window materials for electronic devices. During the sawing process of sapphire crystal, the wear of saw wire leads to different sawing performance. In this paper, the abrasives wear state, the diameter change and wear rate of the saw wire, the change of surface morphology and surface roughness (SR) of as-sawn sapphire crystal wafer during the whole service cycle of saw wire under typical sawing parameters were analyzed, and the stable service period of diamond saw wire was determined. Further, sawing experiments were conducted during the stable service period of diamond saw wire, and the effects of sawing parameters within the industrial production on the as-sawn sapphire crystal wafers surface characteristics were studied. The results show that within range of sawing parameters adopted in this paper, the abrasives mainly remove the material in a brittle mode, and the SR of the as-sawn wafers decreases as the saw wire speed increases (from 1000 m/min to 1600 m/min), and the as-sawn wafer surface morphology is improved. As the specimen feed speed increases (from 0.05 mm/min to 0.5 mm/min), the SR increases, and the consistency of the as-sawn wafer surface morphology deteriorates.

Ultrasonic vibration assisted double disc chemo-magnetorheological finishing of silicon wafer: Experimental investigations and optimization for surface roughness

To polish the surface of silicon wafers, the impact of ultrasonic vibration assistance on the double disc chemo-magnetorheological finishing was investigated. The in-house setup was fabricated to provide vibrations to the workpiece during the polishing in the longitudinal direction. The central composite design (CCD) approach was adopted in experiment planning to understand the influence of process parameters (like magnets rotation, abrasive concentration, and ultrasonic power) on the surface roughness ([Formula: see text]). A 3D optical profilometer was employed to check the surface roughness of the polished wafers. The individual and interaction of significant process factors affecting were determined using the analysis of variance (ANOVA) technique. A regression equation based on response surface methodology was developed. The process parameters were optimized using a genetic algorithm to maximize the change in surface roughness before and after polishing. The experiment performed at an optimized set resulted in an average surface finish of 3.4 nm. A 3D surface plots and scanning electron microscopy (SEM) were used to understand the changes on the surfaces of unpolished and polished samples at the optimized parameters.

Effects of argon plasma pretreatment of Si wafers on Si-Si bonding based on Mo/Au interlayers

To improve the bonding quality of Si-Si wafers bonded based on Mo/Au intermediate layers at room temperature, the surfaces of Si wafers were pretreated with argon plasma, and the effect of argon plasma pretreatment on Si-Si wafer bonding was analyzed by combining experimental and theoretical methods. Owing to the plasma treatment of Si wafers, the surface roughness of Si wafers was significantly reduced, and the bonded Si-Si samples had lower interfacial voidage. The average bonding strength of 11.46 MPa for the argon plasma pretreated Si-Si bonded samples is much higher than the bonding strength of 4.23 MPa for the unpretreated Si-Si bonded samples. The analysis of the fractured surface revealed that the fracture of the Si-Si bonded samples without argon plasma treatment occurred mainly at the Mo/Si interface, while the fracture of the plasma-treated Si-Si bonded samples arose mainly within the bulk Si. Molecular dynamics (MD) simulations suggest that strong atomic diffusion takes place at the Mo/Au interface, while Mo atoms hardly diffuse into the bulk Si. These results indicate that argon plasma pretreatment not only cleans and activates the Si wafer surface but also makes the Si wafer surface smooth, which helps to enhance the deposited Mo/Au film quality and the adhesion between the Mo film and the Si wafer.

Experimental Study on the Influence of Wire-Saw Wear on Cutting Force and Silicon Wafer Surface.

Hard and brittle materials such as monocrystalline silicon still occupy an important position in the semiconductor industry, but hard and brittle materials are difficult to process because of their physical properties. Fixed-diamond abrasive wire-saw cutting is the most widely used method for slicing hard and brittle materials. The diamond abrasive particles on the wire saw wear to a certain extent, which affects the cutting force and wafer surface quality in the cutting process. In this experiment, keeping all the given parameters unchanged, a square silicon ingot is cut repeatedly with a consolidated diamond abrasive wire saw until the wire saw breaks. The experimental results show that the cutting force decreases with the increase in cutting times in the stable grinding stage. The wear of abrasive particles starts at the edges and corners, and the macro failure mode of the wire saw is fatigue fracture. The fluctuation of the wafer surface profile gradually decreases. The surface roughness of wafer is steady during the wear steady stage, and the large damage pits on the wafer surface are reduced in the whole process of cutting.

Conversion efficiency improvement of ELO GaAs solar cell, deposited on water soluble sacrificial buffer

We demonstrate the improvement of power conversion efficiency of an epitaxially-lifted-off single junction GaAs solar cell deposited on a water-soluble sacrificial buffer architecture by introducing an additional germanium (Ge) interlayer between GaAs and the fluoride buffer. The epitaxial lift-off (ELO) technique has been extensively used to separate III-V device layers from their single crystal GaAs substrates. However, conventional ELO requires the use of concentrated hydrofluoric acid (HF) for extended times to etch out the sacrificial layer, subsequently degrading the surface roughness of the parent wafer. As a result, the wafer has to undergo expensive and intensive chemical mechanical polishing (CMP) processes, costing about 25 % of a pristine 6-inch GaAs substrate. In our previous work, we demonstrated a method to eliminating the need for CMP post-processing by using water-assisted ELO (H2O-ELO). A water-soluble, 3-layer buffer architecture was developed using alkaline earth compounds. However, devices suffered low performance due to a high defect density in the GaAs active layers. A Ge interlayer was introduced to provide a more favorable surface energy for GaAs growth, which leads to an improvement of GaAs crystal quality. The Ge deposition conditions were optimized to achieve a high-quality Ge layer on triple-layer fluoride buffer. Single junction GaAs devices fabricated on Ge/(Ca,Sr)F2/BaF2/(Ca,Sr)F2 showed improvement of solar cell performance parameters featuring increases in Voc by 23.7 %, and fill factor (F.F.) by 4.9 %, which results in an overall improvement of power conversion efficiency from 10.3 % to 12.69 %.

Image-processing-based model for the characterization of surface roughness and subsurface damage of silicon wafer in diamond wire sawing

The damages of silicon wafer in diamond wire sawing have a significant impact on its mechanics, economy, and use properties, which should be evaluated accurately and quickly. A theoretical model is developed to determine the surface roughness Rz (ten-point mean height) and subsurface damage (SSD) depth by the fracture width of silicon wafer. The model takes into account the scratch groove direction and material pile-up effect of silicon wafer. A digital image processing method is integrated into the model to extract the fracture parameters of silicon wafer. Many silicon wafers are processed under different slicing parameters, for which the fracture parameters and surface roughness Rz are measured by confocal microscopy, and the SSD depth is measured with the method of cross-section scanning microscopy. The scratch-induced material pile-up height is evaluated by nanoscratching. The calculated and measured fracture parameters, surface roughness Rz, and SSD depth are analyzed by contrast. The result shows that the model can accurately and quickly determine the surface roughness Rz and SSD depth with an average relative error of less than 12.0% in 20 s. The distribution characteristics of fractures, surface roughness, and SSD are analyzed. The result shows that more fractures have relatively smaller fracture width, depth, length, or related SSD depth. The image-processing-based model would be a reasonable approach for estimating the damages in silicon wafers during wire sawing.

Prediction and verification of wafer surface morphology in ultrasonic vibration assisted wire saw (UAWS) slicing single crystal silicon based on mixed material removal mode

Monocrystalline silicon slicing is the first step in making chips, and the surface quality of silicon wafers directly affects the quality of later processing and accounts for a large proportion in the chip manufacturing cost. Ultrasonic vibration assisted wire saw (UAWS) is an effective sawing process for cutting hard and brittle materials such as monocrystalline Si, which can significantly improve the surface quality of silicon wafers. In order to further study the formation mechanism of the surface morphology of single crystal silicon sliced by UAWS, a new model for prediction of wafer surface morphology in UAWS slicing single crystal silicon based on mixed material removal mode is presented and verified by experiments in this paper. Firstly, the surface model of diamond wire saw tool is established by equal probability method. Then, the trajectory equation of arbitrary abrasive particles on the surface of wire saw is derived and analyzed. Thirdly, a new model for prediction of the wafer surface morphology based on mixed material removal mode is presented. Finally, the prediction model is verified by UAWS slicing experiment, and the effects of slicing parameters such as wire saw speed, feed speed, and workpiece rotate speed on the surface quality of silicon wafer were studied. It shows that the predicted wafer surface morphology and the experimental wafer surface morphology are similar in some characteristics, and the average error between the experimental and the theoretical values of the wafer surface roughness is 11.9%, which verifies the validity of the prediction model.

Undeformed chip width non-uniformity modeling and surface roughness prediction in wafer self-rotational grinding process

Silicon wafers are commonly thinned employing an ultra-precision grinding machine based on a workpiece self-rotational principle. The diamond grains, stochastically located on the grinding wheel surface, remove the workpiece material and generate a difference in the size and shape of undeformed chips. However, an in-depth understanding of the grain-workpiece interaction randomness in wafer thinning process and its link with surface roughness has not been revealed yet. In this paper, a new index, i.e., undeformed chip width, is first proposed to analyze and describe the stochastic characteristics in material removal process as well as predict the surface roughness of ground wafer. The grinding wheel morphology is constructed by the random operation for grain size and position. Then, a 2D topography generation model is established to calculate the undeformed chip width. The non-uniform distribution characteristics of undeformed chip width under different grinding conditions are further analyzed. Finally, the relation between undeformed chip width and surface roughness of ground wafer is presented. The correctness of developed models is verified using a series of grinding experiments.

Study on the processing characteristics of sapphire wafer polished with different properties plates

To realize the processing demands of the sapphire wafer surface with scratch-free and nano-scale roughness by mechanical polishing, a novel flexible polishing plate was developed by using soft unsaturated resin. The surface characteristics, material removal rate, and residual stress of the sapphire wafer after the flexible polishing process have been compared with those of the sapphire wafer after the rigid polishing process. Both theoretical and simulation analysis results show that the abrasive particles in the flexible polishing exhibit an apparent yielding effect during the polishing course, which contributes to the achievement of plastic flow removal for the wafer surface. The experimental results show that the surface roughness and subsurface damage of the sapphire wafer polished by the flexible polishing process can be decreased by 18.7% and 57.3%, respectively, compared with those of the sapphire wafer polished by the rigid polishing process.