Wafer-sized Graphene Research Articles

Polyacrylonitrile as an Efficient Transfer Medium for Wafer-Scale Transfer of Graphene.

The disparity between growth substrates and application-specific substrates can be mediated by reliable graphene transfer, the lack of which currently strongly hinders the graphene applications. Conventionally, the removal of soft polymers, that support the graphene during the transfer, would contaminate graphene surface, produce cracks, and leave unprotected graphene surface sensitive to airborne contaminations. In this work, it is found that polyacrylonitrile (PAN) can function as polymer medium for transferring wafer-size graphene, and encapsulating layer to deliver high-performance graphene devices. Therefore, PAN, that is compatible with device fabrication, does not need to be removed for subsequent applications. The crack-free transfer of 4 in. graphene onto SiO2/Si wafers, and the wafer-scale fabrication of graphene-based field-effect transistor arrays with no observed clear doping, uniformly high carrier mobility (≈11000 cm2 V-1 s-1), and long-term stability at room temperature, are achieved. This work presents new concept for designing the transfer process of 2D materials, in which multifunctional polymer can be retained, and offers a reliable method for fabricating wafer-scale devices of 2D materials with outstanding performance.

Revealing the Crystalline Integrity of Wafer-Scale Graphene on SiO2/Si: An Azimuthal RHEED Approach.

The symmetry of graphene is usually determined by a low-energy electron diffraction (LEED) method when the graphene is on the conductive substrates, but LEED cannot handle graphene transferred to SiO2/Si substrates due to the charging effect. While transmission electron microscopy can generate electron diffraction on post-transferred graphene, this method is too localized. Herein, we employed an azimuthal reflection high-energy electron diffraction (RHEED) method to construct the reciprocal space mapping and determine the symmetry of wafer-size graphene both pre- and post-transfer. In this work, single-crystalline Cu(111) films were prepared on sapphire(0001) and spinel(111) substrates with sputtering. Then the graphene was epitaxially grown on single-crystalline Cu(111) films with a low pressure chemical vapor deposition. The reciprocal space mapping using azimuthal RHEED confirmed that the graphene grown on Cu(111) films was single-crystalline, no matter the form of the monolayer or multilayer structure. While the Cu(111) film grown on sapphire(0001) may occasionally consist of 60° in-plane rotational twinning, the reciprocal space mapping revealed that the in-plane orientation of graphene grown atop was not affected. The proposed method for checking the crystalline integrity of the post-transferred graphene sheets is an important step in the realization of the graphene as a platform to fabricate electronic and optoelectronic devices.

Online Determination of Graphene Lattice Orientation Through Lateral Forces

Rapid progress in graphene engineering has called for a simple and effective method to determine the lattice orientation on graphene before tailoring graphene to the desired edge structures and shapes. In this work, a wavelet transform-based frequency identification method is developed to distinguish the lattice orientation of graphene. The lattice orientation is determined through the different distribution of the frequency power spectrum just from a single scan line. This method is proven both theoretically and experimentally to be useful and controllable. The results at the atomic scale show that the frequencies vary with the lattice orientation of graphene. Thus, an adjusted angle to the desired lattice orientation (zigzag or armchair) can easily be calculated based on the frequency obtained from the single scan line. Ultimately, these results will play a critical role in wafer-size graphene engineering and in the manufacturing of graphene-based nanodevices.Electronic supplementary materialThe online version of this article (doi:10.1186/s11671-016-1553-z) contains supplementary material, which is available to authorized users.

Controllable Sliding Transfer of Wafer-Size Graphene.

The innovative design of sliding transfer based on a liquid substrate can succinctly transfer high-quality, wafer-size, and contamination-free graphene within a few seconds. Moreover, it can be extended to transfer other 2D materials. The efficient sliding transfer approach can obtain high-quality and large-area graphene for fundamental research and industrial applications.

ChemInform Abstract: Chemical Vapor Deposition of Graphene Single Crystals

AbstractReview: 46 refs.

Chemical Vapor Deposition of Graphene Single Crystals

As a two-dimensional (2D) sp(2)-bonded carbon allotrope, graphene has attracted enormous interest over the past decade due to its unique properties, such as ultrahigh electron mobility, uniform broadband optical absorption and high tensile strength. In the initial research, graphene was isolated from natural graphite, and limited to small sizes and low yields. Recently developed chemical vapor deposition (CVD) techniques have emerged as an important method for the scalable production of large-size and high-quality graphene for various applications. However, CVD-derived graphene is polycrystalline and demonstrates degraded properties induced by grain boundaries. Thus, the next critical step of graphene growth relies on the synthesis of large graphene single crystals. In this Account, we first discuss graphene grain boundaries and their influence on graphene's properties. Mechanical and electrical behaviors of CVD-derived polycrystalline graphene are greatly reduced when compared to that of exfoliated graphene. We then review four representative pathways of pretreating Cu substrates to make millimeter-sized monolayer graphene grains: electrochemical polishing and high-pressure annealing of Cu substrate, adding of additional Cu enclosures, melting and resolidfying Cu substrates, and oxygen-rich Cu substrates. Due to these pretreatments, the nucleation site density on Cu substrates is greatly reduced, resulting in hexagonal-shaped graphene grains that show increased grain domain size and comparable electrical properties as to exfoliated graphene. Also, the properties of graphene can be engineered by its shape, thickness and spatial structure. Thus, we further discuss recently developed methods of making graphene grains with special spatial structures, including snowflakes, six-lobed flowers, pyramids and hexagonal graphene onion rings. The fundamental growth mechanism and practical applications of these well-shaped graphene structures should be interesting topics and deserves more attention in the near future. Following that, recent efforts in fabricating large single-crystal monolayer graphene on other metal substrates, including Ni, Pt, and Ru, are also described. The differences in growth conditions reveal different growth mechanisms on these metals. Another key challenge for graphene growth is to make graphene single crystals on insulating substrates, such as h-BN, SiO2, and ceramic. The recently developed plasma-enhanced CVD method can be used to directly synthesize graphene single crystals on h-BN substrates and is described in this Account as well. To summarize, recent research in synthesizing millimeter-sized monolayer graphene grains with different pretreatments, graphene grain shapes, metal catalysts, and substrates is reviewed. Although great advancements have been achieved in CVD synthesis of graphene single crystals, potential challenges still exist, such as the growth of wafer-sized graphene single crystals to further facilitate the fabrication of graphene-based devices, as well as a deeper understanding of graphene growth mechanisms and growth dynamics in order to make graphene grains with precisely controlled thicknesses and spatial structures.

Self-regulating homogenous growth of high-quality graphene on Co–Cu composite substrate for layer control

The composite substrate of Co and Cu was proposed to grow homogenous high quality wafer-size graphene films by an atmosphere pressure CVD method. The composite substrate consists of a moderate-carbon-solubility metal top (Co coating) as a C-dissolving layer and a low-carbon-solubility metal base (Cu foil) as a C-rejecting layer. During the CVD process, the interdiffusion of Co and Cu atoms occurs in the composite. With the dynamic control on Co and Cu alloying process to affect the carbon solubility, active carbon atoms captured by the Co layer were segregated to form spontaneously a high-quality graphene film on the top of Cu-Co substrate. The tunable layer-number of the graphene films can be precisely controlled by adjusting the thickness of the Co layer. High quality single-layered graphene films with a 98% yield were prepared on an 80 nm-Co-coated Cu foil and insensitive to growth temperature and time. More importantly, this type of composite substrate has also been developed to grow AB-stacked bilayers and three-layer graphene with 99% surface coverage and absence of defects. The approach is opening up a new avenue for high-quality graphene production with precise layer control through composite substrate design.

Effect of surface morphology on the electron mobility of epitaxial graphene grown on 0° and 8° Si-terminated 4H-SiC substrates

Graphene with different surface morphologies were fabricated on 8°-off-axis and on-axis 4H-SiC(0001) substrates by high-temperature thermal decompositions. Graphene grown on Si-terminated 8°-off-axis 4H-SiC(0001) shows lower Hall mobility than the counterpart of on-axis SiC substrates. The terrace width is not responsible for the different electron mobility of graphene grown on different substrates, as the terrace width is much larger than the mean free path of the electrons. The electron mobility of graphene remains unchanged with an increasing terrace width on Si-terminated on-axis SiC. Interface scattering and short-range scattering are the main factors affecting the mobility of epitaxial graphene. After the optimization of the growth process, the Hall mobility of the graphene reaches 1770 cm2/V·s at a carrier density of 9.8. × 1012 cm−2. Wafer-size graphene was successfully achieved with an excellent double-layer thickness uniformity of 89.7% on a 3-inch SiC substrate.

A systematic study of atmospheric pressure chemical vapor deposition growth of large-area monolayer graphene.

Graphene has attracted considerable interest as a potential material for future electronics. Although mechanical peel is known to produce high quality graphene flakes, practical applications require continuous graphene layers over a large area. The catalyst-assisted chemical vapor deposition (CVD) is a promising synthetic method to deliver wafer-sized graphene. Here we present a systematic study on the nucleation and growth of crystallized graphene domains in an atmospheric pressure chemical vapor deposition (APCVD) process. Parametric studies show that the mean size of the graphene domains increases with increasing growth temperature and CH4 partial pressure, while the density of domains decreases with increasing growth temperature and is independent of the CH4 partial pressure. Our studies show that nucleation of graphene domains on copper substrate is highly dependent on the initial annealing temperature. A two-step synthetic process with higher initial annealing temperature but lower growth temperature is developed to reduce domain density and achieve high quality full-surface coverage of monolayer graphene films. Electrical transport measurements demonstrate that the resulting graphene exhibits a high carrier mobility of up to 3000 cm2 V-1 s-1 at room temperature.

Direct Formation of Wafer Scale Graphene Thin Layers on Insulating Substrates by Chemical Vapor Deposition

Direct formation of high-quality and wafer scale graphene thin layers on insulating gate dielectrics such as SiO(2) is emergent for graphene electronics using Si-wafer compatible fabrication. Here, we report that in a chemical vapor deposition process the carbon species dissociated on Cu surfaces not only result in graphene layers on top of the catalytic Cu thin films but also diffuse through Cu grain boundaries to the interface between Cu and underlying dielectrics. Optimization of the process parameters leads to a continuous and large-area graphene thin layers directly formed on top of the dielectrics. The bottom-gated transistor characteristics for the graphene films have shown quite comparable carrier mobility compared to the top-layer graphene. The proposed method allows us to achieve wafer-sized graphene on versatile insulating substrates without the need of graphene transfer.

Growth of Wafer Size Graphene on SiC Substrates

Graphene, as strict two-dimensional material, exhibits exceptionally good electronic properties. In this paper, graphene was prepared on SiC substrates at different temperature based on two types of pre-treated surface. The surface morphology was characterized by atomic force microscopy (AFM) and scanning electronic microscopy (SEM). The results on SiC surface pre-treatment showed that chemical mechanical polishing (CMP) was an effective surface treatment method for reproducible and controlled growth of graphene. Images of the Si-surface revealed that the thickness of graphitic layers increased with annealing temperature. Meanwhile, a mesh-like network of wrinkles tended to tent-like features with the increase of temperature. The residual stresses, average crystallite size and number of graphene layers were analyzed by Raman spectroscopy. Little shift of 2D-band indicated the presence of certain stresses. Results among four samples showed that graphene layers grown on MP C-surface substrates had the thickest layers，contained the smallest average crystallite size La and exhibited no stresses. While graphene layers grown on Si-surface under 1600°C built upon compressive stresses, exhibited largest La and least number of graphene layers, indicating perfect quality.

Segregation Growth of Graphene on Cu–Ni Alloy for Precise Layer Control

A facile way to segregate wafer-size graphene with controllable layer number using Cu–Ni binary alloy under vacuum annealing condition is presented here. Increasing atomic percentage of Ni in Cu–Ni alloy was found to segregate thicker uniform graphene. To date, over 95% monolayer and 91% bilayer graphene films have been prepared by only changing atomic percentage of Ni in Cu–Ni alloy, respectively. The synergetic combination of the distinct carbon solubilities of Cu and Ni and the well-known segregation phenomenon is believed to be responsible for the formation of high-quality uniform few layer graphene. Together with the easy detachment from growth substrates, we believe this facile segregation technique will offer a great driving force for graphene research.

Preparation of Single- and Few-Layer Graphene Sheets Using Co Deposition on SiC Substrate

Single- and few-layer graphene sheets were fabricated by selective chemical reactions between Co film and SiC substrate. A rapid cooling process was employed. The number of layers and crystallinity of graphene sheets were controlled by process parameters. The formation mechanism of graphene was highly sensitive to carbon diffusion. Free carbon precipitated and then moved across the product layer that was composed mainly of cobalt-silicides. The graphene layer formed homogeneously on the surface and then transferred to the other substrate. This could provide a method for high-quality fabrication of wafer-sized graphene sheets.

Universal Segregation Growth Approach to Wafer-Size Graphene from Non-Noble Metals

Graphene has been attracting wide interests owing to its excellent electronic, thermal, and mechanical performances. Despite the availability of several production techniques, it is still a great challenge to achieve wafer-size graphene with acceptable uniformity and low cost, which would determine the future of graphene electronics. Here we report a universal segregation growth technique for batch production of high-quality wafer-scale graphene from non-noble metal films. Without any extraneous carbon sources, 4 in. graphene wafers have been obtained from Ni, Co, Cu-Ni alloy, and so forth via thermal annealing with over 82% being 1-3 layers and excellent reproducibility. We demonstrate the first example of monolayer and bilayer graphene wafers using Cu-Ni alloy by combining the distinct segregation behaviors of Cu and Ni. Together with the easy detachment from growth substrates, we believe this facile segregation technique will offer a great driving force for graphene research.

Towards wafer-size graphene layers by atmospheric pressure graphitization of silicon carbide

Graphene, a single monolayer of graphite, has recently attracted considerable interest owing to its novel magneto-transport properties, high carrier mobility and ballistic transport up to room temperature. It has the potential for technological applications as a successor of silicon in the post Moore's law era, as a single-molecule gas sensor, in spintronics, in quantum computing or as a terahertz oscillator. For such applications, uniform ordered growth of graphene on an insulating substrate is necessary. The growth of graphene on insulating silicon carbide (SiC) surfaces by high-temperature annealing in vacuum was previously proposed to open a route for large-scale production of graphene-based devices. However, vacuum decomposition of SiC yields graphene layers with small grains (30-200 nm; refs 14-16). Here, we show that the ex situ graphitization of Si-terminated SiC(0001) in an argon atmosphere of about 1 bar produces monolayer graphene films with much larger domain sizes than previously attainable. Raman spectroscopy and Hall measurements confirm the improved quality of the films thus obtained. High electronic mobilities were found, which reach mu=2,000 cm (2) V(-1) s(-1) at T=27 K. The new growth process introduced here establishes a method for the synthesis of graphene films on a technologically viable basis.