Wafer Scale Systems Research Articles

Experimental Demonstration of Pressure-Driven Flash Boiling for Transient Two-Phase Cooling

This work demonstrates transient cooling for high-heat-flux electronics using pressure-controlled flash boiling. Many advanced electronics packages demand rapid, high-heat flux removal under stringent spatial and temporal constraints such as limited lateral heat spreading area, sharp power delivery transients, and heterogeneous power dissipation among dies. Flash cooling achieved by rapid depressurization of liquid coolant is inherently transient and provides high initial peak cooling that can be used for adaptive cooling demanded by these advanced packages. A coolant loop thermal testbed has been constructed to perform rapid transient thermo-fluid experiments of flash cooling with methanol. This work provides insights into depressurization-based flash incipience, thermodynamic analysis of flash cooling, and the ability to provide transient cooling in two application settings. First, a vapor chamber able to adapt to high initial transients applicable for short-burst applications. Second, a co-designed convective chamber that supports simultaneous power delivery and heat extraction for high-performance wafer-scale systems. A prototype vapor chamber was tested to obtain results for overall cooling and flash incipience experiments. The results demonstrate the efficacy of flash cooling for transient thermal management and highlight directions for further research and necessary data to exploit this technique for future electronics applications.

Silicon-Interconnect Fabric for Fine-Pitch (≤10 μm) Heterogeneous Integration

The apparent saturation of aggressive Moore's law scaling of semiconductor technologies is pushing the boundaries of traditional packaging and integration schemes to accommodate the ever-growing data bandwidth and heterogeneity demands. In this article, we demonstrate the silicon-interconnect fabric (Si-IF) technology as a superior alternative to conventional printed circuit boards (PCBs) to enhance system scaling. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform to assemble and integrate massive wafer-scale systems. In this technology, dielets are closely assembled on the Si-IF at small interdielet spacings ( ≤ 50 μm) using fine-pitch ( ≤ 10 μm) die-to-substrate interconnects allowing for tight integration on a system-level package. To achieve these fine-pitch interconnects, a novel assembly technique using solder-less direct metal-metal [copper-copper (Cu-Cu)] thermal compression bonding was developed. Using this process, sub-10- μm-pitch interconnects with a low specific contact resistance of ≤ 0.7 Ω·μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> 2</sup> and high shear force of 90 N for 4-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> dies were successfully demonstrated. Moreover, these fine-pitch interconnects combined with the small interdie spacing provide a large number of parallel short links ( ≤ 500 μm) with low loss (≤2 dB) for interdielet communication that is comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) protocol at low link latency (<; 20 ps), low energy per bit (≤0.03 pJ/b), and high data rates (up to 10 Gb/s/link), corresponding to an aggregate data bandwidth of up to 8 Tb/s/mm. The benefits of the SuperCHIPS interface are experimentally demonstrated using functional dielet assembly on the Si-IF to show 4- 23× higher data bandwidth, 3- 65× lower latency, and 5- 40× lower energy per bit compared to existing integration schemes.

A Configurable Multi-Rail Power and I/O Pad Applied to Wafer-Scale Systems

We propose in this paper a novel configurable multi-power-rail pad that combines power supply support circuits and a digital input/output (I/O) buffers designed for a wafer-scale system. This wafer-scale platform includes a reconfigurable wafer-scale circuit, the WaferIC, comprising an alignment-insensitive surface that can be configured to interconnect any digital components manually deposited on its surface. The proposed multi-power-rail pad minimizes power losses and heat dissipation within the circuit. The pad that is fed from two distinct voltage sources providing power at 1.8 and 3.3 V has been implemented and tested. This pad has two merged configurable control loops that can select the power source. Merging takes place through shared transistors. This dual supply pad embeds a voltage regulator that achieves a fast response time of 21.1 ns and that can operate over a wide range of configurable regulated output voltage, from 500 mV up to 2.955 V. This regulator is capable of providing a maximum output current of 40 mA while needing only a very small quiescent current of 126 μA. The regulator's power supply noise rejection ranges from -25 down to -40 dB for frequencies ranging from 1 kHz up to 1 MHz. The embedded digital I/O pad shares a common output with the power distribution and can be configured from 0.5 up to 3.3 V for a maximum speed of 250 MHz.

Loop based design for wafer scale systems

This paper presents a loop based design scheme suitable for wafer scale systems and introduces a variant of the basic reconfiguration algorithm. The underlying topology has been extended to a nonplanar graph of vertex degree five. The yield for this system is higher than that of a planar graph of vertex degree six and requires less hardware for its implementation. Several comparisons among various topologies and reconfiguration algorithms are made within the context of percolation models.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Pipelining communications in large VLSI/ULSI systems

A simple and very effective solution to the delay incurred while propagating data through long interconnection wires is presented. Such delays can be found in large VLSI/ULSI or wafer scale systems. The basic idea of the technique relies on the fragmentation of the wires and in reconnecting them with a special device called repeater in order to form a bidirectional pipeline. A method for determining the optimum configuration of the pipeline is presented. It is shown that, even in presence of an appreciable skew in synchronous systems, the technique improves the transmission speed by 150% for 32-byte messages, when a 10 cm 8-bit bus implemented in a 1.2 /spl mu/m CMOS technology is used. The improvement increases for longer messages and for larger skews. It is also shown that the actual transmission time is close (to within a factor of 2) to the theoretical limit that could be achieved with a zero-length wire. A method based on repeaters operating at a multiple of the basic system clock frequency is also proposed. It is shown that this technique may speedup data transfer by an order of magnitude. The extension of the technique to asynchronous self-timed repeaters is also discussed. Finally, a VLSI implementation of the synchronous reconnection device is described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An adaptive message passing environment for water scale systems

An overview of wafer scale systems, including a discussion of yield requirements that could make them viable alternatives for the next generation of computers, is presented. Following this, an architecture necessary in order to fully exploit concurrent processing in an inherently faulty environments such as that envisioned by wafer scale systems is presented. This includes a discussion of exploiting nondeterministic message passing and adaptation for fault and congestion avoidance. The long-term goal of this work is to present a concurrent computer system with emphasis on improving general processing efficiency as opposed to achieving optimal processing upper bounds for specific algorithms.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

VLSI reliability challenges: from device physics to wafer scale systems

The philosophical and practical differences between Japanese and US IC industries in regard to VLSI reliability, as well as recent research topics and new analysis methods such as wafer scale testing, are discussed. It is suggested that a new approach to VLSI reliability is needed in response to the paradigm shift being brought about by simple scaling limitations, increased process complexity and application of VLSI to advanced systems. An example of this shift is the movement from simple failure analysis by sampling the output of a manufacturing line to the building-in-reliability approach. To introduce and expand on the building-in reliability approach in VLSIs, the authors discuss the required deeper physical understanding of such important processes as hot-carrier effects, dielectrics and metallization. >

Laser interconnection techniques for defect avoidance in large-area restructurable silicon systems

Expanding IC sizes beyond the current chip limits for large area/ wafer-scale systems requires the use of circuit redundancy and defect replacement techniques. Aspects of a post-fabrication defect avoidance process using a laser to make low resistance connections and cut lines in 3 and 1·2μm technologies are described.

Wafer-scale integration using restructurable VLSI

Results from a restructurable very large scale integration (RVLSI) program show the viability of using a laser to restructure wafer-scale circuits for customization and defect avoidance. Wafer-scale circuits are built with a standard integrated circuit fabrication process when the diffused-link restructuring device is used. Nine wafer-scale systems that have been built using the RVLSI technique are described. It is shown that the laser interconnection process has high yield and provides the high reliability of monolithic circuitry. The technology is well suited to signal processing systems, which characteristically use many replications of a small number of circuits and often have modest interconnection requirements. >

A reconfiguration algorithm for wafer-scale integration of systolic arrays

A major problem with assembling a large system of cells on a single wafer is that some of the elements are likely to be defective. Hence a practical procedure for integrating wafer scale systems should be fault-tolerant, that is it should have the ability to configure network arounf fault. The paper presents a reconfiguration algorithm for WSI of two dimensional array. Characteristic of the algorithm is minimization of the path lengths and hence the interconnection delays between the cells of the array.