Abstract
An overview of wafer scale systems, including a discussion of yield requirements that could make them viable alternatives for the next generation of computers, is presented. Following this, an architecture necessary in order to fully exploit concurrent processing in an inherently faulty environments such as that envisioned by wafer scale systems is presented. This includes a discussion of exploiting nondeterministic message passing and adaptation for fault and congestion avoidance. The long-term goal of this work is to present a concurrent computer system with emphasis on improving general processing efficiency as opposed to achieving optimal processing upper bounds for specific algorithms.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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