High-speed interconnections using true single-phase clocking

Abstract

Long interconnections in wafer scale systems can severely limit their operating frequency and the speed of data transfers between distant components. One way to significantly improve these parameters consists in converting long wires into synchronous pipelines. For this purpose, a high-speed pipeline stage has been designed using a state-of-the-art circuit design methodology: single-phase clocking. This methodology usually allows one to design faster circuitries with lower transistor counts. Based on SPICE simulations, it is shown that the designed pipeline stage can transfer data at rates above 800 Mbits/s per wire, when a 1.2 /spl mu/m CMOS technology is used. In order to estimate the maximum data rate when such pipeline stages are used in a practical situation, SPICE simulations were also carried out by interconnecting them using 1 cm metallic wire segments. It is shown that, in this case, data transfer rates larger than 300 Mbits/s can be reached.