The influence of clock-gating on NBTI-induced delay degradation

Abstract

This paper presents an analysis of the implications of clock gating techniques on the increase of aging degradations in new node digital circuits. NBTI is the dominant effect that cause long-term performance degradations over time, and circuit operating conditions may increase significantly these degradations, namely with high power-supply voltage values, signals' probability of operation and low operating frequencies. A proprietary tool is used, AgingCalc, to predict performance degradations caused by NBTI effects over time. SPICE simulations show that by reducing signal transitions in pipeline circuits implemented with clock gating techniques, the performance degradation in the critical paths could lead to delay errors captured by the pipeline stages. The solution is to replace specific flip-flops (FF) with performance sensors' FF, that allow predicting the delay error occurrence in the pipeline. Simulation results are presented for five case studies in 65 nm CMOS technology, using Berkeley Predictive Technology Models (PTM).