Performance Sensor for Subthreshold Voltage Operation

Abstract

The low power quest in CMOS integrated circuits is pushing power-supply voltages to enter the subthreshold levels. The drastic power savings obtained in subthreshold voltage operation makes this an important technique to be used in battery-operated devices. However, working at subthreshold power-supply voltages, frequency operation has to be reduced, making Dynamic Voltage and Frequency Scaling (DVFS) methodologies hard to implement. In fact, existing solutions use wide safety margins and DVFS are typically implemented with static and pre-defined steps, both for the supply-voltage or the clock frequency. But changes in VDD and in clock frequency impose additional challenges, as delay faults may arise, especially in nanometer technologies. Moreover, when a PVTA (Process, power-supply Voltage, Temperature and Aging) variation occurs, circuit performance is affected and circuits are more prone to have delay-faults, especially when cumulative degradations pile up. This paper presents an improved version of the Scout Flip-Flop, the Low-power version, a performance Sensor for tolerance and predictive detection of delay-faults in synchronous digital circuits, which now can operate at power-supply subthreshold voltage levels. The sensor is based on a master-slave Flip-Flop (FF), the Scout FF, with built-in sensor functionality to locally identify critical operations, denoted here as in the eminence of an error, a performance error. The novelty of this solution is on the new architecture for sensor functionality, which allows the operation at VDDs’ subthreshold voltage levels. This feature makes Scout FF a unique solution to control DVFS and avoid delay-fault errors, allowing optimizing circuit operation and performance. To accomplish this, two distinct guard-band windows are created: a tolerance window; and a detection window. Simulations using a SPICE tool allowed characterizing the new sensor and flip-flop to work at sub-threshold voltages, and results are presented for a 65 nm CMOS technology, which uses Predictive Technology Models (PTM). The results show that the improved Scout’s version is effective on tolerance and predictive error detection, working at subthreshold voltages.