Wafer-level Testing Research Articles

Micro/nano electro mechanical systems for practical applications

Silicon MEMS as electrostatically levitated rotational gyroscope, 2D optical scanner and wafer level packaged devices as integrated capacitive pressure sensor and MEMS switch are described. MEMS which use non-silicon materials as diamond, PZT, conductive polymer, CNT (carbon nano tube), LTCC with electrical feedthrough, SiC (silicon carbide) and LiNbO3 for multi-probe data storage, multi-column electron beam lithography system, probe card for wafer-level burn-in test, mould for glass press moulding and SAW wireless passive sensor respectively are also described.

Reliability Tradeoffs and Scaling Issues of Read Drain Bias in nor Flash Memory

Drain read disturb (DRD) is becoming an intrinsic reliability concern for NOR flash scaling and multilevel cell operation. There is a tradeoff between reducing this concern via drain voltage reduction and the effect of that reduction on random telegraph signal (RTS) noise and measured charge detrapping for cycled cells. A DRD time-to-error model has been generated, which takes into consideration voltage dependence, read cycling, and Poisson random statistics. This model can be used for wafer-level tests that allow the quantification of the read window budget tradeoff of the drain voltage with DRD, RTS, and charge-detrapping effects. Models for the read drain voltage effect on RTS and charge detrapping are also presented. These models show that RTS increases with reduced drain voltage due to the mobility effect of the increased gate field. Together, the models allow the optimization of read drain voltage for a given product usage model and the wafer-level assessment of process improvements to ensure that products meet the reliability requirements.

MEMS Vertical Probe Cards With Ultra Densely Arrayed Metal Probes for Wafer-Level IC Testing

We have developed a MEMS probe-card technology for wafer-level testing ICs with 1-D line-arrayed or 2-D area-arrayed dense pads layouts. With a novel metal MEMS fabrication technique, an area-arrayed tip matrix is realized with an ultradense tip pitch of 90 mum times196 mum for testing 2-D pad layout, and a 50-mum minimum pitch is also achieved in line-arrayed probe cards for testing line-on-center or line-on-perimeter wafers. By using the anisotropic etching properties of single-crystalline silicon, novel oblique concave cavities are formed as electroplating moulds for the area-arrayed microprobes. With the micromachined cavity moulds, the probes are firstly electroplated in a silicon wafer and further flip-chip packaged onto a low-temperature cofired ceramic board for signal feeding to an automatic testing equipment. The microprobes can be efficiently released using a silicon-loss technique with a lateral underneath etching. The measured material properties of the electroplated nickel and the Sn-Ag solder bump are promising for IC testing applications. Mechanical tests have verified that the microprobes can withstand a 65-mN probing force, while the tip displacement is 25 mum, and can reliably work for more than 100 000 touchdowns. The electric test shows that the probe array can provide a low contact resistance of below 1 Omega, while the current leakage is only 150 pA at 3.3 V for adjacent probes.

Design Optimization of Needle Geometry for Wafer-Level Probing Test

The probing test is a typical quality control method for individual chips on a wafer. With a proper design, the service life of probing needles in the probe card can be sufficiently elongated and hence reduces the testing cost. In this paper, we followed the Taguchi method with the L18(21 times 37) orthogonal array to obtain an optimal geometrical design of the probing needle based on the minimization of the scrub length the probe tip travels during a wafer-level probing test procedure. Geometrical factors of the needle included tip shape, needle diameter, beam length, taper length, knee diameter, shooting angle, tip length, and tip diameter. Importance of theses factors on the scrub length was also ranked.

Wafer-Level Defect Screening for “Big-D/Small-A” Mixed-Signal SoCs

Product cost is a key driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of ldquobig-D/small-Ardquo mixed-signal system-on-chip (SoC) designs. Packaging cost has recently emerged as a major contributor to the product cost for such SoCs. Wafer-level testing can be used to screen defective dies, thereby reducing packaging cost. We propose a new correlation-based signature analysis technique that is especially suitable for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is used to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss, and packaging costs. Experimental results are presented for a typical mixed-signal ldquobig-D/small-Ardquo SoC, which contains a large section of flattened digital logic and several large mixed-signal cores.

Silicon cantilever arrays with by-pass metal through-silicon-via (TSV) tips for micromachined IC testing probe cards

In this paper, an integrated probe card is proposed and developed for wafer-level IC testing. Based on micromachining technology, totally about 26,000 cantilever-tip probes can be formed simultaneously in one 4-in. silicon wafer, with the minimum pitch of 35 μm for adjacent probing tips. The probe card is designed with a novel composite structure that combines both single-crystalline silicon and electroplated metals. In the composite structure, a novel bypass through-silicon-via with a low aspect ratio can be high-yield fabricated for transferring the testing signals from the probing sided (at the wafer bottom side) to the I/O interface (at the front side). The probe card makes full use of the advantages of the single-crystal silicon and the electroplated nickel and copper. Bulk micromachined silicon cantilevers behave uniform probing height and a good elastic deformation property, while the electroplated nickel probing tips promise high hardness and satisfactory electric contact performance with the dies-under-test (DUT). Measurements show that the fabricated cantilever is able to withstand a contact force of 80mN by a tip displacement of 20 μm. The measured contact resistances on metal pads (Al, Cu, and Au) are all below 1 Ω, whereas the maximum current leakage is 64 pA for 3.3 V voltage across two adjacent tips. After a probing reliability test of 100,000 cycles, the cantilever-tip shows no sign of any performance degradation.

Application of a Genetic Algorithm to the Design Optimization of a Multilayer Probe Card for Wafer-Level Testing

The number of input and output pads on high-performance IC devices has increased in recent years, and hence wafer-level testing is conventionally performed using a probe card with a multilayer needle layout. This paper employs ANSYS commercial software and a Genetic Algorithm (GA) to optimize the design parameters of a multilayer needle probe card such that the scrub marks produced by the different needle layers are of approximately equal length. A dummy probe card containing both a conventional multilayer needle layout and the optimized needle layout is then fabricated and used in a series of single-contact probing tests. The results reveal that the scrub marks produced by the optimized needle layout are both shorter and of a more uniform length that those produced by the conventional needle design. For both needle layouts, a lower and more stable contact resistance is obtained as the overdrive distance is increased. Finally, a multicontact probing test is performed to evaluate the effect on the contact resistance of probe tip contamination following repeated surface contacts. The results show that the needles in the optimized layout are less heavily contaminated than those in the conventional layout, and hence the contact resistance is both lower and more stable. As a consequence, the probe card requires cleaning less frequently and hence its service life is improved.

Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs

Wafer-level testing (wafer sort) is used in the semiconductor industry to reduce packaging and test cost. However, a large number of wafer-probe contacts lead to higher yield loss. Therefore, it is desirable that the number of chip pins contacted by tester channels during wafer sort be kept small to reduce the yield loss resulting from improper contacts. Since test time and the number of contacted chip pins are major practical constraints for wafer sort, not all scan-based digital tests can be applied to the die under test. We propose an optimization framework based on mathematical programming (integer linear programming, nonlinear programming, and geometric programming) and fast heuristic methods. This framework addresses test-access mechanism (TAM) optimization and test-length selection for wafer-level testing of core-based digital system-on-chips (SoCs). The objective here is to design a TAM architecture and determine test lengths for the embedded cores such that the overall SoC defect-screening probability at wafer sort is maximized. Defect probabilities for the embedded cores, obtained using statistical yield modeling, are incorporated in the optimization framework. Simulation results are presented for five of the ITC'02 SoC Test benchmarks.

Micro Hysteresis Sensor for Wafer Level Testing of Magnetic Films

To guarantee a successful fabrication of magnetic micro devices, attaining the desired properties of magnetic thin-films is a precondition. This is particularly true for anisotropic magnetic films. This paper presents the development and fabrication of a micro hysteresis sensor chip consisting of two independent sensors oriented perpendicular to each other. Such an approach allows measuring the properties of anisotropic magnetic thin-films along the two desired axes. The paper describes design, fabrication, and evaluation of the micro hysteresis sensor.

Extensive investigations of temperature influence on barrier integrity during reliability testing

Investigation of stress migration phenomena is one of the key aspects to characterize metallization reliability. Typical test methodologies are investigations of resistance shifts at wafer-level or package-level temperature storage tests under a temperature range between 150 °C and 275 °C. During these tests a very limited resistance increase dependent on the test structure is allowed. Most recently we encounter unusual resistance shift at the highest stress temperature which did not yield classical stress voiding detectable by failure analysis. We found changes in barrier integrity explaining the resistance shift by barrier oxidization. This has been verified by specially prepared material as well as extensive failure analysis investigation.

Development of Stretch Solder Interconnections for Wafer Level Packaging

A wafer level packaging technique has been developed with an inherent advantage of good solder joint co-planarity suitable for wafer level testing. A suitable weak metallization scheme has also been established for the detachment process. During the fabrication process, the compliancy of the solder joint is enhanced through stretching to achieve a small shape factor. Thermal cycling reliability of these hourglass-shaped, stretch solder interconnections has been found to be considerably better than that of the conventional spherical-shaped solder bumps.

A MEMS probe card with 2D dense-arrayed ‘hoe’-shaped metal tips

In this paper, we present a novel MEMS probe card with densely area-arrayed microprobes for the wafer-level test of advanced ICs. In a 4 inch silicon wafer, a total of about 110 000 probe tips can be simultaneously fabricated, with a two-dimensional tip pitch of 240 µm × 160 µm. The ‘hoe-shaped’ microprobe structure is composed of one or two planar arms and an up-tilted tip, both of which are high-yield fabricated with metal micromachining techniques including low-stress nickel electroplating. With micromachined cavities, the silicon wafer serves as moulds for the up-tilted metal probes. Then, the microprobes are finally flip-chip packaged to a ceramic board for further connection to automatic testing equipment (ATE). After the probe structures are formed, the silicon wafer is removed completely by using TMAH wet etching, while the probes are freed by silicon laterally etching. The measured spring constants for all the three types of probes agree well with the designed values. As both mechanical anchors and electrical interconnections, the Sn–Ag solder-bumps feature satisfactory properties. The tested contact resistance values for three different thin-film pads on dies under test are always below 0.8 Ω, while the current leakage between two adjacent probes is only about 150 pA under 3.3 V.

Wafer-Level Modular Testing of Core-Based SoCs

Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of core-based system-on-chip (SoC) designs. Packaging has been recognized as a significant contributor to the product cost for such SoCs. To reduce packaging cost and the test cost for packaged chips, wafer-level testing (wafer sort) is used in the semiconductor industry to screen defective dies. However, since test time is a major practical constraint for wafer sort, even more so than for package test, not all the scan-based digital tests can be applied to the die under test. We present an optimal test-length selection technique for wafer-level testing of core-based SoCs. This technique, which is based on a combination of statistical yield modeling and integer linear programming, allows us to determine the number of patterns to use for each embedded core during wafer sort such that the probability of screening defective dies is maximized for a given upper limit on the SoC test time. We also present a heuristic method to handle large next-generation SoC designs. Simulation results are presented for five of the ITC'02 SoC Test benchmarks, and the optimal test-length selection approach is compared with the heuristic method.

Wafer-Level Modular Testing of Core-Based SoCs

Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of core-based system-on-chip (SoC) designs. Packaging has been recognized as a significant contributor to the product cost for such SoCs. To reduce packaging cost and the test cost for packaged chips, wafer-level testing (wafer sort) is used in the semiconductor industry to screen defective dies. However, since test time is a major practical constraint for wafer sort, even more so than for package test, not all the scan-based digital tests can be applied to the die under test. We present an optimal test-length selection technique for wafer-level testing of core-based SoCs. This technique, which is based on a combination of statistical yield modeling and integer linear programming, allows us to determine the number of patterns to use for each embedded core during wafer sort such that the probability of screening defective dies is maximized for a given upper limit on the SoC test time. We also present a heuristic method to handle large next-generation SoC designs. Simulation results are presented for five of the ITC'02 SoC Test benchmarks, and the optimal test-length selection approach is compared with the heuristic method.

Electromigration in ULSI interconnects

The first reported work on electromigration (EM) was presented in 1959, and since then extensive studies on the EM are being conducted theoretically, experimentally and numerically. In this work, the history and the evolution on the studies of EM are presented for both Al and Cu interconnection. Electron wind force was proposed to be the driving force for EM. However, as the interconnect line width shrinks to sub-micrometer level, other driving forces become important and even dominating. As a result, the conventional diffusion path approach for the modeling of EM is inadequate, and the driving force approach is needed. Both approaches are presented in this work. The extensive studies of EM lead to a much better understanding of the physics of EM, and with this understanding, the factors that affect the EM of interconnects, especially at the field operating conditions are identified and presented here. This identification leads to various design and process modifications and inventions in order to face the challenges of high EM reliability for an ever shrinking interconnection. The understanding of EM has also led to a better EM testing methodology in order to accurately assess the EM of an interconnection. Rigorous statistical analysis of EM test data is another key factor for this accurate assessment. In this work, we presented both the wafer level and package EM testing methodologies, and the rigorous data analysis that takes into account of the bimodal distribution of EM test data.

Concept for a Wafer Level Test System for Measuring Magnetic Film Properties

Achieving the specified magnetic properties of magnetic thin- films is a precondition for a successful wafer fabrication of magnetic thin-film devices. In many cases, these films are anisotropic, with two main axes (hard and easy) perpendicular to each other. For a wafer level measurement along these axes, a new test approach is suggested: employing two micro sensors, each one measuring along one of the two desired axes and engaging them alternatively by means of a micro actuator. This paper discusses the suggested approach and presents a design for the micro sensors and the micro actuator.

Reliability assessment of multi-via Cu-damascene structures by wafer-level isothermal electromigration tests

In this paper, the isothermal wafer-level electromigration test method has been used to compare the resistance to electromigration damage of multi-level structures, realized by dual-damascene copper technology with a variable number of vias. “Upstream” and “downstream” structures have been defined, depending on the metal level where the line under test was located, with respect to the metal level where current and voltage taps were drawn. Not unexpectedly, the most critical current path for electromigration has been found in downstream structures, where the electron flow is entering the line under test. Worthy of note, a well defined dependence of the time to failure on the number of vias has been observed for these structures. Activation energy and current-density acceleration coefficient have been extracted and a quantitative relation is proposed to relate the lifetime expectancy to the number of vias.

A robust MEMS probe card with vertical guide for a fine pitch test

A vertically guided MEMS probe card was designed to deflect 50 µm at a force of 1.5 g and achieve less than 50 µm of pad pitch. Based on our experimental results, the measured average contact resistance of a device under test (DUT) was approximately 0.2 Ω at 1.44 g of force and the leakage current between two tips in the distance of one pitch was about 10 pA. In addition, tip planarity was about ±6 µm with x–y alignment errors within ±8 µm. A reliability test showed that the average contact resistance was 0.34 Ω and the probe tip wear was less than 1 µm after the 10 000 timed touchdowns. To be capable of fine pitch probing, a cantilever beam was constructed by dry etching using a positive photoresist. After the cantilever beam was formed by silicon etching using a deep RIE etcher inside a deep-recessed trench, a vertically guided structure was created from the cantilever beam. Furthermore, to make a horizontally stopped structure, the cantilever beam was designed to have a pyramid tip with a width bigger than that of the beam itself. This kind of structure is mechanically stable when the tip is applied with an oblique force. Because the probe card can be guided vertically and horizontally, it can be neither broken nor deformed by any directional force. In that respect, this newly proposed probe card is suitable for wafer-level testing and fine pitch device testing.

A method for mechanical characterization of capacitive devices at wafer level via detecting the pull-in voltages of two test bridges with different lengths

The paper aims at developing a wafer-level testing method to examine Young's modulus and residual stress of structural materials of capacitive micro-devices by detecting the pull-in voltages of micro test beams made of the materials to be tested. We derive a formula that correlates the Young's modulus, residual stress and pull-in voltage of the micro test beams. The analytical model considers the fringing field capacitance, the distributed characteristics of the micro test beams and the electromechanical coupling effect. By the present method, one can extract Young's modulus and residual stress simultaneously by detecting the pull-in voltages of two test beams of different lengths. Three common structural materials used in micro-devices are demonstrated: mono-crystalline silicon, poly-silicon and aluminum. The extracted Young's moduli and residual stresses agree very well with the experimental measurement. The present method is expected to be applicable to the wafer-level testing in MEMS device manufacture and compatible with the wafer-level testing in IC industry since the test and the pickup signals are both electrical.

Wafer-level microelectromechanical system structural material test by electrical signal before pull-in

The letter develops a wafer-level testing method to examine Young’s modulus and residual stress of structural material of capacitive microdevice by measuring the pre-pull-in capacitance variation of the microtest beam made of the material to be tested. The required instrument is only a precision LCR meter. The extracted Young’s moduli and residual stresses of demonstrated samples agree very well with the experimental measurement. The present method is expected to be applicable to the wafer-level testing in microdevice manufacture and compatible with the wafer-level testing in integrated circuit industry, since the test and pickup signals are both electrical.