Wafer-level Testing Research Articles

First results on the final readout chip for the High-Luminosity LHC upgrade of the CMS Inner Tracker

The CMS Readout Chip (CROC) is a 65nm CMOS hybrid pixel readout chip for the High-Luminosity LHC upgrade of the CMS Inner Tracker. The chip has been developed by the CERN RD53 Collaboration in order to withstand radiation doses up to 10MGy and hit rates up to 3GHzcm−2 on the innermost tracking layer. Moreover, it must handle an increased sensor granularity (pixel size of 2500µm2) with respect to current detectors and operate at detection thresholds as low as 1000e. Twenty wafers of the prototype chip (CROCv1) have been produced in 2021. The CROCv1 characterisation and verification campaign has, overall, demonstrated the radiation resistance of the chip and its performance. The production version of the chip (CROCv2) was submitted in October 2023 and the engineering run wafers have been received in January 2024. In this contribution, the first results from CROCv2 wafer-level testing of more than 1900 chips from the engineering run will be outlined.

Wafer-level Adaptive Testing Based on Dual-Predictor Collaborative Decision

Wafer-level Adaptive Testing Based on Dual-Predictor Collaborative Decision

Wafer and chip-level characterization of edge-coupled photonic integrated circuits by cascaded grating couplers and spot-size converters

This study presents an efficient testing process for characterizing silicon photonic ICs. This process utilizes a coupling structure that integrates grating couplers and spot-size converters for efficient testing both at the chip and wafer levels, respectively. By leveraging wafer-level testing to estimate the characteristics of final chip-level devices, we anticipate a reduction in testing costs. To demonstrate the validity of the proposed testing process, we fabricated and measured silicon-on-insulator ring resonator devices on both wafer and chip levels. The results showed good agreement between the two levels of measurement, validating the effectiveness of our proposed testing process.

High-Speed Electro-Optic Plasmonic Modulator for CMOS Non-Contact Wafer-Level Testing

High-Speed Electro-Optic Plasmonic Modulator for CMOS Non-Contact Wafer-Level Testing

Testing and characterisation of the prototype readout chip for the High-LuminosityLHC upgrade of the CMS Inner Tracker

This contribution describes the characterisation and validation campaign of the prototype of the CMS Readout Chip (CROC), a 65 nm CMOS pixel readout ASIC for the CMS Inner Tracker upgrade for High Luminosity LHC. This validation campaign includes tests with single-chip and multi-chip modules, irradiation campaigns, test beams and wafer-level tests. The main results obtained in the testing of the CROC prototype will be outlined. Key improvements and fixes that have been implemented in the final version of the chip before the October 2023 submission will be described.

Demonstration of MHz piezoelectric micromachined ultrasonic transducers array and its potential application for biomedical treatment

In this paper, we successfully developed the 24 × 31 piezoelectric micromachined ultrasound transducers (PMUTs) array with 8 inch complementary metal oxide semiconductor (CMOS) compatible processes. Scandium aluminum nitride (ScxAl1−xN) thin film (x = 20%) was used as the piezoelectric material. The PMUTs array was fabricated on 8 inch cavity silicon-on-insulator wafers with the device silicon layer thickness of only 3 μm and a cavity pitch of 59 μm. The wafer-level electrical test was conducted using inline auto-prober and the yield rate >90% was achieved across the 8 inch wafer. The following acoustic test on our PMUTs array (1.5 mm × 2.0 mm) indicated the transmit sensitivity of 18.4 kPa V−1 @ 10 mm @ 11.6 MHz in oil with −3 dB bandwidth of 2.3 MHz. In order to validate the potential of using PMUTs array for biomedical treatments, subsequent ultrasonic heating experiments were carried out on a silicone block. A temperature rise of 4 °C was achievable in about 50 s. These results demonstrate that the potential of using PMUTs array as a disposable biomedical device in many therapeutic applications, for example, a treatment for dry eye disease.

(Invited) Applications of Electrochemistry Toward Blue/Green and SWIR-Wavelength VCSELs

Unlike the more established edge-emitting lasers (EELs) with a horizontal Fabry-Perot (FB) cavity, VCSELs have a vertical cavity with highly reflective top and bottom mirrors sandwiching the active region. This design enables wafer-level testing, one- and two-dimensional arrayed integration, and scalability for low- and high-power applications. VCSELs are poised to surpass EELs as a more versatile and intelligent option for semiconductor lasers in the future.Currently commercially available VCSELs only cover the red to near-infrared (NIR) range of 700-1100nm, whereas EELs offer products across a wide spectral range. The optimal active regions for blue and short-wavelength infrared (SWIR) spectra are only supported on GaN and InP substrates, respectively. Lattice-matched, epitaxial mirrors compatible with these two substrates remain major challenges. As a solution, we propose the use of electrochemistry to engineer the refractive index of the material. The innovation is based on the recognition that nanoporous (NP) semiconductor layers can be considered a nanocomposite with nanoscale voids of air uniformly dispersed in a single-crystalline semiconductor, thus rendering a unique way to control the effective optical index with a tunability that is typically un-attainable through epitaxy.We have studied the electrochemistry of semiconductors for applications in photonics, beginning with GaN and most recently with InP. In both material systems, we have discovered a selective porosification process based on the doping concentration. Due to the doping selectivity in EC etching, layers with high doping concentration will be converted to low index nanoporous material with an unprecedented tunability in the refractive index depending on the porosity. Meanwhile, the lightly doped layers remain intact. As a result, highly reflective mirrors were fabricated on GaN and InP substrates with wide stopbands. In this talk, we will provide latest updates in the VCSEL performances in the blue/green and long-wavelength region.

Polarization-stable single-mode 795 nm grating-coupled surface-emitting laser for quantum sensing

We demonstrate a polarization-stable and single-mode grating-coupled surface-emitting laser (GCSEL) with high side-mode suppression ratio (SMSR) of ∼40 dB and orthogonal polarization suppression ratio (OPSR) of ∼25 dB around 795 nm. The fabricated devices have low threshold current of ∼4.8 mA and low electrical resistance of 53 Ω at 25 °C. Meanwhile, a low thermal resistance of ∼1 K/mW is achieved, which is comparable with that of the record of ever reported for vertical-cavity surface-emitting lasers (VCSELs). The far-field divergence angle of surface-emitting beam is ∼14.5°x14.7° at an injection current of 12 mA indicating a relatively good beam quality. Our results open what we believe is a new way to produce polarization-stable single-mode surface-emitting lasers with simple fabrication process. While the GCSEL is specifically designed for quantum sensing applications such as atomic clocks, magnetometers, and gyroscope, its performance in terms of low-power consumption, low thermal resistance, good beam qualities, and wafer-level testing are of particular interest for a wide range of applications.

A novel multi-axis pendulum sandwich structure accelerometer

This paper proposes a new scheme of pendulum accelerometer with sandwich structure. In this scheme, the electrical signal on the mass is connected to the wafer surface through glass isolated through-silicon-via (TSV), so that the basic characteristics of the accelerometer can be obtained by wafer-level testing. Compared with the current commercial device process scheme, the packaging and testing cost of the device can be greatly reduced. The glass-in-silicon (GIS) encapsulation caps on both sides of the device are prepared by glass isolated TSV and GIS reflow process. By designing the shape and size of the silicon electrode area and glass area of the GIS caps, the parasitic capacitance between the pendulum structure and the fixed electrode is reduced. Another advantage of using TSV to extract the electrical signal of the mass is that the Z-axis inertial force can be detected when the pendulum structure is placed perpendicular to the direction of gravity acceleration. In addition, electrodes are grown on the side of the split device, and when the pendulum structure is placed parallel to the direction of gravity acceleration, the inertial force of the XY-axis can be detected. The test shows that when the range of the pendulum accelerometer based on this scheme is ±2 g, the noise density of the accelerometer is 42 μg √Hz−1 (X-axis), 40 μg √Hz−1 (Y-axis) and 27 μg √Hz−1 (Z-axis), and the bias instability is 6.6 μg (X-axis), 7.1 μg (Y-axis) and 6.8 μg (Z-axis), reaching the level of commercial devices.

A Novel Evaluation Methodology for the Reliability and Lifetime of 200 mm E-Mode GaN-on-Si Power HEMTs

In this paper, a novel evaluation methodology for the reliability and lifetime of E-mode AlGaN/GaN HEMTs has been proposed. A practical example of reliability evaluation is presented for commercial 100V E-mode GaN-on-Si power HEMTs, which are fabricated on an industrial 200mm Si CMOS compatible technology platform. Firstly, wafer-level reliability test (WLRT), Joint Electron Device Engineering Council (JEDEC) qualification and dynamic high temperature operating life (DHTOL) test of 200mm GaN-on-Si power HEMTs for mass production have been carried out. Secondly, the relationships of WLRT with JEDEC and DHTOL have been found, therefore, a fast evaluation method for the reliability of commercial 100V E-mode GaN-on-Si power devices has been established. Finally, DHTOL and switching accelerated lifetime test (SALT) have been carried out to demonstrate the validity of the fast evaluation method. In summary, it is proved that the novel evaluation methodology can better screen the robust GaN power devices, and greatly simplify the reliability testing flow of commercial 200mm GaN-on-Si power devices for mass production.

Preview the Products on Display at Display Week 2023

Preview the Products on Display at Display Week 2023

Coupling model of electromigration and experimental verification – Part I: Effect of atomic concentration gradient

This paper presented integrated electromigration (EM) studies through experiment, theory, and simulation. First, extensive EM tests were performed using Blech and standard wafer-level electromigration acceleration test (SWEAT)-like structures, which were fabricated on four-inch wafers. Second, a molecular dynamics (MD) simulation-based diffusion-induced strain was incorporated into the existing coupled theory. Third, one-dimensional (1D) governing equations in terms of atomic concentration for un-passivated and passivated configurations were derived for void formation and growth, using a modified Eshelby's solution to consider the effect of passivation. Fourth, a systematic approach was established, including theoretical formulations and experimental methods, to obtain key material properties, i.e., critical atomic concentration and diffusivity. We then determined the material's properties from a specific set of experimental data, using aluminium (Al) as a carrier for demonstration. These properties were then used to predict the time to failure and void growth under various conditions. The theoretical results agreed well with the experimental data. Moreover, we theoretically determined the critical threshold products of current density and conductor length for the un-passivated and passivated configurations, respectively. Both experiment and theory showed that, in the absence of mechanical stress in un-passivated configurations, the atomic self-diffusion, which was opposite to electron wind, was significant in resisting EM development. However, when mechanical stress was present, such as in passivated configurations, stress migration played a dominant role in resisting EM development. Our numerical results showed that the current density exponent n in Black's law remained as 2 in the range of the current density greater than 0.2 MA/cm2 and rapidly approached infinity at a low level of current density.

Coupling model of electromigration and experimental verification – Part II: Impact of thermomigration

This paper presented a comprehensive experimental and simulation study for thermomigration (TM) accompanying electromigration (EM) at elevated current densities. Both Blech and standard wafer-level electromigration acceleration test (SWEAT)-like test structures, with aluminum (Al) as a carrier, were used for testing and analysis. In Part I of our study (Cui et al., 2023a), the experimental and numerical results with the current density of 1 MA/cm2 were presented. We observed that Al stripes with a SWEAT structure did not show damage in the entire length, while Blech structures showed void and hillock formations only at the cathode and anode, respectively. The temperature gradient owing to Joule heating was neglected in our previous simulations, and the predicted results agreed well with the experimental observations. However, we have not theoretically verified the effect of the temperature gradient. In this paper, we first reported the new experimental data under the elevated current densities of 3 and 5 MA/cm2. In both Blech and SWEAT structures, the spreading of voids in the middle region of conductors was observed. Moreover, in Blech structures, voiding in the middle region occurred after a period of time when voids/hillocks were formed at the cathode and anode, while the SWEAT structures did not show damage at the two ends. Next, based on the coupled 3D theory (Cui et al., 2023a), new analytical one-dimensional (1D) solutions were derived for the Blech and SWEAT structures in the un-passivated configuration considering TM. We found that TM played a significant role in the EM development in the middle of conductors under the elevated current density. The numerical results were in excellent agreement with the experimental data with the consideration of TM. We further established new EM failure's threshold criteria for the SWEAT structures in the form of the product of current density and square of conductor length. This is a major departure from the original Blech's theory in which only mechanical stress gradient was considered. We also studied the acceleration factor of the current density exponent and presented an insight into failure mechanisms associated with TM.

Performance characterization and radiation tolerance evaluation of the SSA2 ASIC, the strip sensor readout ASIC of the CMS Outer Tracker at the HL-LHC

This contribution presents the results of the performance characterization and radiation tolerance evaluation of the SSA2 ASIC, the short-strip readout ASIC for the CMS Outer-Tracker PS-module. The ASIC performance is characterised by different temperatures and operating conditions, at the die level as well as at the wafer level. The radiation evaluation comprises Total-Ionising-Dose (TID) tests and Single-Event-Effects (SEEs). Wafer-level testing provided a large dataset to evaluate the production yield. The presented test results are in agreement with the design simulations and are well within the application requirements for operation in the CMS outer-tracker at the HL-LHC.

Wafer-level testing of inverse-designed and adjoint-inspired dual layer Si-SiN vertical grating couplers

Recently, silicon photonics foundries started providing access to new dielectric stacks which can be utilized to reduce optical I/O losses. For example, in a hybrid c-Si/SiN platform, inverse design techniques can be used to create novel dual layer grating coupler (GC) designs which, in simulations, reach state-of-the-art performance. In this paper, we experimentally validate such designs for perfectly vertical single-polarization GCs in the O-band consisting of a single-etch c-Si layer with a patterned SiN overlay, fabricated using a DUV immersion lithography process on wafers. Here, we investigate designs generated by two different design paradigms: inverse design based on the adjoint method and adjoint-inspired design. Using wafer-level testing, we experimentally demonstrate a record low median insertion loss (IL) of (with interquartile range of –) for perfectly vertical coupling in DUV lithography compatible devices which is a improvement over previously demonstrated single-layer, single-etch c-Si GCs.

Wafer-level testing of the readout chip of the CMS Inner Tracker for HL-LHC

The CMS Inner Tracker, in the High Luminosity LHC (HL-LHC) phase, will be instrumented with approximately 13 × 103 CMS Readout Chips (CROCs). This integrated circuit has been developed by the RD53 Collaboration in order to work reliably in the high hit rates and radiation doses of HL-LHC. The CMS Readout Chip includes a novel powering scheme, a very complex digital circuitry, and a low power analogue front-end. The first batch of prototype CROC wafers has been received in the third quarter of 2021 and several wafers have been tested in 2022 with the wafer-level testing (WLT) setup developed at INFN Torino. The WLT data are being used to produce prototype detector modules, to characterise the CROC v1 before the submission of the final version of the chip, and to estimate wafer yields. This paper describes the wafer-level testing apparatus and the major results obtained in the first waferprobing campaign.

Superconducting routing platform for large-scale integration of quantum technologies

To reach large-scale quantum computing, three-dimensional integration of scalable qubit arrays and their control electronics in multi-chip assemblies is promising. Within these assemblies, the use of superconducting interconnections, as routing layers, offers interesting perspectives in terms of (1) thermal management to protect the qubits from control electronics self-heating, (2) passive device performance with significant increase of quality factors and (3) density rise of low and high frequency signals thanks to minimal dispersion. We report on the fabrication, using 200 mm silicon wafer technologies, of a multi-layer routing platform designed for the hybridization of spin qubit and control electronics chips. A routing level couples the qubits and the control circuits through one layer of Al0.995Cu0.005 and superconducting layers of TiN, Nb or NbN, connected between them by W-based vias. Wafer-level parametric tests at 300 K validate the yield of these technologies while low temperature electrical measurements in cryostat are used to extract the superconducting properties of the routing layers. Preliminary low temperature radio-frequency characterizations of superconducting passive elements, embedded in these routing levels, are presented.

Testing station for fast screening of through silicon via-enabled application-specific integrated circuits for hard x-ray imaging detectors

Application-specific integrated circuits (ASICs) are used in space-borne instruments for signal processing and detector readout. The electrical interface of these ASICs to frontend printed circuit boards is commonly accomplished with wire bonds. Through silicon via (TSV) technology has been proposed as an alternative interconnect technique that will reduce assembly complexity of ASIC packaging by replacing wire bonding with flip-chip bonding. TSV technology is advantageous in large detector arrays where TSVs enable close detector tiling on all sides. Wafer-level probe card testing of TSV ASICs is frustrated by solder balls introduced onto the ASIC surface for flip-chip bonding that hamper alignment. Therefore, we developed the ASIC test stand (ATS) to enable rapid screening and characterization of individual ASIC die. We successfully demonstrated ATS operation on ASICs originally developed for CdZnTe detectors on the Nuclear Spectroscopic and Telescope Array (NuSTAR) mission that were later modified with TSVs in a via-last process. We tested both backside blind-TSVs and frontside through-TSVs, with results from internal test pulser measurements that demonstrate performance equal to or exceeding the probe card wafer-level testing data. The ATS can easily be expanded or duplicated to parallelize ASIC screening for large area imaging detectors of future space programs.

Reconfigurable fiber-to-waveguide coupling module enabled by phase-change material incorporated switchable directional couplers

In silicon photonics, grating-assisted fiber-to-waveguide couplers provide out-of-plane coupling to facilitate wafer-level testing; however, their limited bandwidth and efficiency restrict their use in broadband applications. Alternatively, end-fire couplers overcome these constraints but require a dicing process prior usage, which makes them unsuitable for wafer-level testing. To address this trade-off, a reconfigurable fiber-to-waveguide coupling module is proposed and designed to allow for both grating-assisted and end-fire coupling in the same photonic circuit. The proposed module deploys a switchable directional coupler incorporating a thin layer of phase-change material, whose state is initially amorphous to render the coupler activated and hence facilitate grating-assisted coupling for wafer-level testing. The state can be altered into crystalline through a low-temperature annealing process to deactivate the directional coupler, thus facilitating broadband chip-level coupling through end-fire couplers. All the components encompassing conjoined switchable directional couplers as well as the grating and end-fire couplers were individually designed through rigorous simulations. They were subsequently assembled to establish the proposed reconfigurable coupling module, which was simulated and analyzed to validate the selective coupling operation. The proposed module gives rise to a low excess loss below 1.2 dB and a high extinction ratio over 13 dB throughout the C-band, when operating either under grating-assisted or end-fire input. The proposed reconfigurable coupling module is anticipated to be a practical solution for flexibly expediting the inspection of integrated photonic circuits on a wafer scale.

Selection of 8-channel silicon phototransistor arrays for space applications, based on wafer-level radiation and high-temperature storage tests

Selection of 8-channel silicon phototransistor arrays for space applications, based on wafer-level radiation and high-temperature storage tests