Wafer-level Testing Research Articles

Wafer-level testing of inverse-designed and adjoint-inspired vertical grating coupler designs compatible with DUV lithography.

Perfectly vertical grating couplers have various applications in optical I/O such as connector design, coupling to multicore optical fibers and multilayer silicon photonics. However, it is challenging to achieve perfectly vertical coupling without simultaneously increasing reflection. In this paper, we use the adjoint method as well as an adjoint-inspired methodology to design devices that can be fabricated using only a single-etch step in a c-Si 193 nm DUV immersion lithography process, while maintaining good coupling and low reflection. Wafer-level testing of devices fabricated by a pilot line foundry confirms that both design paradigms result in state-of-the-art experimental insertion loss (<2 dB) and bandwidths (∼20 nm) while having only moderate in-band reflection (<-10 dB). Our best design has a (median) 1.82 dB insertion loss and 21.3 nm 1 dB-bandwidth.

Impact of Thermo-Mechanical Stress Due to Probing and Wire Bonding on CUP Devices

Recently, the circuit under pad (CUP) designs are getting very popular because they could save lots of silicon especially for high-density and high-complexity applications. Polysilicon is a material widely used in many electronic device components. When such devices are placed underneath the bond pads, it is highly expected not to show any change in the electrical behavior due to any kind of thermo-mechanical stresses such as probing or wire bonding mainly during the process of packaging. This article presents a detailed investigation of such impacts on a polysilicon resistor placed underneath the bond pads. The standard meander-shaped polysilicon resistor was used as a test vehicle. In this article, different stress-causing factors such as probing insertions, probing temperature, and wire bond materials were investigated in detail. The impact of such thermo-mechanical stresses is simulated using Comsol to understand the stress phenomenon and for qualitative analysis. Then, the wafer-level silicon testing was carried out to quantify the impact of such thermo-mechanical stresses using a standard design of experiments (DOEs). The impact in terms of change in resistance of the polysilicon resistor of two different widths (5 and 0.42 μm) for two different bond pad metal options viz. Middle thickness metal (METMID) (thickness of 880 nm) and thick metal (METTHK) (thickness of 3000 nm) was investigated. The percent change in resistance was observed to be very negligible after multiple probing attempts and probe temperatures. However, after wire bonding, up to ~14% change in resistance was observed when copper was used as the wire bonding material. Nevertheless, this percent change was still well within the reliability specification limit set by Joint Electron Device Engineering Council (JEDEC), which is widely used in the industry. This detailed investigation will help CUP designers choose the correct back end of line (BEOL) metal options and also wire bonding material upfront and accordingly plan their design margins.

Dual-Frequency CMUT Arrays for Multiband Ultrasound Imaging Applications.

Dual-frequency capacitive micromachined ultrasonic transducers (CMUTs) are introduced for multiscale imaging applications, where a single array transducer can be used for both deep low-resolution imaging and shallow high-resolution imaging. These transducers consist of low- and high-frequency membranes interlaced within each subarray element. They are fabricated using a modified sacrificial release process. Successful performance is demonstrated using wafer-level vibrometer testing, as well as acoustic testing on wirebonded dies consisting of arrays of 2- and 9-MHz elements of up to 64 elements for each subarray. The arrays are demonstrated to provide multiscale, multiresolution imaging using wire phantoms and can span frequencies from 2 MHz up to as high as 17 MHz. Peak transmit sensitivities of 27 and 7.5 kPa/V are achieved with the low- and high-frequency subarrays, respectively. At 16-mm imaging depth, lateral spatial resolution achieved is 0.84 and 0.33 mm for low- and high-frequency subarrays, respectively. The signal-to-noise ratio of the low-frequency subarray is significantly higher for deep targets compared to the high-frequency subarray. The array achieves multiband imaging capabilities difficult to achieve with current transducer technologies and may have applications to multipurpose probes and novel contrast agent imaging schemes.

Transient Tap Couplers for Wafer-Level Photonic Testing Based on Optical Phase Change Materials

Transient Tap Couplers for Wafer-Level Photonic Testing Based on Optical Phase Change Materials

Study on Abnormally Accelerated Oxidation of Tungsten Plugs during Tungsten Chemical Mechanical Polishing in Semiconductor Manufacturing

The root cause of the abnormally accelerated oxidation behavior occurring in tungsten (W) chemical mechanical polishing (CMP) has been performed to provide guidance to those developing practical solutions. Abnormal oxidation behavior refers to the case where the surrounding W contact plugs are normal, but oxidation occurs rapidly and abruptly only at a specific contact, causing device failure. For this study, the failure location was determined through a wafer-level probe test of fully processed DRAM device wafers. With this specific location information, a top-down view inspection was performed on the location immediately after CMP to assess the characteristics, and then a wafer-level probe test was conducted to confirm the failure. In this way, the top-down view plug images immediately after CMP and their potential failure were classified. Based on these results, the CMP process step involving abnormal oxidation was determined, as were the conditions needed to cause abnormal oxidation. Potential solutions to abnormal oxidation are presented based on our results.

Deformation Behavior of Various Interconnection Structures Using Fine Pitch Microelectromechanical Systems (MEMS) Vertical Probe.

Recently, fine pitch wafer level packaging (WLP) technologies have drawn a great attention in the semiconductor industries. WLP technology uses various interconnection structures including microbumps and through-silicon-vias (TSVs). To increase yield and reduce cost, there is an increasing demand for wafer level testing. Contact behavior between probe and interconnection structure is a very important factor affecting the reliability and performance of wafer testing. In this study, with a MEMS vertical probe, we performed systematic numerical analysis of the deformation behavior of various interconnection structures, including solder bump, copper (Cu) pillar bump, solder capper Cu bump, and TSV. During probing, the solder ball showed the largest deformation. The Cu pillar bump also exhibited relatively large deformation. The Cu bump began to deform at OD of 10 μm. At OD of 20 μm, bump pillar was compressed, and the height of the bump decreased by 8.3%. The deformation behavior of the solder capped Cu bump was similar to that of the solder ball. At OD of 20 μm, the solder and Cu bumps were largely deformed, and the total height was reduced by 11%. The TSV structure showed the lowest deformation, but exerted the largest stress on the probe. In particular, copper protrusion at the outer edge of the via was observed, and very large shear stress was generated between the via and the silicon oxide layer. In summary, when probing various interconnection structures, the probe stress is less than that when using an aluminum pad. On the other hand, deformation of the structure is a critical issue. In order to minimize damage to the interconnection structure, smaller size probes or less overdrive should be used. This study will provide important guidelines for performing wafer-level testing and minimizing damage of probes and interconnection structures.

Design of New Au–NiCo MEMS Vertical Probe for Fine-Pitch Wafer-Level Probing

As fine-pitch 3D wafer-level packaging becomes more popular in semiconductor industries, wafer-level prebond testing of various interconnect structures has become increasingly challenging. Additionally, improving the current-carrying capacity (CCC) and minimizing damage to the probe and micro-interconnect structures are very important issues in wafer-level testing. In this study, we propose an Au–NiCo MEMS vertical probe with an enhanced CCC to efficiently reduce the damage to the probe and various interconnect structures, including a solder ball, Cu pillar microbump, and TSV. The Au–NiCo probe has an Au layer inside the NiCo and an Au layer outside the surface of the NiCo probe to reduce resistivity and contact stress. The current-carrying capacity, contact stress, and deformation behavior of the probe and various interconnect structures were evaluated using numerical analyses. The Au–NiCo probe had a 150% higher CCC than the conventional NiCo probe. The maximum allowable current capacity of the 5000 µm-long Au–NiCo probe was 750 mA. The Au–NiCo probe exhibited less contact force and stress than the NiCo probe. The Au–NiCo probe also produced less deformation of various interconnect structures. These results indicate that the proposed Au–NiCo probe will be a prospective candidate for advanced wafer-level testing, with better probing efficiency and higher test yield and reliability than the conventional vertical probe.

Improvement of output efficiency of p-face up photonic-crystal surface-emitting lasers.

We optimized the p-side emission device configuration of photonic-crystal surface-emitting laser (PCSEL) to facilitate the easier chip process and wafer level testing as well as the feasibility of lasing at shorter wavelength. Typically, in order to obtain uniformly distributed current for larger emission area of PCSELs, laser output is designed through the n-side window due to the low hole mobility and thin p-side cladding layer. However, the substrate as well as the epi-layers have to be isolated before the test of each single die on the wafer, which compromised the advantage of wafer-level test of surface emitters. On the other hand, for lasers with emission photon energy higher than the bandgap energy of GaAs substrate, the power will be entirely attenuated. In this study, the optimized p-side emission by applying the transparent conduction layer on top of the p side contact layer to enhance the current distribution and breaking the symmetry of conventional circle pattern in a unit cell to boost the output efficiency is investigated. Through this approach, a high efficiency p-side up PCSEL platform with lower fabrication cost is developed, which is also applicable for short wavelength PCSELs.

3D-printed optical probes for wafer-level testing of photonic integrated circuits.

Wafer-level probing of photonic integrated circuits is key to reliable process control and efficient performance assessment in advanced production workflows. In recent years, optical probing of surface-coupled devices such as vertical-cavity lasers, top-illuminated photodiodes, or silicon photonic circuits with surface-emitting grating couplers has seen great progress. In contrast to that, wafer-level probing of edge-emitting devices with hard-to-access vertical facets at the sidewalls of deep-etched dicing trenches still represents a major challenge. In this paper, we address this challenge by introducing a novel concept of optical probes based on 3D-printed freeform coupling elements that fit into deep-etched dicing trenches on the wafer surface. Exploiting the design freedom and the precision of two-photon laser lithography, the coupling elements can be adapted to a wide variety of mode-field sizes. We experimentally demonstrate the viability of the approach by coupling light to edge-emitting waveguides on different integration platforms such as silicon photonics (SiP), silicon nitride (TriPleX), and indium phosphide (InP). Achieving losses down to 1.9 dB per coupling interface, we believe that 3D-printed coupling elements represent a key step towards highly reproducible wafer-level testing of edge-coupled photonic integrated circuits.

A Sub-THz Wireless Power Transfer for Non-Contact Wafer-Level Testing

In this paper, a sub-THz wireless power transfer (WPT) interface for non-contact wafer-level testing is proposed. The on-chip sub-THz couplers, which have been designed and analyzed with 3-D EM simulations, could be integrated into the WPT to transfer power through an air media. By using the sub-THz coils, the WPT occupies an extremely small chip size, which is suitable for future wafer-testing applications. In the best power transfer efficiency (PTE) condition of the WPT, the maximum power delivery is limited to 2.5 mW per channel. However, multi-channel sub-THz WPT could be a good solution to provide enough power for testing purposes while remaining high PTE. Simulated on a standard 28-nm CMOS technology, the proposed eight-channel WPT could provide 20 mW power with the PTE of 16%. The layouts of the eight-channel WPT transmitter and receiver occupy only 0.12 mm2, 0.098 mm2, respectively.

Frequency Induced Stiction for MEMS Accelerometers

With the rising market for inertial MEMS, reliable stiction detection methods at wafer level become increasingly important. This paper describes a new mechanism for producing enhanced stiction results at wafer level testing due to electric stimulation of the electrode fingers of the MEMS devices and provides a new wafer level measurement method to detect critical frequency ranges. Dependent on the architecture of the sensor core the modulation frequency and amplitude have a distinct impact on the stiction results. The effect is studied systematically for two different test device types by variation of the modulation carrier amplitude and frequency. The results are compared to critical modes gained from transient finite element simulations of the sensor cores. Additionally, a mechanical modal analysis has been performed for result verification. The obtained results show a distinct correlation between the resonance frequencies of the electrode fingers and the likelihood of stiction events. [2019-0189]

On-Wafer FinFET-Based EUV/eBeam Detector Arrays for Advanced Lithography Processes

A novel microdetector array (MDA) for monitoring electron beam (eBeam) and extreme ultraviolet (EUV) lithography processes in 5 nm and beyond FinFET technology is first-time presented. This on-wafer detector array consists of high-density sensing cells which are fully compatible with standard FinFET CMOS processes. Fin coupling structures and energy-sensing pads are first applied in an ultrasmall detector for realizing efficient eBeam and EUV photon detection. In advanced lithography process, eBeam or EUV level projected on the wafer can be precisely recorded on the on-wafer MDA without power or batteries. The distributions and variations on the beam intensities collected by MDA can be electrically measured in real time or inline through wafer level test after eBeam or EUV exposures. The proposed MDA is expected to provide real-time feedback for the optimization and stable maintenance of advanced photolithography processed critical to the development nanometer CMOS technologies.

Testing of the sensing element of a capacitive micromechanical accelerometer

Sensing element is one of the main parts of a micromechanical accelerometer. It determines a lot of parameters of the whole device. Its design flow is a complex process including the steps from the analysis of technical and technological requirements to testing the manufactured devices. Testing is one of the most important steps because it allows not only getting the final characteristics of the chip, but also verifying and specifying the mathematical model of the sensing element for future designs. The paper presents the results of micromechanical accelerometer sensing element testing. Special attention is given to the steps of wafer-level testing and testing with an integrated circuit in the accelerometer.

Adjoint-method-inspired grating couplers for CWDM O-band applications.

We have designed a grating coupler on Silicon-on-Insulator (SOI) platform that has sufficient bandwidth to cover the entire CWDM O-band from 1270 nm to 1330 nm. The grating architecture is inspired by adjoint method-based geometry optimization, and then parameterized to accommodate DOE construction for tapeouts at commercial CMOS foundries and wafer-level testing on fiber probe stations. One grating design achieved peak loss of 3.2 dB with 1-dB bandwidth spanning from 1265 nm to 1338 nm in simulations.

Evaluation and Analysis of Temperature-Dependent Dynamic $R_{{{\mathrm{DS}}},{{\mathrm{ON}}}}$ of GaN Power Devices Considering High-Frequency Operation

Commercial enhancement-mode gallium nitride (GaN) HEMTs device is a superior candidate for high-frequency power electronics applications. However, GaN power devices have a unique dynamic ${R}_{{\mathrm{\scriptscriptstyle DS},\mathrm{\scriptscriptstyle ON}}}$ problem which increases the conduction loss of the converter during operation. In this article, the temperature-dependent dynamic ${R}_{{\mathrm{\scriptscriptstyle DS},\mathrm{\scriptscriptstyle ON}}}$ at high frequency is evaluated experimentally for the first time using the double-pulse test (DPT) and multiple-pulse test (MPT) techniques. Different temperature-dependent dynamic ${R}_{{\mathrm{\scriptscriptstyle DS},\mathrm{\scriptscriptstyle ON}}}$ characteristics between the DPT and the MPT at high temperatures are investigated. The significance of the dynamic ${R}_{{\mathrm{\scriptscriptstyle DS},\mathrm{\scriptscriptstyle ON}}}$ ’s temperature dependence is important since GaN devices are typically operating at elevated temperatures. The results suggest that the traditional wafer-level test method using one pulse or two pulses and the MPT without heating consideration or at lower pulse frequency may not be sufficient to evaluate the dynamic ${R}_{\mathrm{\scriptscriptstyle DS},\mathrm{\scriptscriptstyle ON}}$ effect. Combined with high-frequency, high-voltage, and high-current stress, high operating temperatures result in severe ${R}_{\mathrm{\scriptscriptstyle DS},\mathrm{\scriptscriptstyle ON}}$ degradation; hence, there is a diminished return on operating the devices at high temperatures.

A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits

Monolithic 3-D (M3D) integration has the potential to achieve significantly higher device density compared to 3-D integration based on through-silicon vias. We propose a test solution for M3D ICs based on dedicated test layers, which are inserted between functional layers. We evaluate the cost associated with the proposed design-for-test (DfT) solution and compare it with that for a potential DfT solution based on the IEEE Std. P1838. Our results show that the proposed DfT solution is more cost-efficient than the P1838-based DfT solution for a wide range of interlayer via density. We also present a test scheduling and optimization technique for wafer-level testing of M3D ICs. The proposed technique provides test schedules with minimum test time under power consumption and probe pad constraints.

300-mm Monolithic Silicon Photonics Foundry Technology

A competitive 300-mm silicon photonics foundry technology has been developed by GLOBALFOUNDRIES for general availability, which takes advantage of advanced CMOS process technology and provides a manufacturing scale. A state-of-the-art process design kit offers a codesign environment with access to a comprehensive photonics device library along with a monolithically integrated SOI CMOS device library. Advances in automated wafer-level optical test enable statistical photonic device characterization for development, photonic modeling, and manufacturing controls. The key challenges and solutions in developing a manufacturable photonic technology with state-of-the-art performance are described, as well as a roadmap for next generation high-performance monolithic silicon photonics are outlined.

Transferable-Tip Technology for Fine-Pitch Probes and Interconnections

A transferable-tip technology has been developed that has applications for wafer-level fine-pitch probe and electrical test of semiconductor devices. The tips are made by filling a mold made in a (100)-oriented Si substrate wafer, with cavities created by anisotropic etch. The tips are very sharp and planar, with a precise cone angle of 70.5°. The metal tips are then transferred to any suitable substrate, using a solder and release process. The tips, used in a probe head, enable electrical contact to large-area microbump arrays at low force. Test structures were fabricated with as many as 250 000 tips at the 50- $\mu \text{m}$ pitch. This approach also enables test electronics to be incorporated into the probe head. In this way, high-speed functional tests can be performed that minimize difficulties normally encountered in wiring and shielding many high-frequency signals in the probe head and to external test electronics. This probe tip technology also has potential for improved chip-to-chip interconnections that ensure known-good-dies are added to a chip stack. As compared to other probe contact technologies, the transferable-tip approach is potentially low-cost and amenable to new modes of probing, particularly applicable to chip stacks made with 3-D Si integration and heterogeneous integration.

Open-Access 3-μm SOI Waveguide Platform for Dense Photonic Integrated Circuits

This paper gives an overview of the 3-μm silicon-on-insulator (SOI) platform that is openly available from VTT and suitable for the realization of photonic integrated circuits (PICs) for near and mid-infrared applications. Specific benefits of this thick-SOI PIC platform include low optical losses (∼0.1 dB/cm), ultra-dense integration (μm-scale bends), small polarization dependency (down-to-zero birefringence), and ability to tolerate relatively high optical powers (>1 W). Fabrication technology is based on an i-line stepper and 150-mm wafer size. Open access to the waveguide platform is supported by design kits, wafer-level testing, multi-project wafer runs, dedicated R&D runs, and small-to-medium volume manufacturing.

Time Division Multiplexing based Test Access for Stacked ICs

The test cost and complexity of stacked ICs (SICs) are higher than those of 2D-ICs because an SIC is tested at more stages before shipping. The existing test access architectures and their optimization techniques for SICs underutilize the tester-channel frequency because the test data is shifted at low scan-shift frequency due to test power constrain. Moreover, the wafer-level test frequency is constrained by limited probe-pin to pad contact current; however, the package-level test can be performed at a higher frequency yet lower than the tester-channel frequency offered by the testers. Therefore, we present a time-multiplexed test access architecture for SICs that leverages the tester-channel frequency at both the wafer-level and package-level tests. Unlike exiting architectures, the proposed architecture does not require the knowledge of the number of dies to be stacked and the hierarchical tier of each die. The proposed architecture is discussed for SICs based on IEEE standards 1149.1 and 1500. The experimental results with a synthetic SIC, constructed with ITC’02 benchmark SoCs, show significant reduction in the test time. Furthermore, the analyses based on the test frequency limits and the number of stacked dies show that the proposed architecture scales well with increasing frequency limits and the number of stacked dies.