Wafer Inspection Research Articles

Tensile Strength Property with PdCo-Cu Multi-Layer Lamination and Heat Treatment of MEMS Probe for Probe Card

Cantilever wire probe card has limited to transport high-speed signal because of long wire but it is suitable for inspecting high-current and high voltage semiconductor such as wide band gap (WBG) power semiconductors.Superior mechanical property of a probe card wire is in demand because it is respectively used wafer inspection with in and out pad on the top surface of the power semiconductor wafer. Therefore, in this study, tensile specimens of micro electro-mechanical systems (MEMS) probe alternatively layered and electroplated with palladium (Pd)-cobalt (Co) alloy layers and copper (Cu) layers. MEMS probe was also measured tensile strength and elongation with multi-lamination and heat treatment conditions. Additionally, fractography of fracture surface after tensile test were analyzed using a scanning electron microscope (SEM). As the number of PdCo-Cu multi-layer increased, 11, 15 and 21 layered specimens showed higher tensile strength and longer elongation than 5 layered specimens because of the increase of laminated interface of PdCo and Cu. 7 layered specimen after isothermal aging had higher tensile strength and longer elongation than before isothermal aging. In 5, 11, 15 and 21 layered specimens, the fracture surfaces of tensile test specimens without aging treatment showed a ductile-brittle mixed fracture mode. Fracture surfaces of 7-layered specimen before and after isothermal aging showed a ductile-brittle mixed fracture mode.

Non-Destructive Quantification of In-Plane Depth Distribution of Sub-Surface Damage on 4H-SiC Wafers Using Laser Light Scattering

The development of non-destructive quantitative evaluation techniques for the in-plane depth distribution of sub-surface damage (SSD) layer induced by mechanical processing of chemical mechanical polishing (CMP) finished SiC wafers is essential to reduce the occurrence of crystal defects during epitaxial growth. Until now, no wafer inspection method has been able to nondestructively and quantitatively assess the in-plane depth distribution of the SSD. This study investigates the correlation between the scattered light intensity measured nondestructively by the Laser light scattering (LLS) method and the SSD depth estimated by destructive inspection using the Dynamic AGE-ing® method, a sublimation-controlled etching and growth process, to develop a novel non-destructive SSD inspection method. As a result, it was found that there is an exponential relationship between the scattered light intensity by the LLS method on the bare wafer surface and the depth of the SSD layer that contributes to the formation of in-grown stacking faults (IGSF) during subsequent epitaxial growth. The results show that SiC wafer inspection using the novel LLS method, which introduces this relational equation, enables non-destructive and quantitative evaluation of SSD depth and in-plane distribution.

Wafer Edge Metrology and Inspection Technique Using Curved-Edge Diffractive Fringe Pattern Analysis

Abstract This paper introduces a novel wafer-edge quality inspection method based on analysis of curved-edge diffractive fringe patterns, which occur when light is incident and diffracts around the wafer edge. The proposed method aims to identify various defect modes at the wafer edges, including particles, chipping, scratches, thin-film deposition, and hybrid defect cases. The diffraction patterns formed behind the wafer edge are influenced by various factors, including the edge geometry, topography, and the presence of defects. In this study, edge diffractive fringe patterns were obtained from two approaches: (1) a single photodiode collected curved-edge interferometric fringe patterns by scanning the wafer edge and (2) an imaging device coupled with an objective lens captured the fringe image. The first approach allowed the wafer apex characterization, while the second approach enabled simultaneous localization and characterization of wafer quality along two bevels and apex directions. The collected fringe patterns were analyzed by both statistical feature extraction and wavelet transform; corresponding features were also evaluated through logarithm approximation. In sum, both proposed wafer-edge inspection methods can effectively characterize various wafer-edge defect modes. Their potential lies in their applicability to online wafer metrology and inspection applications, thereby contributing to the advancement of wafer manufacturing processes.

Discriminative non-destructive imaging of flip chips based on photoacoustic remote sensing microscopy with layered elasto-optic models

Discriminative internal imaging for different chip layers can pinpoint the location of critical defect in the flip chips, yet existing methods face challenges in in-line imaging to identify defects or structures from the sub-surface within the silicon substrate and their underlying coating. To address these challenges, we develop and verify layered elasto-optic models for photoacoustic remote sensing microscopy (PARS) that distinguish structures from multi-layers within a single device for in-line flip-chip wafer inspection. A finite-difference time-domain algorithm based on transparent source (TS-FDTD) accurately predicts different initial slopes of PARS signals within the silicon-metal and the silicon-air models. The initial slopes of PARS signals are experimentally validated and utilized for discriminative non-destructive imaging of the interdigital electrode chips and silicon cracks within the same region of interest. PARS with layered elasto-optic models and non-contact fast scanning has the potential for in-line detection of defects from various layered structures with different refractive indices, offering an approach for discriminative non-destructive testing (NDT) of flip-chip and layered structures.

Hybrid Semiconductor Wafer Inspection Framework via Autonomous Data Annotation

Abstract In smart manufacturing, semiconductors play an indispensable role in collecting, processing, and analyzing data, ultimately enabling more agile and productive operations. Given the foundational importance of wafers, the purity of a wafer is essential to maintain the integrity of the overall semiconductor fabrication. This study proposes a novel automated visual inspection (AVI) framework for scrutinizing semiconductor wafers from scratch, capable of identifying defective wafers and pinpointing the location of defects through autonomous data annotation. Initially, this proposed methodology leveraged a texture analysis method known as gray-level co-occurrence matrix (GLCM) that categorized wafer images—captured via a stroboscopic imaging system—into distinct scenarios for high- and low-resolution wafer images. GLCM approaches further allowed for a complete separation of low-resolution wafer images into defective and normal wafer images, as well as the extraction of defect images from defective low-resolution wafer images, which were used for training a convolutional neural network (CNN) model. Consequently, the CNN model excelled in localizing defects on defective low-resolution wafer images, achieving an F1 score—the harmonic mean of precision and recall metrics—exceeding 90.1%. In high-resolution wafer images, a background subtraction technique represented defects as clusters of white points. The quantity of these white points determined the defectiveness and pinpointed locations of defects on high-resolution wafer images. Lastly, the CNN implementation further enhanced performance, robustness, and consistency irrespective of variations in the ratio of white point clusters. This technique demonstrated accuracy in localizing defects on high-resolution wafer images, yielding an F1 score greater than 99.3%.

Lens-free reflective topography for high-resolution wafer inspection

The demand for high-resolution and large-area imaging systems for non-destructive wafer inspection has grown owing to the increasing complexity and extremely fine nature of semiconductor processes. Several studies have focused on developing high-resolution imaging systems; however, they were limited by the tradeoff between image resolution and field of view. Hence, computational imaging has arisen as an alternative method to conventional optical imaging, aimed at enhancing the aforementioned parameters. This study proposes a method for improving the resolution and field of view of an image in a lens-less reflection-type system. Our method was verified by computationally restoring the final image from diffraction images measured at various illumination positions using a visible light source. We introduced speckle illumination to expand the numerical aperture of the entire system, simultaneously improving image resolution and field of view. The image reconstruction process was accelerated by employing a convolutional neural network. Using the reconstructed phase images, we implemented high-resolution topography and demonstrated its applicability in wafer surface inspection. Furthermore, we demonstrated an ideal diffraction-limited spatial resolution of 1.7 μm over a field of view of 1.8 × 1.8 mm2 for the topographic imaging of targets with various surface roughness. The proposed approach is suitable for applications that simultaneously require high throughput and resolution, such as wafer-wide integrated metrology, owing to its compact design, cost-effectiveness, and mechanical robustness.

Spot scanning imaging calibration method based on deviation model for wafer inspection

The spot scanning defect detection system has good detection performance for wafer defects. However, due to the existence of system assembly errors, the wafer defect inspection system could not scan following the planned trace, which resulted in distortion of the reconstructed image and had a greater impact on defect feature extraction and accurate defect location. The system deviation calibration and adjustment can further facilitate the accuracy of the system position and image reconstruction. To address this issue, the causes and shapes of imaging distortion were analyzed and simulated, and a simple and effective calibration method based on a scanning deviation model for the spot scanning defect detection system was proposed. First, a scanning deviation model was established following the characteristics of the spot scanning system, and different degrees of reconstructed image distortion were simulated and analyzed as the system deviation changes. Then, an 8-inch wafer with a grid was used as the calibrator and scanned using the developed spot scanning system. Serveral grid corners in the reconstructed image are selected and used as the calibration feature points. The constraint function is constructed using the equidistant features between adjacent grid points, and then the quasi-Newton method is used to optimize the parameters of the function to obtain the best deviation estimation of the spot scanning system. To prove the validity of the estimated deviation parameters, another patterned wafer was scanned and the distortion image was used for reconstruction. The experiment demonstrated that an accurate and distortion-free wafer image can be reconstructed using the calibrated deviation parameters, and the root mean square error of the measured distance between two points of interest was only 0.61 pixels, which proved the effectiveness of the proposed calibration method.

Quantitative shear stress imaging in high throughput in-line Si wafer inspection

Defect inspection methods are basic steps in electronic chip manufacturing and power device production processes in the semiconductor industry. Based on stress induced photoelastic anisotropy, in-line polarized stress imaging (PSI) and quantitative determination of the local shear stress component are possible in single crystalline silicon wafers. Hereafter, such polarization stress images are compared and validated quantitatively with results of finite element simulations based on different 3D elastic models. Uniquely, high resolution at high throughputs is achieved for 300 mm wafer size in the present quantitative stress imaging study.

Balancing the Efficiency and Sensitivity of Defect Inspection of Non-Patterned Wafers with TDI-Based Dark-Field Scattering Microscopy.

In semiconductor manufacturing, defect inspection in non-patterned wafer production lines is essential to ensure high-quality integrated circuits. However, in actual production lines, achieving both high efficiency and high sensitivity at the same time is a significant challenge due to their mutual constraints. To achieve a reasonable trade-off between detection efficiency and sensitivity, this paper integrates the time delay integration (TDI) technology into dark-field microscopy. The TDI image sensor is utilized instead of a photomultiplier tube to realize multi-point simultaneous scanning. Experiments illustrate that the increase in the number of TDI stages and reduction in the column fixed pattern noise effectively improve the signal-to-noise ratio of particle defects without sacrificing the detecting efficiency.

Multiphysics modeling and simulations of laser-sustained plasmas

Laser-sustained plasma (LSP), which can be utilized for a novel radiation light source, has advantages such as high irradiance, broad spectral range, and stable emission, demonstrating significant applications in wafer inspection in the field of the semiconductor industry. This paper revisits the historical development of LSP research and introduces fundamental physical processes in LSP. The mathematical description equations for LSP and methods of calculating plasma parameters are provided, thereby a time-dependent two-dimensional fluid model is established by taking into consideration a laser-thermal-hydrodynamic coupling effect. The propagation of the laser in plasma is investigated based on the established model, and the fundamental processes in LSP, including the initial evolution process, laser energy deposition, steady-state characteristics, and instability, are explored. The effectiveness of the simulation model is confirmed through comparing with the experimental results of high-pressure Xe LSP. The findings indicate that the mode, power, <i>F</i>-number of incident lasers, as well as parameters including components, pressure, and flow velocity of gas, can all affect the steady-state properties of LSPs. Under the identical power and <i>F-</i>number conditions, Gaussian mode laser and annular mode laser both produce LSPs with different shapes and positions. Notably, under the conditions of high-power annular laser incidence, large laser <i>F-</i>number, and high flow velocity, the simulation results reveal temporal and spatial instability in LSP. These simulation results contribute significantly to a more in-depth understanding of the underlying physical mechanisms of the LSP. Furthermore, they provide a theoretical basis for designing the light source system and optimizing the multiple parameters. The influence of laser parameters on LSP properties elucidated in this study not only advances the fundamental understanding of LSP but also offers crucial insights for designing and optimizing the light source systems in various applications, particularly in the field of optical detection for semiconductor wafer inspection.

Oxide-Free SiC-SiC Direct Wafer Bonding and Its Characterization

There are different requirements for the production process and the final product of SiC-SiC wafer bonding. The manufacturing of devices that are sensitive to high temperature processing – due to broadened doping profiles and induced thermal stresses – requires room temperature bonding with high bond strength, while for electrical devices, it is mandatory that the bonding interface with a thin amorphous layer is oxide-free.[1] Reduced complexity of processes is also an important point for the final production. Hence, the goal of this work was to perform and characterize direct bonding of SiC-SiC without any added/deposited bonding layer. This type of bonded SiC wafers can be used for power electronics such as for the fabrication of traction inverter for automotive applications, DC/DC converter, on board charger or charging station.[2]For the wafer bonding processes standard 100 mm 4H SiC wafers were bonded with their Si-terminated faces in order to fabricate oxide-free bonds. The wafer bonding process was performed using the EVG ComBond® system: first the native oxides from both wafer surfaces were removed using an ion beam sputtering process, followed by the transfer of both wafers to the bonding process station operated in ultra-high vacuum (UHV) to significantly retard the oxidation process. Finally, the bonding process was performed at room temperature (RT).The goal of this study was to demonstrate the feasibility of the bonding process and to gain insight on the surface chemistry after activation. The investigations covered three areas: incoming inspection of the original wafer, characterization of activated single wafer and analysis of bonded wafer pairs. The focus was on compositional, chemical, mechanical and morphological analysis of the surfaces and of the bonded interfaces. In the case of single wafers, the focus of the incoming inspection was on whether the wafers fulfill the requirements of wafer bonding, and on the characterization of activated wafers to measure the surface modifications. Atomic force microscopy (AFM), white light interferometry (WLI) and spectroscopic ellipsometry (SE) were used to determine the surface roughness, the wafer topography and the surface layer structure, respectively. All three parameters are essential for successful RT SiC-SiC wafer bonding. The change of the surface chemistry was investigated by angle resolved x-ray photoelectron spectroscopy (AR-XPS). The quality of the bonded wafers and the bonding energy were verified using scanning acoustic microscopy (SAM) measurements (Fig. 1) as well as the Maszara blade test. Furthermore, cross-section transmission electron microscopy (X-TEM) showed a bonding interface with a thin amorphous layer and no noticeable additional oxygen containing layer (Fig. 2). In order to gain quantitative elemental distributions of oxygen and argon, energy dispersive x-ray spectroscopy (EDXS) was applied.The work reported is a demonstration of the capability of the different characterization methods regarding SiC-SiC wafer bonding. Future work will focus on the investigation of the bonded interface characteristics in the function of the bonding process parameters and the annealing conditions.[1] F. Mu, M. Fujino, T. Suga, Y. Takahashi, H. Nakazawa and K. Iguchi, "Wafer bonding of SiC-SiC and SiC-Si by modified surface activated bonding method" 2015 International Conference on Electronics Packaging and iMAPS All Asia Conference (ICEP-IAAC), Kyoto, Japan, 2015, pp. 542-545, doi: 10.1109/ICEP-IAAC.2015.7111073.[2] Tsunenobu Kimoto, "Material science and device physics in SiC technology for high-voltage power devices" Jpn. J. Appl. Phys. 54 040103 (2015), doi: 10.7567/JJAP.54.040103. Figure 1

Soft-Sensing Regression Model: From Sensor to Wafer Metrology Forecasting.

The semiconductor industry is one of the most technology-evolving and capital-intensive market sectors. Effective inspection and metrology are necessary to improve product yield, increase product quality and reduce costs. In recent years, many types of semiconductor manufacturing equipments have been equipped with sensors to facilitate real-time monitoring of the production processes. These production-state and equipment-state sensor data provide an opportunity to practice machine-learning technologies in various domains, such as anomaly/fault detection, maintenance scheduling, quality prediction, etc. In this work, we focus on the soft-sensing regression problem in metrology systems, which uses sensor data collected during wafer processing steps to predict impending inspection measurements that used to be measured in wafer inspection and metrology systems. We proposed a regressor based on Long Short-term Memory network and devised two distinct loss functions for the purpose of the training model. Although the assessment of our prediction errors by engineers is subjective, a novel piece-wise evaluation metric was introduced to evaluate model accuracy in a mathematical way. Our experimental results showcased that the proposed model is capable of achieving both accurate and early prediction across various types of inspections in complicated manufacturing processes.

3D process simulation-assisted device failure analysis with virtual defect injection in IC layout

The development and use of nanotechnology has enabled the creation of submicron electronic devices with unprecedented levels of functionality, speed, and efficiency. While most of the semiconductor industry and its consumers are becoming increasingly dependent on nanoelectronics, these devices are becoming more susceptible to defects and transient faults. Non-Visual Defects (NVD) is a category of semiconductor material and process induced defect that cause electrical failures but are not detected with visual wafer inspection tools (Findlay et al., 2016 [1] and Kim et al., 2009 [10]) or with fault localization tools. Devices with NVD may fail at any stage of their life cycle and may benefit from complex Failure Analysis (FA) investigations including software support to analyze design and diagnostic data. For a higher FA success rate, these investigations can be further supplemented with Technology Computer-Aided Design (TCAD) Process Simulation software to simulate a failure prior to actual physical analysis on limited device samples. In this work, we will showcase an innovative technique for simulating NVD using a 3D process model to pinpoint the exact process step where the defect was introduced. By injecting a new virtual defect layer (which can be autonomously introduced by an FA engineer) in the original device data, we can emulate the failing device. We also present a real-life case study where defect simulation correlates well with the actual Transmission Electron Microscope (TEM) cross-section results.

Development of multi-stage optical variable attenuator system and its control method for wafer inspection system

Development of multi-stage optical variable attenuator system and its control method for wafer inspection system

Detection and identification of particles on silicon wafers based on light scattering and absorption spectroscopy and Machine learning

Modern semiconductor manufacturing technology have a high-quality requirement of the wafers, and therefore the wafer inspection technique becomes increasingly important. During the manufacturing processes, particles can attach on the surface of the wafer which is an important factor of the quality and can even make it impossible to use the wafer. In this research, we introduce a particle detection and identification method based on the scattering and absorption spectra of the particles. A machine learning algorithm was developed to capture the feature of the particles and is able to identify the particle material from the scattering spectrum. Three different particles (Al2O3, SiC, and Si) were used to test this system. The validation accuracy achieves higher than 98% after 5 iterations training. The system was tested by scattering these three particles on the same wafer in different regions without mixing with each other. The results shows that particle Al2O3 and Si were identified with a high accuracy, whereas it is still challenging for the system to correctly label SiC particles. This can be improved by a larger dataset to enhance the generalization ability of the machine learning model.

High Sensitivity Surface Defect Inspection of SiC and SmartSiC<sup>TM</sup> Substrates Using a DUV Laser-Based System

SmartSiCTM technology enables the supply of cost-effective and high-quality substrates to support the manufacturing of Silicon Carbide (SiC) Power Devices and the transition to High Volume Manufacturing (HVM) [1]. As detailed in [2] SmartSiCTM is prepared using a poly-crystalline handle wafer, it combines the benefit from both an optimized high quality epi-ready 4H-SiC layer and an ultra high conductivity handle material. Smart CutTM technology can be extended to SiC 200mm substrates and first SmartSiCTM 200mm sample has been prepared [2].SmartSiCTM substrates crystal quality is inherited by donor wafers [1, 2] and do not require a systematic control, enabling a new defects monitoring strategy, focusing on surface defects.This paper describes how a commercially available DUV inspection system was utilized for high sensitivity, high-throughput inspections of 150 and 200 mm 4H-SiC and SmartSiCTM substrates, for the HVM environment. The KLA Surfscan® SP A2 unpatterned wafer inspection system offers the opportunity to complement other inspection technologies to optimize SiC substrate defect control, with low threshold detection, below 150 nm.

4H-SiC Full Wafer Mapping Image of CMP-Finished Sub-Surface Damage by Laser Light Scattering

Developing an observation method for distributing sub-surface damage (SSD) on large-diameter 4H-SiC bulk wafers formed by mechanical processing can significantly improve the epitaxial and bulk growth processes. This study used a novel laser light scattering (LLS) technique to observe SSD distribution on a 6-inch 4H-SiC (0001) wafer. As a result, scattering intensity distributions similar to the grinding and lap-polishing traces and the shape of the jig used to hold the wafer during polishing were observed on the CMP-finished SiC wafer surface. Since the surface topography of the area was flat by a laser microscopy observation, it is assumed that this is the SSD. This result suggests that LLS can be a wafer inspection method that can observe SSD distribution. In addition, wafer inspection using LLS has demonstrated that it is possible to observe scratches, particles, and macrostep bunching. This method is anticipated to allow further optimization of the mechanical processing and thermal etching process prior to CVD epitaxial growth.

Trainable die-to-database for large field of view e-beam inspection

Extreme ultraviolet lithography has advanced microfabrication of semiconductor devices toward the sub-10-nm generation. In this situation, stochastic defects increase and hence process evaluation requires an entire wafer inspection at high speed. To satisfy this requirement, a large field of view (FoV) inspection with low-resolution enables us to inspect an entire wafer within an acceptable time because the throughput of e-beam inspection depends on imaging resolution. However, low-resolution images are difficult to inspect at high precision using conventional methods because of a smaller photographed defect size and worse signal-to-noise ratio. Moreover, deformation caused by the manufacturing process and larger distortion caused by large FoV result in false detections when we apply die-to-database (D2DB) inspection. To solve these issues, we propose trainable D2DB inspection, which predicts a pixel-value distribution of normal images from a corresponding design layout. The proposed method is robust to low-resolution images because it considers noise and acceptable deformation as variance of the learned distribution. In addition, by introducing a model to predict a misalignment between a design layout and inspection image, trainable D2DB becomes robust to image distortion. Experiments show that trainable D2DB can perform high-precision inspection on images with large noise and image distortion.

Modelling of the backside pattern transfer in magic mirror (Makyoh) imaging

A model of magic-mirror (Makyoh) imaging with the mirror backside relief as the input is described. The mechanical pattern transfer is modelled by a convolution approach while the optical imaging using a nonlinear geometrical optical model, more general than previous approaches. Characteristic features of the imaging is analysed and the linear approximation is examined. Diffraction effects are also treated. Characteristic features for the ancient mirror and applications in semiconductor wafer inspection are discussed.

Simultaneous Absorption and Near‐Infrared Emission Enhancement of Cr3+ Ions in MgGa2O4 Spinel Oxide via Anionic F‐Substitution

AbstractNear‐infrared (NIR) phosphor‐converted light‐emitting diodes (pc‐LEDs) are newly emerging broadband NIR light sources. However, the lack of high‐performance NIR‐emitting materials limits their popularization. Herein, an anionic F‐substitution strategy is presented to regulate the light absorption and emission of MgGa2O4:Cr3+ phosphors. Accordingly, absorption enhancement as well as emission redshift and broadening are achieved for F‐substituted MgGa2O4:Cr3+ (MGOF:Cr3+) phosphors, simultaneously with high efficiency and excellent thermal stability. Upon blue light excitation, the MGOF:0.02Cr3+ phosphor exhibits a broadband NIR emission (650–1200 nm) with a peak wavelength (λmax) of 835 nm and a full width at half maximum of ≈250 nm. Furthermore, MGOF:0.02Cr3+ has a near‐unity internal quantum efficiency and its emission intensity at 150 °C maintains 94% of the initial value. A record external quantum efficiency of 60.6% is further achieved for MGOF:0.08Cr3+ with a redshifted λmax of 870 nm. The Cr3+ local structural alteration with F‐substitution is revealed to account for the outstanding NIR luminescence characteristics of MGOF:Cr3+ in view of systematic structural characterization and spectroscopic analysis. A broadband NIR pc‐LED device with good optical performance is fabricated and its application in semiconductor wafer inspection is demonstrated. This study initiates a new way to design high‐performance NIR phosphors.