Wafer Fab Research Articles

Cooperative multi-agent reinforcement learning for multi-area integrated scheduling in wafer fabs

The existing scheduling methods of wafer fabs focus on single area, achieving local optimisation while failing to realise global optimisation due to neglecting the coordination of multi-area. Therefore, it is necessary to consider the complex opposing relationships between multi-area caused by constraints such as batch processing, re-entrance, and multiple residency times within and between areas to conduct integrated scheduling and shorten the production cycle time. For this issue, this paper proposes a cooperative multi-agent reinforcement learning for multi-area integrated scheduling. Aiming at the dynamic batching and scheduling considering the dynamic arrival lots in multi-area, a multi-agent reinforcement learning algorithm is presented to learn the optimal dynamic batching and scheduling policy firstly. Subsequently, a cooperative multi-agent framework is raised to achieve the global optimisation and coordination of multi-area. Furthermore, an adaptive exploration strategy is constructed to enhance the global exploration capability of the complex solution space caused by residency time constraints and re-entrant property. Moreover, a policy share enhanced Double DQN is employed to improve the generalisation and adaptability of the multi-agent. Finally, the experiments demonstrate that the proposed integrated scheduling method has better comprehensive performance compared to the previous area-separated scheduling methods.

Enhancing Parameters Tuning of Overlay Models with Ridge Regression: Addressing Multicollinearity in High-Dimensional Data

The extreme ultraviolet (EUV) photolithography process is a cornerstone of semiconductor manufacturing and operates under demanding precision standards realized via nanometer-level overlay (OVL) error modeling. This procedure allows the machine to anticipate and correct OVL errors before impacting the wafer, thereby facilitating near-optimal image exposure while simultaneously minimizing the overall OVL error. Such models are usually high dimensional and exhibit rigorous statistical phenomena such as collinearities that play a crucial role in the process of tuning their parameters. Ordinary least squares (OLS) is the most widely used method for parameters tuning of overlay models, but in most cases it fails to compensate for such phenomena. In this paper, we propose the usage of ridge regression, a widely known machine learning (ML) algorithm especially suitable for datasets that exhibit high multicollinearity. The proposed method was applied in perturbed data from a 300 mm wafer fab, and the results show reduced residuals when ridge regression is applied instead of OLS.

Bayesian Optimization for the Vehicle Dwelling Policy in a Semiconductor Wafer Fab

Bayesian Optimization for the Vehicle Dwelling Policy in a Semiconductor Wafer Fab

DeepSEM-Net: Enhancing SEM defect analysis in semiconductor manufacturing with a dual-branch CNN-Transformer architecture

Due to the increasing complexity of modern semiconductor integrated circuit fabrication processes, various defects may occur at each process step, leading to a semiconductor integrated circuit yield loss as well as reliability problems. This study introduces DeepSEM-Net, a novel dual-branch architecture that harmoniously integrates Convolutional Neural Networks (CNN) with Transformers. This innovative approach significantly enhances defect classification and precise segmentation in Scanning Electron Microscope (SEM) defect images, crucial for semiconductor manufacturing processes. DeepSEM-Net consists of a classification branch, which synergizes CNN and Transformers for robust global feature extraction, and a segmentation branch, which incorporates a Pyramid Attention module to meticulously recalibrate and exploit the feature map, thereby enriching the segmentation quality. A semi-supervised defect analysis system based on this model markedly reduces manual inspection efforts and is adept at operating in both simultaneous and sequential classification-segmentation modes. Rigorously tested on a diverse dataset from a real 12-inch wafer fab, DeepSEM-Net not only demonstrated a commendable classification accuracy of 97.25% on a 5-class dataset and a segmentation IoU of 84.40% but also exhibited remarkable resilience against the introduction of new defect classes in an unbalanced dataset. The dual-branch strategy of DeepSEM-Net, thus, significantly elevates the efficiency and reliability of SEM defect image analysis, offering a substantial leap forward in addressing yield loss and ensuring the reliability of semiconductor products.

Scheduling a Single-Arm Two-Cluster Tool With a Process Module Failure Subject to Wafer Residency Time Constraints

Multi-cluster tools are widely adopted in semiconductor manufacturing. When a process module (PM) at a step fails, a multi-cluster tool cannot complete the process recipe of work-in-process wafers and must be forced to enter a closedown process to be empty. To increase the throughput of a wafer fab, it is economically significant to shorten the failure-closedown process. However, due to the wafer residency time constraints, it is highly challenging to respond to a PM failure and find a corresponding optimal schedule. By assuming no parallel PM at a step, this work is the first to study this important issue for scheduling multi-cluster tools. We analyze the task sequences and synchronization conditions for robot activities to avoid deadlock in a shared buffer module. Upon these analyses, for process-dominant multi-cluster tools whose optimal steady-state schedule is known, algorithms are proposed to synthesize the proper sequences for robots in case of PM failures, then, a nonlinear program model is proposed to find an optimal schedule for the corresponding closedown process or decide no feasible solutions. The proposed model can uniformly deal with different scenarios of PM failures. Examples are given to illustrate the application of the proposed method. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Note to Practitioners</i> —In a wafer fab, there are hundreds, even thousands, of cluster tools. It is common that a failure of a processing module happens in a cluster tool. How to intelligently respond to such a random failure in a multi-cluster tool is an important issue in real-world production. This paper studies the scheduling problem of a multi-cluster tool in case of a failure at a PM. For a multi-cluster tool in case of a failure module, the proposed method can significantly reduce the loss of work-in-process wafers and shorten the closedown process.

Subpopulation preference adjective non-dominated sorting genetic algorithm for multi-objective capacity expansion for matured fabs

Capacity expansion strategy consists of fulfilling the demand with capacity portfolio via alternative configurations with long lead time for procurement and installation. Sequential dependent decisions including demand planning and cost structure of capital expenditure shall be taken into consideration for achieving enterprise profitability. Though a number of studies have been done to address related issues, limitations of existing approaches can be traced in part to the lack of a systematic framework in which multiple objectives of related total resource management problems can be considered and integrated. Little research has been done to address the present problem for capacity expansion for matured fabs from the perspective of total resource management. To fill the gaps, this study applies the concept of total resource management to integrate operational strategies and the overall usage of resources. This study develops a capacity expansion model with multiple objectives including minimizing resource costs, maximizing overall return, maximizing revenue, and minimizing capacity risk. Since the formulation of the multi-objectives can be non-linear and the size of the problem is increasing, it is difficult to solve the problem in reasonable time for practical use. A subpopulation preference adjective non-dominated sorting genetic algorithm (SPANS-GA) is developed to solve the decision problem. An empirical study in a leading semiconductor company in Taiwan is conducted for validation. The results have shown practical viability of the developed solution for multi-objective capacity planning for matured wafer fabs for total resource management.

Ranking routes in semiconductor wafer fabs

We develop a method to estimate the quality of processing routes in a wafer fabrication process. Ranking such routes can be useful for identifying the “best” and “worst” routes when making adjustments to recipes. Route categorization is also useful in developing efficient scheduling algorithms. In particular, we propose a method for ranking routes based on count-based metrics such as the number of defects on a wafer. We start with a statistical model to produce a “local” ranking of a tool and then build a “global” ranking via a heuristic procedure. Creating a fully statistical procedure for ranking routes in semiconductor fabrication plants is virtually impossible, given the number of possible routes and the limited data available. Nonetheless, our discussions with working engineers indicate that even approximate rankings are useful for making better operational decisions.

Data-Driven Production Planning Models for Wafer Fabs: An Exploratory Study

Cycle time, which is of order of ten weeks for most products in semiconductor wafer fabrication facilities (wafer fabs), must be explicitly considered in production planning models. Cycle times depend nonlinearly on the resource workload in a wafer fab. Different data-driven (DD) production planning formulations are studied in this paper. Such formulations are based on a set of system states representing the congestion behavior of a wafer fab with work in process (WIP) and resulting output levels. Different WIP-output relations in the DD formulations are investigated. In addition, different methods are proposed to gather representative sets of system states. The DD formulations are compared with the Allocated Clearing Function (ACF) formulation with respect to profit and cost values using simulation models of a scaled-down and a large-sized multiproduct wafer fab, respectively. The simulation results show that some DD variants are able to outperform the ACF formulation under several experimental conditions.

Supply Chain Planning for IC Design House Back-End Production Network With Turnkey Service

Owing to global competition, integrated circuit (IC) design houses are facing challenges in the optimal use of capacity and resources to fulfill customer demands and maximize profit. A hybrid make-to-stock (MTS) and make-to-order (MTO) model is generally used. Wafer procurement is made according to customers’ long-term demand forecast based on MTS. Limited wafer fab resources and back-end capacity are first allocated to on-hand orders and then to forecast demand. In production planning, several factors need to be considered to determine the production quantity and inventory level, such as the material, capacity, substitute, technical constraint, and order tardiness. This study considers a typical multi-stage supply chain network of semiconductor back-end production with turnkey service for IC design houses. The objective is to maximize the total profit with the constraints of equipment capacity, the flexibility of substitutes, and the usage of the turnkey mode. The problem is formulated with a mixed-integer programming model and solved using two novel heuristic algorithms: a product-based decomposition (PD_SCP) with profit-based criteria and a Lagrangian decomposition combined with the product-based decomposition (LD-SCP) method. Using the LD-SCP algorithm takes a long time but results in a great solution. Sensitivity analysis is conducted to investigate the impact of different parameters on production cost and total profit.

Data-driven aggregate modeling of a semiconductor wafer fab to predict WIP levels and cycle time distributions

In complex manufacturing systems, such as a semiconductor wafer fabrication facility (wafer fab), it is important to accurately predict cycle times and work-in-progress (WIP) levels. These key performance indicators are commonly predicted using detailed simulation models; however, the detailed simulation models are computationally expensive and have high development and maintenance costs. In this paper, we propose an aggregate modeling approach, where each work area, i.e., a group of functionally similar workstations, in the wafer fab is aggregated into a single-server queueing system. The parameters of the queueing system can be derived directly from arrival and departure data of that work area. To obtain fab-level predictions, our proposed methodology builds a network of aggregate models, where the network represents the entire fab consisting of different work areas. The viability of this method in practice is demonstrated by applying it to a real-world wafer fab. Experiments show that the proposed model can make accurate predictions, but also provide insights into the limitations of aggregate modeling.

Low-loss silicon nitride photonic ICs for near-infrared wavelength bandwidth.

Low-loss photonic integrated circuits (PICs) are the key elements in future quantum technologies, nonlinear photonics and neural networks. The low-loss photonic circuits technology targeting C-band application is well established across multi-project wafer (MPW) fabs, whereas near-infrared (NIR) PICs suitable for the state-of-the-art single-photon sources are still underdeveloped. Here, we report the labs-scale process optimization and optical characterization of low-loss tunable photonic integrated circuits for single-photon applications. We demonstrate the lowest propagation losses to the date (as low as 0.55 dB/cm at 925 nm wavelength) in single-mode silicon nitride submicron waveguides (220×550 nm). This performance is achieved due to advanced e-beam lithography and inductively coupled plasma reactive ion etching steps which yields waveguides vertical sidewalls with down to 0.85 nm sidewall roughness. These results provide a chip-scale low-loss PIC platform that could be even further improved with high quality SiO2 cladding, chemical-mechanical polishing and multistep annealing for extra-strict single-photon applications.

Scheduling approach for a wafer fab with re-entrant flows and photo dedication constraints

Scheduling approach for a wafer fab with re-entrant flows and photo dedication constraints

Hierarchical Decision-Making for Qualification Management in Wafer Fabs: A Simulation Study

A qualification management problem arising in semiconductor wafer fabrication facilities (wafer fabs) is discussed. The stepper equipment needs to be qualified to process lots that belong to different families. Stepper- and family dependent qualification time windows exist. Time windows can be reinitialized if required and can be extended by on-time processing of lots from qualified families. A hierarchical approach is proposed. The base-level provides a dispatching strategy that takes into account qualification decisions, while the mid-level consists of a mixed integer linear program (MILP) for making qualification decisions. The top-level comprises a linear program (LP) that computes target quantities for the families on the steppers in each period of the planning window taking into account fab-wide objectives. In addition to an LP formulation with conventional capacity constraints, we provide a formulation where clearing functions are used to represent the congestion of the wafer fab. We also discuss how to anticipate the behavior of the mid-level on the top-level. Results of simulation experiments where the hierarchical approach is applied in a rolling horizon manner demonstrate that the LP-based approaches outperform a heuristic to determine the target quantities. Among the LP formulations, the ones with clearing functions perform best. We also demonstrate the value of anticipation. Note to Practitioners—A hierarchical approach is designed to decide when tools in wafer fabs have to be qualified for a certain lot family. Qualification-related decisions are highly relevant because qualifications are costly and take a lot of time. The top-level determines target quantities for each family based on linear programming. The mid-level is formed by a MILP. A dispatching scheme to implement the qualification decisions provides the base-level. The hierarchical approach is assessed in a rolling horizon setting using a simulation model of a 200mm wafer fab. The benefit of the different levels of the hierarchy is demonstrated by simulation experiments.

Job Shop Scheduling in Wafer Fab with Random Job Arrivals using Hybrid Tabu Search

Job Shop Scheduling in Wafer Fab with Random Job Arrivals using Hybrid Tabu Search

Insights into circular material and waste flows from c-Si PV industry

A material flow model for the production of Bifacial Selective Emitter 60-cell p-type Cz PERC (Passivated Emitter and Rear Contacted) glass-backsheet modules with aluminium frame was built. The selected module represents mature technologies in the PV industry and their manufacturing is considered to take place in China in a production cluster with an annual module capacity of 5 GWp. In a first step, data acquisition and validation for wafer, cell and module fabs took place. The data were used to generate the reference system lifecycle inventories (LCI) and extended waste databases for the reference wafers, cells and modules. A set of potential circularity actions, such as the vertical integration of the operations and waste revalorisation strategies, had been proposed and their environmental performance and cost assessed by means of a life cycle assessment (LCA) and a total cost of ownership (TCO). Our results show that 87% of the waste can be reduced and revalorised, this represents a circular flow of raw materials of 18,756 Mg per year from a 5GWp PV module production cluster. Environmental impact reductions of 0.6–2.3% are estimated for different impact categories. We also estimate a cost reduction potential of 2.59% from total module costs.

Deployment of convolutional neural network solutions for image computing in semiconductor manufacturing environment

BackgroundSimilar to many other industries, semiconductor manufacturing is undergoing a digital transformation. The wafer fabs have been highly automated for a few years, and data are everywhere, in high volume, heterogeneous, and not always structured. Data analytics for manufacturing is becoming a key competence to be embedded in the daily lives of wafer fabs engineers. Among the wide variety of data, this paper focuses on images and their classification by convolutional neural networks (CNN), which are illustrated by various use cases in the manufacturing environment.AimPractically, in over a year in a wafer fab, millions of pictures are generated. Most of the time these images are treated directly by metrology and inspection tools, and humans eventually look at these only if a measurement alarm (measurement quality or out-of-specification value) is reported. Is there any interest in reviewing all of them? Technically, images are underused data sources of information because they contain a lot of relevant information that is not captured. The return on investment of inspecting all images is highly questionable if the review needs to be done by humans. When done by the operator, this task is time-consuming and prone to human interpretation, which can lead to variability in the result. The aim of this work is to show that CNNs are perfectly adapted to wafer fabs and can take on this workload in a very efficient way.ApproachSince the middle of the last decade, new tools (software and hardware) have emerged to solve these massive classification needs, including (1) deep learning algorithms and particularly CNNs or region-based CNNs (RCNN), (2) graphical processor unit (GPU) to speed up training time, (3) distributed database to store high volumes of data, and (4) open-source community driven by python eco-systems to support proof of concept build-ups and customized solutions.ResultsThis paper will emphasize the integration of these deep learning solutions into the daily life of semiconductor manufacturing with a focus on transfer learning, which provides high versatility of CNNs/R-CNNs solutions with respect to different use cases.ConclusionsA unique CNN infrastructure has been set up to offer wafer fab engineers a versatile solution adapted to many different kinds of images and use cases to demonstrate that CNN image classification can be smoothly embedded in daily tasks.

Effect of Oxide Thickness by Metallic Residue during Radical Oxidation Using Vertical Batch-Type Furnace Equipment on 300-Mm-Diameter Silicon Substrates

Metallic residues have a detrimental effects on device performance as well as retard gate oxide growth rate to induce unintended thinner oxide layer. In this study, we found that oxide thickness could be subjective to metallic residues on the edge of silicon substrate. Hydrogen-assisted radical oxidation was investigated using vertical batch-type furnace equipment for a 300-mm wafer fab. Radical oxidation has been used to improve gate oxide quality overcoming the disadvantages of conventional wet or dry thermal oxidation for some applications. Since the radical oxidation method reduces dangling bonds and defects in the oxide layer due to activated oxygen radicals, a high-quality oxide film can be formed. It also helps improve reliability due to reduced dependence on the silicon crystal direction of oxidation, enabling uniform membrane deposition of stress-focused corner rounding oxidation. In addition, it has excellent throughput as it is possible to process up to 100 wafers simultaneously. This study has shown that as the number of wafers with metallic residues in the dummy pattern on the edge due to the wafer edge exposure (WEE) difference for each photo step increases in the same batch for radical oxidation, the median thickness has decreased. When the silicon wafer with the metallic residue was included within the same batch of the furnace equipment, the thickness of the oxide layer was reduced by 1.8% compared to when the metallic residue-free silicon wafer was included. The radical oxygen have a tendency to react to tungsten rather than silicon, which reduces the O2 value required to form SiO2 and lowers the thickness, which is due to the difference in electronegativity between silicon and tungsten, 1.9 and 2.36 respectively. The study is expected to improve gate oxide quality by controlling metal residues on the wafer edge or backside during the fab process.

Investment strategy of TSMC based on industry research, financial analysis, and PE valuation

With the rise of 5G technology, new energy vehicles, IOT and other industries in the last two years, the demand for semiconductor chips has reached a peak, but the slow recovery of wafer fab capacity due to the global economic downturn caused by the impact of the COVID-19 has a very important impact on the current chip supply. This paper conducts a study of the business status of TSMC, the leading semiconductor product company, in three dimensions: industry outlook, financial condition and P/E valuation, and gives data-backed recommendations for future investments. The research in this paper shows that the industry has a broad outlook, good operating status, leading net profit margin in the industry, reasonable investment in technology R&amp;D, and is now in a reasonable valuation range, worthy of continued attention and long-term value investment. This paper provides some help and insight for stockholders and institutions to study the analysis and valuation of the semiconductor product segment track.

Salicide Residues Defects Characterization and Reduction in Front-End Pre-Metal Cleaning Process Wafer Fabrication

Wafer fabrication for integrated circuit is one of the most complicated process in semiconductor manufacturing industry. High yield is always the ultimate goal to achieve hence a good defect management is the key to ensure the goal is met. Salicide residue is a major defect wet etching process. The defect is contributing a total of 1% loss in overall wafer fab sort yield, that is an equivalent to USD$ 5 million loss per year. The objective for this research is to identify the root cause and determine the element of the residue defect in the wafer substrate at Salicide Pre-Clean wafer fabrication process. Once this has been achieved, next is to determine a novelty solution to reduce the residue defects and finally validate the effectiveness of the novel solution in reducing the salicide residue defects. An investigation of one factor at the time has been conducted with various experiments including screening all the hardware resources available by using ANOVA studies. The result has concluded that the salicide residue consists of carbon defect is observed after Salicide Pre-Clean step when the standard diluted hydrofluoric acid (dHF) is used by the wet station equipment to clean the product wafers. This study has discovered an innovated solution to minimize the chemical contact on the wafer has resulted in reducing the post clean defects residue by 80% and eliminate 1% of the total product sort yield loss issue.

Feature Selection for Waiting Time Predictions in Semiconductor Wafer Fabs

Based on real operational data from the Robert Bosch GmbH, we investigate influencing features for waiting time estimation of operations in high product-mix / low-volume semiconductor manufacturing fabs. We define waiting time as the elapsed time between completing the previous operation and starting the next one. In addition to well-established features, we introduce novel features to capture the complexity of the manufacturing environment. To the best of our knowledge, we are the first to attempt waiting time estimation in a high product-mix / low-volume semiconductor fab. We present a framework for feature selection which is composed of three steps: First, random forest models are trained for each operation. Second, a permutation feature importance (PFI) for the full set of features for each operation is computed and the performance is statistically evaluated. The optimal subset of features is then chosen by a sequential backward search based on the PFI values. Third, the performance in terms of the coefficient of determination of each optimized model is evaluated by means of the initial performance. We apply the framework to real operational data from the production areas Lithography and Diffusion and conclude that the feature set can be reduced significantly, while the prediction performance remains equal. The novel features are found to be frequently used when estimating waiting times in the investigated use case.