Wafer Edge Research Articles

Improvement of Quality of Thick 4H-SiC Epilayers

The epitaxial growth of ~250 μm thick 4H-SiC epilayers has been demanded for ultra-high-voltage power devices. We have attempted to improve the quality of thick epilayers. At the edge of wafer, stacking faults, epi-crown and interfacial dislocations could be well suppressed by controlling the distribution of growth rate. Investigation of carrier concentration depth profile revealed that increasing surface roughness increased the carrier concentration during thick epitaxial growth. Under N2-doped growth condition, memory effect by accumulation of by-products containing dopant element is also one of the reasons of the carrier concentration increasing during the growth.

Resolving critical dimension drift over time in plasma etching through virtual metrology based wafer-to-wafer control

As semiconductor devices are scaled down to sub-20 nm, process window of plasma etching gets extremely small so that process drift or shift becomes more significant. This study addresses one of typical process drift issues caused by consumable parts erosion over time and provides feasible solution by using virtual metrology (VM) based wafer-to-wafer control. Since erosion of a shower head has center-to-edge area dependency, critical dimensions (CDs) at the wafer center and edge area get reversed over time. That CD trend is successfully estimated on a wafer-to-wafer basis by a partial least square (PLS) model which combines variables from optical emission spectroscopy (OES), VI-probe and equipment state gauges. R2 of the PLS model reaches 0.89 and its prediction performance is confirmed in a mass production line. As a result, the model can be exploited as a VM for wafer-to-wafer control. With the VM, advanced process control (APC) strategy is implemented to solve the CD drift. Three σ of CD across wafer is improved from the range (1.3–2.9 nm) to the range (0.79–1.7 nm). Hopefully, results introduced in this paper will contribute to accelerating implementation of VM based APC strategy in semiconductor industry.

Crystalline damage in silicon wafers and 'rare event' failure introduced by low-energy mechanical impact

We used X-ray diffraction imaging to detect and characterize mechanical damage introduced to 300mm silicon wafers by low impact energy exerted on the wafer edge. Maps of crystalline damage show a correlation between the damage size, the magnitude of the impact energy and the location of the impact point. We demonstrate the existence of crystalline non-visual defects; crystalline defects that appear in the X-Ray diffraction images but not in optical microscopy or scanning electron microscope. We propose a mechanism of crystalline damage formation at low impact energies based on finite element analysis and high-resolution synchrotron white beam transmission X-ray topography. Finally, we propose the concept of 'rare-event' to described relatively low rate of occurrence of wafer failure by fracture within semiconductor manufacturing facilities.

Edge trimming for surface activated dielectric bonded wafers

The impact of the edge trimming process on permanently bonded wafers is described. The edge trimming process is a blade sawing process applied on the Si wafer edge and bevel, removing the fragile edge of the wafer prior to grinding. We investigated two routes for the integration on permanently bonded Si wafers, edge-trim before bonding and edge-trim after bonding. The impact on the subsequent processes for both integration routes is assessed. For the case of edge-trim before bonding, a combination of functional water cleaning such as ozone dissolved in water and ammoniac scrub cleaning shows a significant effect to remove Si residues, enabling void free dielectric bonding. For the case of edge-trim after bonding, utilizing a small grit diamond blade shows no mechanical failures into the dielectric bonding interface. These proposed processes are a very promising for the fabrication of extreme thinned Si without mechanical failure at wafer edge.

New Evaluation Method of Polishing Pad Property for Estimating Edge Roll-Off of Silicon Wafer

With the ever-growing demand for further increase in the integration density of semiconductor devices, silicon wafers as the substrates for most devices are required to be extremely flat. In particular, it is strongly required to suppress edge roll-off, which seriously deteriorates the surface flatness near the wafer edge during polishing process in the final stage of the wafer manufacturing. In this study, we investigate the properties of polishing pads required for decreasing edge roll-off and propose the evaluation method of the properties. Polishing experiments with silicon wafers and evaluation tests for polishing pads reveal that the proposed method can estimate the obtained edge surface flatness.

Analysis of Si Wet Etching Effect on Wafer Edge

We investigated the effect of Si wet etching on the vertical step at wafer edge. We found that the concave-convex shape appeared at the wafer edge after Si etching by the Atomic Force Microscopy analysis. From the liquid simulation and the detailed evaluation of Si etching rate, we revealed that the concave-convex shape was formed by the distribution of the fluid velocity at the wafer edge.

A Study on Profile Control at Wafer Edge By CMP Head Separated Retainer Ring

CMP (chemical mechanical planarization) is a process in which both chemical and mechanical mechanisms act simultaneously to produce the planarized wafer.[1] The wafer edge profile control is the most challenging issue in CMP process. Even much investigation has been tried to eliminate wafer edge profile control, the understanding the origins of the wafer edge profile control during polishing are still needed. Fig1. shows the differences were compared with the single retainer ring and separated retainer ring. Fig2. shows that the separated retainer ring can control wafer edge profile as the result of the simulation. Fig3. is the removed wafer normalize amount as compared with the result of single retainer ring and separated retainer ring. In this study, we examined the better wafer edge profile control was presented by changing the original form of RR(retainer ring) into having two individual pressure controls. Based on experimental and simulation result, it was possible to achieve uniform surface even in the wafer edge area in the case of separated retainer ring by decreasing pad deformation. REFERENCE 1. P. Singer, “Chemical-Mechanical Polishing : A new focus on consumable”, Semiconductor International, pp. 48-53, Feb, 1994. 2. Preston, F. W., “The Theory and Design of Plate Glass Polishing Machine”. Journal of the Society of Glass Technology, 11, p. 214, 1927. 3. Zhao, D., Wang, T., He, Y., and Lu, X., “Effect of Zone Pressure on Wafer Bending and Fluid Lubrication Behavior during Multi-zone CMP Process”, Microelectronic Engineering, 108, p. 33, 2013. 4. Wang, T., Lu, X., Zhao, D., & He, Y., "Contact Stress Non-uniformity of Wafer Surface for Multi-zone Chemical Mechanical Polishing Process." Science China Technological Sciences, 56(8), p.1974, 2013. Figure 1

Minimizing Wafer Surface Charging for Single-Wafer Wet Cleaning for 10 nm and beyond

Wafer charging has become an issue since single-wafer wet clean has been introduced and multiple aspects could be potential root causes. In chemistry and DIW process factors, typical process parameters; flow rate and time were re-evaluated. As an alternative solution, dilute NH4OH could reduce the wafer surface charging. Hardware parts were also investigated and wafer holding chuck-pin material was revealed to become a risk of discharging failure at edge of wafer. Ionizer has been known to discharge wafer surface; however, it is not enough to remove pre-existing charge from post DIW rinsed wafer. Soft X-ray is challenged to remove pre-existing charge and obtained initial positive result.

Particle Removal in Wet Wafer Cleaning Processes

Defects in semiconductor manufacturing that originate from add-on particles can contribute to device yield loss. One possible avenue in removing these particles is a wet wafer cleaning process. Single wafer wet cleaning systems are the current industry standard for defect removal due to their superior ability to control particle re-deposition, especially near wafer edge, as compared to batch cleaning systems. However, our experiments have shown that large micron-sized particles re-deposit during a typical single wafer cleaning process in a model system. These particles were moved and re-deposited primarily during the initial wetting stage. A mechanistic model has been developed to estimate the forces acting on the particles at the three-phase contact line during the wetting stage. The model results show that the forces acting on a particle in the wetting stage are orders of magnitude higher than those in the steady state condition (Fig. 1). Thus, particles are more likely to be moved during the initial wetting step. However, if these moved particles were not transported out of the flow boundary, they could re-deposit and stress produced in steady state flow condition is insufficient to remove them. To further remove smaller particles from wafer surface, a novel particle removal technology based on a polymer solution is reported in this paper. Physical cleaning methods, such as cryogenic aerosol spray, two-phase fluid aerosol spray and megasonic cleaning, have been used in both front-end- and back-end-of-line cleaning processes for a long time. However, all these methods have the risk of damaging fine features on the wafer in today’s advanced process nodes. Thus, there is a need for a damage-free high efficiency particle removal technology. Polymer solutions have long been used in paper making and water treatment industries to aggregate particles either to deposit them on papers or for their removal from water. The same particle aggregation property of polymer solution has been successfully applied to particle removal. High particle removal and no pattern damage have been demonstrated. The particle removal effect is also highly synergistic with SC1 chemistry. By combining these two approaches, particles 25 nm and above can be removed with >90% efficiency. Fig. 1 Schematic of forces acting on defects during wetting stage. FM is motion induced interfacial force, Fdis the hydrodynamic drag force. Figure 1

Impact of Water Edge Absorption on Silicon Oxide Direct Bonding Energy

Direct bonding of silicon and silicon dioxide thin films is now widely used in industry for SOI (Silicon on Insulator) elaboration for instance or in some backside imager manufacturing processes which are now at a stage of mass production processes. Silicon oxide capping layer is very often used as a convenient bonding layer allowing efficient topography planarization with classical CMP (Chemical Mechanical Planarization) process. Thus silicon oxide//silicon oxide direct bonding has been very developed when bonding interface behaviour deserves to be deeply studied. The bonding energy evolution is one of the key parameters and has been widely studied for many years [1,2,3]. Notably, water edge penetration at the bonding interface after the direct bonding was reported recently [4,5]. This work is then focused on the impact of water edge penetration on silicon oxide direct bonding energy values. 200 mm <001> silicon wafers are thermally oxidized at 950 °C under steam atmosphere in order to growth 145 nm of silicon dioxide thin film. After classical RCA cleaning, these wafers are bonded at room temperature and ambient pressure. Just after the bonding, they are diced into 2 cm wide beams and annealed at 300 °C for bonding energy measurement under anhydrous atmosphere [3]. But after the dicing, the atmospheric water can start to penetrate the direct bonding interface. Two times are then considered: t1 is the time between the dicing and the annealing steps and t2 is the time between the annealing and the energy measurement. The bonding energy dependence regarding t1 and t2 is studied. It will be shown that increasing t1 is beneficial for the oxide/oxide bonding energy in contrary to t2 increase. A mechanism for bonding evolution will be proposed to explain these results mainly based on water stress corrosion influence. The annealing atmosphere will also be pointed out to explain some behaviours. Recommendations for storage time and atmosphere as well as for annealing conditions could then be formulated to make bonding energy values at the wafer edge suitable for subsequent device elaborations. REFERENCES [1] G. Kräuter, A. Schumacher, U. Gösele, Sensors and Actuators A: Physical, Vol. 70 (3), 271–275 (1998). [2] F. Fournel, C. Martin-Cocher, V. Larrey, H. Moriceau, F. Rieutord, WaferBond International Conference Brunswick Germany (2015) [3] F. Fournel, L. Continni, C. Morales, J. Da Fonseca, H. Moriceau, F. Rieutord, A. Barthelemy, I. Radu, J. Appl. Phys., 111, 104907 (2012) [4] M. Tedjini, F. Fournel, V. Larrey, F. Rieutord, WaferBond International Conference, Brunswick Germany (2015) [5] M. Tedjini, F. Fournel, H. Moriceau, V. Larrey, D. Landru, O. Kononchuk, S. Tardif, F. Rieutord, Submitted to Journal of Applied Physics.

Agglomeration and long-range edge retraction for Au/Ni bilayer films during thermal annealing

The solid state dewetting of Au/Ni bilayer films from SiO2/Si substrates exhibits both homogeneous and localized dewetting of Ni and long-edge retraction for Au under isothermal annealing condition. The top Au layer retracted up to 1 mm from the edge of the substrate wafer to reduce the energetically unfavored Au/Ni interface. In contrast, Ni dewetted and agglomerated locally due to its limited diffusivity compared to Au. Film morphology and local chemical composition varied significantly across hundreds of micrometers along the direction normal to the retracting edge. The accumulation of Au from long-range edge retraction resulted into the separation of Au and Ni, which are affected by alloying between the two elements. The experimental observations suggest that alloying combined with unequal self-diffusion coefficient for the metal components control the bilayer dewetting process.

Influence of dielectric materials on uniformity of large-area capacitively coupled plasmas for N2/Ar discharges**Project supported by the National Natural Science Foundation of China (Grant Nos. 11335004 and 11405019) and the Important National Science and Technology Specific Project of China (Grant No. 2011ZX02403-001).

The effect of the dielectric ring on the plasma radial uniformity is numerically investigated in the practical 450-mm capacitively coupled plasma reactor by a two-dimensional self-consistent fluid model. The simulations were performed for N2/Ar discharges at the pressure of 300 Pa, and the frequency of 13.56 MHz. In the practical plasma treatment process, the wafer is always surrounded by a dielectric ring, which is less studied. In this paper, the plasma characteristics are systematically investigated by changing the properties of the dielectric ring, i.e., the relative permittivity, the thickness and the length. The results indicate that the plasma parameters strongly depend on the properties of the dielectric ring. As the ratio of the thickness to the relative permittivity of the dielectric ring increases, the electric field at the wafer edge becomes weaker due to the stronger surface charging effect. This gives rise to the lower ion density, flux and N atom density at the wafer edge. Thus the homogeneous plasma density is obtained by selecting optimal dielectric ring relative permittivity and thickness. In addition, we also find that the length of the dielectric ring should be as short as possible to avoid the discontinuity of the dielectric materials, and thus obtain the large area uniform plasma.

High Resolution Sheet Resistance Mapping to Unveil Edge Effects in Industrial IBC Solar Cells

We present Terahertz (THz) transmission measurements with a spatial resolution of down to 10 μm as a new inspection technique for high-resolution sheet resistance (Rsh) measurements, that are well suited to quantify the local Rsh (n-type and p-type regions) of interdigitated back-contact (IBC) structures and to support further optimization of our IBC cells.Using this technique, we investigated the homogeneity of the emitter of our IBC cells. We have greatly improved the Rsh homogeneity of the boron diffusion. Moreover, we compared THz mapping with standard four point probe (4pp) technique. While the 4pp measurement showed a homogeneous mapping, the THz could unveil elevated Rsh near the very edge of the wafer. Higher Rsh of the surface doping can result in higher J0 at the metal contact regions (J0,contact). A local Voc mapping technique was used and it was found that the local Voc at the wafer edge was lowered by 17mV compared to the centre in the most extreme case. We estimate that an improved edge doping could result in a performance gain of at least 0.2% absolute, excluding FF and Jsc benefits.In summary we show that THz mapping is a powerful method in determining inhomogeneities and can aid in the development of diffused-junction IBC solar cells.

Three-point-support method based on position determination of supports and wafers to eliminate gravity-induced deflection of wafers

The flatness measurement of large and thin wafers is affected greatly by gravity. Inverting method is often used to cancel the effect. However, it is required that the positions of the supports and wafers are perfectly symmetric about the inversion axis. In this study a three-point-support method based on position determination of supports and wafers was proposed. The supporting balls and the wafer were placed in arbitrary positions and their positions were obtained by measurement and fed into the FEM model which was developed to calculate the gravity-induced deflection (GID). The methods to acquire the positions of the supports and the wafer were proposed. The position measurement accuracy of the supports was improved greatly by circle fitting to the profile of the supporting ball. Wafer edge point was obtained accurately as the intersection point between the wafer surface line and the edge profile. The method to measure the wafer thickness using only one displacement sensor on the same equipment was presented. The simulation results were verified by experimental results. The centering device for the wafer and the positioning accuracy requirements of the supports are not needed any more. The effect of the positions of the supports and the wafer was reduced to be less than 1μm for a 300mm diameter and 397μm thickness wafer with GID over 140μm. This method could also be used for accurate flatness measurement of other large and thin panels.

Height Uniformity of Micro-Bumps Electroplated on Thin Cu Seed Layers

The emerging 3-dimensional integration relies on components such as through-silicon vias (TSVs) and micro-bumps for vertical stacking [1, 2]. In a typical micro-bump fabrication process, a thin Cu seed layer is coated with a thick layer of photoresist. After exposure and development, cylindrical openings are formed in the photoresist layer. Depending on the application, bumps with single or multiple metal layers, one of them typically being Cu, are deposited. The removal of photoresist is followed by wet etch of the Cu seed, revealing individual micro-bumps. While Cu in the ‘body’ of the micro-bump is deposited electrochemically, the Cu seed layer is typically fabricated using physical vapor deposition (PVD). As the plated Cu etches up to 30% faster than PVD Cu [3], the Cu part of the bumps may suffer from significant radial etch before the seed is removed completely. Figure 1 shows the post-etch SEM image of a micro-bump with Cu-Ni-Sn metal stack. For 4 µm micro-bumps plated on a 200 nm Cu seed, the contact area with the pad will be reduced by about 25 % after seed etch. In order to minimize the ‘under-etch’ of the micro-bumps, the thickness of the Cu seed layer should be reduced. However, the reduction of Cu seed layer thickness leads to the well-known ‘terminal effect’ on the wafer scale [4]. Figure 2 illustrates the cross-section of a plating cell. Due to the potential drop along the radial direction, the plating current density decreases from the wafer edge to the wafer center, resulting in the micro-bump height decreasing from the wafer edge to the wafer center. In this study a quick and cost-effective approach was developed to evaluate the micro-bump height uniformity on wafer level. We studied dependency of micro-bump height uniformity on Cu seed thickness using 300 mm wafers and demonstrated the impact of terminal effect on height variation along the radial direction. By using only the experimentally measured i-ηcurve for the kinetics, numerical simulation of the wafer-scale plating uniformity was significantly simplified. As the proposed methodology required no explicit knowledge of the plating bath composition and only involved coupon-scale experiments, it provided a fast and cost-effective way to evaluate the effectiveness of proprietary plating chemistries with respect to wafer-scale height uniformity of micro-bumps. The usefulness of the proposed approach was supported by the good match between simulation results and the corresponding experimental measurement. Although the simulation capability was only demonstrated for Cu, the same approach can be applied to other layers deposited for micro-bumps. The overall uniformity can be readily calculated through summation of all the layers involved. The simulation program can also be modified to address different profile control approaches such as additional current collectors or anodes with modified geometry.

Quantifying edge and peripheral recombination losses in industrial silicon solar cells

A finite-element model is constructed to represent a silicon solar cell as a vast network of diodes with different saturation current densities, with focus on the definition of three recombination parameters to describe the vicinity of the wafer edges. By simulating the voltage distribution across the cell plane, as well as the cell current-voltage characteristics at different illumination intensities, these peripheral and edge recombination parameters are extracted for various cell types and processes by comparison with corresponding measurement data. It is noted that the monocrystalline silicon PERC cells studied have significantly lower peripheral and second diode edge recombination compared with Al-BSF cells. For the Al-BSF cells studied, there can be ~0.25%-0.6% absolute efficiency gain if the peripheral and edge recombination sources are eliminated.

The Dependence of ECR-CVD Processing Parameters on Deposition Uniformity of Hydrogenated Amorphous Silicon (a-Si:H) Films

The uniformity improvement of high deposition rate in hydrogenated amorphous silicon (a-Si:H) film deposited by electron cyclotron resonance chemical vapor deposition (ECR-CVD) is very essential for a large substrate in PV solar industry. In order to improve the uniformity in depositing thin film in large area, the auxiliary magnetic coils were designed and installed in ECR-CVD to modify the distribution of magnetic field. In addition, the dependence of the other ECR-CVD processing parameters such as resonance position, microwave power, working pressure, and substrate temperature were investigated. The results indicated that more uniform a-Si:H film could be obtained when working pressure was decreased. By using finite element analysis, it was found that location of turbo pump would impact gas flow field and this effect would become more significant at high pressure. Increasing microwave power, increasing horizontal gradient of the magnetic field to the substrate, and forming Cusp magnetic field could enhance ECR-CVD deposition uniformity greatly. However, the plasma location and substrate temperature were not major factors affecting a-Si:H film uniformity in ECR-CVD process. Finally, the optimal and the best 3.8% in uniformity could be achieved in 150mm diameter when the ratio of magnetic field strength at wafer edge to wafer center is 215%, working pressure is 1.5 mtorr, microwave power density is 4W/cm2, and substrate temperature is 180°C.

Enhanced Equipment and New Processes As Enabler for Power Technologies on 300mm Substrates

Transferring power technologies from 200mm silicon substrates to 300mm provides challenges with regard to very special substrate materials, process equipment, and unit processes in addition to those faced by a similar transfer of CD driven commodity products as DRAMS and MPUs. Due to the fact that the current path leads vertically through the substrate and that the final substrate thickness thus determines the figure of merit, the electrical resistance of the device in on-state, ultra-thin wafer handling for wafer backside processing is a further specialty and hence challenge for power semiconductors manufacturing. Current furnace equipment for standard CMOS is capable of processing at temperatures up to 1000°C whereas power technologies require furnace temperatures up to 1200°C which requires hardware adaptation of the tools to comply reliably with these requirements. Some applications furthermore require temperature uniformity within very narrow intervals across the wafers within wafer batches. Wafers with polysilicon films on the wafer backside for impurity gettering are so far only available on 200mm. Such gettering films were deposited and analytically assessed with regard to their gettering capabilities. The extremely high doped wafer substrates for manufacturing power devices are not available yet from the suppliers in both sufficient quality and quantity to start 300mm power semiconductor activities. These substrates have to be manufactured by the semiconductor manufacturer by epitaxial growth. In addition to severe modifications of the epitaxial reactors and the provision of the complete infrastructure that allows running such processes under safe operation conditions unit process development is very challenging. Simultaneous achievements of both supreme uniformity of thick epitaxial layers and of the dopant distribution therein is key to allow perfect pattern generation and transfer and identical electrical device performance respectively all across the wafer until the very wafer edge to take full advantage of the productivity advantage of large diameter wafer processing. All the activities to improve tools and hence processes, were severely supported by equipment and process simulation. To boost productivity additionally to processing 300mm diameter wafers the use of a batch epitaxial tool has been envisioned for the growth of very thick and high resistivity silicon for IGBT applications. All the tool and process learning done on a 5-wafer 200mm batch tool will be used for the design and manufacturing of a similar tool type processing 300mm substrate. For this application high focus was posed on the reduction of sliplines, irregularities in film growth with atomic scale heights, resulting from non-uniform temperature coupling to the substrates in process. While critical CDs in high end products differ by almost an order of magnitude between power semiconductors and standard CD driven CMOS technologies, the tolerated CD uniformities are rather comparable. This finally requires for pattern transfer advanced plasma etch equipment with all the “knobs” to address wafer center and wafer periphery individually regarding etch rate, profile shape, and CD to achieve lowest center-edge non-uniformities. The various tool and process aspects of 300mm power semiconductor manufacturing will be addressed and reviewed in this talk. The work has been performed in the project EPT300, co-funded by grants from Austria, Germany, Italy, The Netherlands and the ENIAC Joint Undertaking.

A study on separating of a silicon wafer with moving laser beam by using thermal stress cleaving technique

This study describes the characteristics of separating a silicon wafer with a moving Nd:YAG laser beam by using a thermal stress cleaving technique. The applied laser energy produces a thermal stress that causes the wafer to split along the irradiation path. The wafer separation is similar to crack extension. In this study, the micro-groove was prepared at the leading edge of the silicon wafer to facilitate the fracture. In order to study the thermal effect in the separating process, the temperature at the laser spot was measured by using a two-color pyrometer with an optical fiber, and the mechanism of crack propagation was observed by using an acoustic emission (AE) sensor. The influence of the micro-groove length and depth was also examined. Thermal stress distribution was calculated using the finite-element method (FEM) by considering the temperature from the experimental result. The result indicates that the wafer separation occurred in two stages, fracture initiation and intermittent crack propagation. A higher temperature resulted in faster fracture initiation and higher repetition of the crack propagation signal. The wave mark on the cleaved surface was consistent with the AE signal. The influences of laser power, temperature and the groove parameters to the fracture initiation, crack propagation and cleaved surface features are explained based on the experimental results, while the thermal stress condition is clarified with FEM analysis.

On the Fabrication of Backside Illuminated Image Sensors: Bonding Oxide, Edge Trimming and CMP Rework Routes

A comprehensive insight to a part of the fabrication process of backside illuminated (BSI) image sensor devices is here discussed. While showing the available process window, special emphasis is given to the key integration developments. The three main areas discussed in this work are bonding using different oxide layers, wafer edge trimming, and CMP rework routes. These processes are relatively new to imager fabrication and hence require mastering each step to achieve the yield requirements of an imager product.