Vth Drift Research Articles

Excellent Reliability Characteristics of Ovonic Threshold Switch Device with Higher‐Temperature Forming Technique

Amorphous chalcogenide‐based ovonic threshold switch (OTS) has significant potential as a selector device in high‐density memory arrays. However, to realize the ideal selector device, OTS still needs to enhance its reliability characteristics such as device uniformity and threshold voltage (Vth) drift. Herein, the effect of elevated temperature forming on the selector characteristics of an OTS device is investigated. The findings indicate that the reliability performance of the device significantly improves when the forming process is conducted at higher temperature. In particular, it shows excellent Vth uniformity (σ = 32 mV) and a notable enhancement in the Vth drift characteristics. Based on trap analysis at cryogenic temperature (77 K), it is confirmed that improved reliability characteristics can be attributed to the stability of the activated trap formed by the HT forming process.

Investigation of dynamic ron stability and hot electrons reliability in normally-off AlGaN/GaN power HEMTs

The current collapse and hot electron effect of 100 V normally-off GaN power HEMTs are investigated. The 100 V GaN-on-Si power HEMTs are fabricated on an industrial 200 mm Si CMOS compatible technology platform. The double pulse test (DPT) and the dynamic high temperature operating life (DHTOL) test are implemented to verify the dynamic on-resistance (dynamic Ron) stability. Wafer level hot electron reliability test is performed to investigate the effect of high electric field and high current on GaN power HEMT. It is proved that the dynamic Ron stability of 100 V GaN power HEMT is qualified (Ron/Rini, static < 1.2) when the drain-source off-state voltage (Vdsoff) is less than 80 V. It is shown that the dynamic Ron degradation of GaN device is recoverable by means of annealing. Hot electrons reliability is dominated by the high electric field at drain edge and the high current which is source injected electrons flowing to the drain. It is demonstrated that the Vth drift and Ron degradation are extraordinary serious under semi on-state stress condition with Vdsoff = 60 V.

New reliability model for power SiC MOSFET technologies under static and dynamic gate stress

This work investigates the Vth degradation of commercial power SiC MOSFET technologies under HTGB and AC stresses with Gate Switching Stress conditions by using relatively accelerated tests whose stressors do not exceed the datasheet specifications. A new model that takes into consideration the variability of the exponent of power-law for Vth drift has been proposed and experimentally verified on planar and trench technologies. The proposed model is useful to estimate accurately the lifetime for any condition or complex mission profile.

Hypothesis to Explain Threshold Drift due to Dynamic Bipolar Gate Stress

We supply a hypothesis that explains threshold voltage (Vth) drift under dynamic bipolar gate stress in SiC-MOSFETs, postulating that ionized donor-like interface traps in the lower half of the bandgap, give rise to an increased internal electric field at each rising edge of a gate voltage pulse. The enhancement of the internal electric field may be viewed as a Vth -reduction, and we devised different experiments to assess this Vth -reduction. Comparing Vth -drift rate using different pulse shapes in dynamic bipolar gate stress tests, we estimated a temporary Vth -reduction in the order of 15 V within 200 ns after the rising edge. Measuring the drain-source current peak 200 ns after the rising edge of a rectangular pulse, gives an estimate for the Vth -reduction of 5.5 V. To resolve this discrepancy, we postulate that in inversion, positive traps are effectively screened such that the impact on the channel is spatially restricted and smaller than the channel length. Channel current will only flow where positive charges induce a percolation path between drain and source, reducing the apparent Vth -reduction in the current based measurement.

Locally formed conductive filaments in an amorphous Ga2Te3 ovonic threshold switching device

Ovonic threshold switching (OTS) selector devices based on chalcogenide materials are promising candidates for addressing the sneak current in high-density cross-point array structures owing to their high selectivity, high endurance, and fast switching speed. However, the OTS mechanism remains controversial and needs to be clarified. In this study, the formation of local conductive filaments (CFs) during threshold switching in an amorphous Ga2Te3 OTS selector device was investigated by electrical measurements and conductive-atomic force microscopy (C-AFM). The amorphous Ga2Te3 OTS selector device requires a forming process before the threshold switching processes. In addition, the off-current density (JOFF) was dependent on the area of the bottom electrode. The difference between the threshold voltage (VTH) and the hold voltage (VH) increased as the applied higher electric field increased. The drift of VTH (VTH drift) depended on the relaxation time and measurement temperature. The requirements of the forming process, area dependence of the JOFF, the difference between the VTH−VH with the applied electric field, and VTH drift are expected to depend on locally formed CFs. In addition, the analysis of the C-AFM results strongly supports the formation of local CFs during threshold switching in an amorphous Ga2Te3 OTS selector device. The understanding of OTS behavior uncovered in this study may provide guidance for improving the characteristics of and designing materials for future applications of OTS selector devices.

Strategies for ultra-fast bit generation of two-terminal threshold switch-based true random number generator using drift-free Ge-doped SiO2 threshold switch device

To achieve fast random bit generation under 50 ns per bit by employing the threshold voltage (Vth) variation of a simple two-terminal threshold switch (TS) device, we have confirmed that Vth drift-free switching characteristics, along with large Vth variation and fast switching speed, are key factors for implementing true random number generator (TRNG) devices. We analyzed the drift-switching characteristics of various TS devices together with our innovative oxide TS device for TRNG applications. Our findings show that stochastic switching is degraded by the Vth drift characteristics of a conventional ovonic threshold switch (OTS) for fast random bit generation. Conversely, the drift-free insulating-to-metal transition (IMT)-based TS device has very tight Vth variation, which is not suitable as a dynamic entropy source for TRNG. However, the Ge-doped SiO2-based TS device operates with drift-free and large Vth variation switching characteristics. Finally, we successfully demonstrated the potential of a Ge:SiO2-based TS device for TRNG application pertaining to fast random bit generation under 50 ns per bit without a complex circuit system.

Gate Oxide Reliability and V&lt;sub&gt;TH&lt;/sub&gt; Stability of Planar SiC MOS Technology

Similar charge to failure distributions with mean values of about 50 C/cm2 were measured for planar SiC MOSFETs and MOS capacitors. Fast occurring and saturating negative flatband and threshold voltage drops were found in time resolved 1 second long pulsed gate current stress with IG=1 mA/cm2 at T=150 °C. No substantial difference in VTH drift rate with VGS=28 V at T=150 °C was found after about 10 s recovery period for IG stressed devices compared with unstressed devices. Additionally, IG stressed and unstressed devices did not differ in final VTH shift at T=25 °C after VGS=28 V stress (during 3 hrs or 31 hrs). More gate oxide reliability characterization is important to determine if 1 mA/cm2 pulsed gate current stress creates any permanent changes to the SiC MOSFET device behaviour. Additionally, parametric shifts in VTH and RDSon was examined after long-term AC gate bias stress by a gate driver switching between-8V and 20V for four different commercially available SiC MOSFETs.

P‐13.3: The Analysis and Improvement of Dim Dark Line Caused By Vth Drift in AMOLED Full Contact Test

In this paper we investigated the dim dark line in AMOLED full contact test. The influence of EL aging and Vth drift were analyzed and compared, and the conclusion that Vth drift was the main reason which caused the dim dark line was achived. We also provided a solution that connecting the ESD ring to the ESD line in low voltage instead of connecting it to the VDD line in high voltage, and the dim dark line was eliminated effectively.

Ovonic threshold switching in polycrystalline zinc telluride thin films deposited by RF sputtering

Chalcogenide materials of the amorphous phase with low band gaps were reported to show Ovonic threshold switching (OTS), making them suitable for selection devices in cross-point memory arrays. Herein, we report that ZnTe films with polycrystalline structures show OTS behavior. Nearly stoichiometric ZnTe thin films were deposited by an RF sputtering method. X-ray diffraction analysis indicated that the films were polycrystalline. The optical band gaps of the ZnTe films were estimated as 2.2 eV from UV–visible spectroscopy transmittance measurements. Photoluminescence measurements indicated the existence of deep-level defects in the ZnTe thin films. Although these ZnTe films have a polycrystalline structure with a relatively high band gap, I–V profiles show OTS characteristics, with a selectivity of over 104, fast threshold switching time in the sub-10 ns scale, and thermal stability up to 400 °C. ZnTe also shows switching endurance for more than 109 cycles without Vth drift, maintaining its selectivity of 104. Thus, we improved the threshold switching characteristics by using a wide band-gap and polycrystalline-structured ZnTe-based chalcogenide material. Post-annealing experiments indicated that the thermal budget of the ZnTe thin film was sufficient for stacked cross-point array structures, thereby overcoming a previous limitation of chalcogenide switching materials. This material is promising for application in high-density cross-point memory arrays as the selection device.

ALD TiOx as a top-gate dielectric and passivation layer for InGaZnO115 ISFETs

The suitability of atomic layer deposited (ALD) titanium oxide (TiOx) as a top gate dielectric and passivation layer for indium gallium zinc oxide (InGaZnO115) ion sensitive field effect transistors (ISFETs) is investigated. TiOx is an attractive barrier material, but reports of its use for InGaZnO thin film transistor (TFT) passivation have been conflicting thus far. In this work, it is found that the passivated TFT’s behavior depends on the TiOx deposition temperature, affecting critical device characteristics such as threshold voltage, field-effect mobility and sub-threshold swing. An O2 annealing step is required to recover TFT performance post passivation. It is also observed that the positive bias stress response of the passivated TFTs improves compared the original bare device. Secondary ion mass spectroscopy excludes the effects of hydrogen doping and inter-diffusion as sources of the temperature-dependent performance change, therefore indicating that oxygen gettering induced by TiOx passivation is the likely source of oxygen vacancies and, consequently, carriers in the InGaZnO film. It is also shown that potentiometric sensing using ALD TiOx exhibits a near Nernstian response to pH change, as well as minimizes VTH drift in TiOx passivated InGaZnO TFTs immersed in an acidic liquid. These results add to the understanding of InGaZnO passivation effects and underscore the potential for low-temperature fabricated InGaZnO ISFETs to be used as high-performance mobile chemical sensors.

Time Resolved Gate Oxide Stress of 4H-SiC Planar MOSFETs and NMOS Capacitors

Lateral SiC MOSFETs and NMOS capacitors were fabricated and electrically evaluated for channel mobility, DIT and gate oxide breakdown. Time resolved measurements of VTH and VFB drift during gate bias stress were performed resulting in logarithmic time dependence for moderate stress time and temperature. Gate bias stress was also carried out during 20 hours at temperatures up to 225 C. Stress times resulting in a VTH shift of 500 mV were determined and an activation energy EA=0.86 eV was extracted for the VTH drift.

Analysis of threshold voltage instability in AlGaN/GaN MISHEMTs by forward gate voltage stress pulses

We report on the investigation of the Vth drift behaviour of AlGaN/GaN MISHEMTs upon forward gate voltage stress in dependence of stress bias and stress time. The pulsed measurements allow for the evaluation of the operational regime for optimum device efficiency. We compared the effect of two different high‐κ gate dielectric materials with similar equivalent oxide thickness ϵ0ϵr/thigh‐κ on the Vth instability in order to separate the influence of the heterojunction design and the high‐κ/GaN‐cap interface from the bulk high‐κ. The matched gate capacitance coupling of the studied Al2O3 and HfO2 gate dielectric results in an nearly identical critical forward gate voltage, where the AlGaN barrier potential is lowered and severe threshold voltage shift (ΔVth) into the positive voltage direction is induced. Beyond this critical forward voltage, detailed time‐dependent stress pulse measurements from 1 µs to 1000 s revealed an immediate electron injection and trapping at the oxide/GaN interface for stress pulses with tstress ≥ 1 µs. The presented results of Vth drift analysis demonstrate the limits of the maximum tolerable forward gate voltage of the investigated Al2O3 and HfO2 MISHEMTs, although the excellent low‐leakage currents of the insulated gate would imply a potentially higher gate‐overdrive.

Analytical model for anomalous Positive Bias Temperature Instability in La-based HfO2 nFETs based on independent characterization of charging components

PBTI improvement in HfO2 nFETs achieved by a controlled insertion of La.Anomalous negative ΔVTH due to charge exchange between high-k and metal gate.Anomalous and conventional PBTI components are decoupled and studied separately.Analytical model including both components for lifetime extrapolation is presented. Incorporation of rare earth capping layers in the gate stack is an effective technique to tune the threshold VTH voltage of advance CMOS technologies. Furthermore, a reduction of the positive VTH drift (instability) has been reported for rare-earth doped nFETs under positive gate bias stress at high temperature. However, a non-optimized process can lead to an anomalous VTH behavior. We demonstrate that two independent components are responsible for this anomalous behavior which can be decoupled, individually studied, and then projected for meaningful lifetime extrapolations.

Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5 nm cross-section and high uniaxial tensile strain

In this work we report dense arrays of accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5nm cross-sections in a highly doped regime. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve ⩾2.5GPa uniaxial tensile stress in the Si nanowire is reported. The deeply scaled Si nanowire including such uniaxial tensile stress shows a low-field electron mobility of 332cm2/Vs at room temperature, 32% higher than bulk mobility at the equivalent high channel doping. The conduction mechanism as well as high temperature performance was studied based on the electrical characteristics from room temperature up to ≈400K and a VTH drift of −1.72mV/K and an ionized impurity scattering-based mobility reduction were observed.

One-Dimensional Thickness Scaling Study of Phase Change Material $(\hbox{Ge}_{2}\hbox{Sb}_{2}\hbox{Te}_{5})$ Using a Pseudo 3-Terminal Device

To address the scalability of phase change memory (PCM), we study a 1-D thickness scaling effect on threshold switching voltage (Vth), Vth drift, high resistance state (RESET) resistance (RRESET) drift, and crystallization temperature (Tcrys). We use a pseudo three-terminal device to accurately correlate the amorphous region thickness to the observed characteristics. The pseudo 3-terminal device is a fully functional PCM cell and enables 1-D thickness scaling study down to 6 nm without the need for ultrafine lithography. Vth scales down to 0.65-0.5 V (at 25°C-75°C) for 6-nm-thick Ge2Sb2Te5 (GST), showing that stable read operation is possible in scaled PCM devices. The Vth drift measurement suggests that Vth drift can be attributed to threshold switching field (Eth) drift, whereas Vth0, i.e., Vth at zero thickness, stays almost constant. RRESET drift shows no dependence on the amorphous GST thickness. Tcrys is ~175°C for the device with 6-nm-thick GST, compared with ~145°C of thick GST. From the 1-D scaling study, no significant hurdles against scaling are found down to 6 nm. Further study of scaling effect on endurance and development of scalable selection device is needed to assess the ultimate scalability of PCM.

Resistance and Threshold Switching Voltage Drift Behavior in Phase-Change Memory and Their Temperature Dependence at Microsecond Time Scales Studied Using a Micro-Thermal Stage

We study the drift behavior of RESET resistance RRESET and threshold switching voltage Vth in phase-change memory (PCM) and their temperature dependence. To extend the temperature-dependent measurement to microsecond time scales, we integrate an innovative micro-thermal stage (MTS) on the PCM cell. The MTS changes the temperature of the programmed region of the PCM cell within a few microseconds by placing the Pt heater in close proximity of the programmed region. First, we experimentally verify the existing phenomenological RRESET and Vth drift model for constant annealing temperature at various temperatures between 25°C and 185°C down to 100 μs and show that the measured temperature dependence of the drift coefficient agrees well with what is expected from the existing drift models. Based on the existing drift model for a constant annealing temperature, we derive the analytical expression for the RRESET drift for time-varying annealing temperature and experimentally verify the analytical expression. The derived analytical expression is important to understand the impact of thermal disturbance on PCM reliability such as variations in RRESET and Vth.

From Amorphous-Si Thin-Film-Transistors to Single Crystal-Si Transistors: Influence of Si Crystallinity on Device Properties

Silicon, under its various phases from amorphous (a-Si:H) to monocrystalline, with intermediates microcrystalline (µc-Si:H) and polycrystalline, can be used to manufacture devices with very different characteristics. We have investigated some links between device characteristics and material crystallinity. Carrier mobility is strongly dependant on defects with energy levels within the semiconductor bandgap, and these defects are reduced when crystal order is increased. The reduced drain leakage current in a-Si:H in comparison with microcrystalline (µc-Si:H) Thin-Film Transistors (TFTs) is explained by differences in material properties related to crystallinity. Finally, it is shown that µc-Si:H TFTs exhibit better threshold voltage (Vth) stability than a-Si:H ones. Investigation of Vth drift mechanisms indicates that this is related to improvement of the semiconductor material quality.

P‐4: Mechanisms of Threshold Voltage Drift in Nanocrystalline Thin‐Film Transistors for Active‐Matrix Displays

AbstractThe mechanisms of threshold voltage (Vth) drift in nanocrystalline silicon (nc‐Si:H) TFTs have been investigated. Using bias‐temperature stress measurements, it is found that the dominant mechanism of Vth drift is charge trapping in the SiNx gate insulator. This result is confirmed by a study on ambipolar nc‐Si:H:TFTs. Comparing with a‐Si:H TFTs, this means that the reduction of the voltage shift in nc‐Si:H TFTs is the result of an improvement of the semiconductor material.