Voltage Swing Research Articles

Research on Techniques for Enhancing the Speed of Low-Power Operational Amplifier

In the context of low utilization, this paper explores various techniques for enhancing the speed of operational amplifier (OA). The main text delves into three methods to gain equilibrium: fully differential operational amplifier (FDA), twostage operational transconductance amplifier (OTA), and a novel high-speed calculation system architecture employing a “rhombus crystal tube.” The FDA improves speed by minimizing noise and enhancing bandwidth and output voltage swing, without increasing power consumption. The design of the two-stage OTA combines the characteristics of a differential amplifier and a telescopic amplifier, optimizing gain and slew rate through Miller compensation and noise gain manipulation, thereby achieving high-speed performance. A novel high-speed operational amplifier structure employs diamond transistors to supply substantial current for capacitor charging, enhancing the slew rate and overall speed. Throughout the text, these methods are presented as a means to jointly promote high speed, low power consumption, and the handling of a significant number of transistors. To further increase the speed, the size of the microcrystalline tube is crucial. The research direction is outlined, and while the design equipment is in the foreground, there remains room for progress, especially in applications for large-scale electrical models. Future research aims to enhance the power efficiency of circuits, making them more practical and efficient. This study provides valuable insights into balancing power consumption and speed in advanced electronic devices.

Improving the photoswitching performance of a transistor with amorphous metal oxide semiconductor thin film by a gradient annealing approach

Metal oxides are attracting attention as electronic mate rials in research and industry. Thin films of amorphous indium gallium zinc oxide (a-IGZO) exhibit low absorbance in the visible spectrum, making them ideal components in transparent electronics. To widen the scope of use for thin film transistor (TFT) devices based on a-IGZO in on-chip sensing applications, photoresponsive behavior has been achieved by proper engineering of the active layers by either introducing a photosensitive top layer or using a method to generate localized states inside the band gap. In this paper, we propose a bilayer structured with the use of thermal annealing of a-IGZO film at different temperatures. Thermal annealing has been shown to improve the electrical performance of the TFT devices because of the improved film quality but negatively affects the photoresponsivity by removing tarp sites that play an important role in both charge generation and photomultiplication via the photogating effect. Therefore, here we propose an a-IGZO film with a high temperature-annealed bottom layer and pristine top layer. The bottom layer plays a vital role in the charge transport behavior, resulting in a low threshold voltage and subthreshold swing similar to the device with a fully annealed film, while the photoresponse of the device is driven by the higher density of gap states in the pristine top layer. This proposed method is advantageous to previously published procedures due to the simplicity of using no additional materials and complex steps to introduce trap sites into the photoactive layer, but only differential annealing temperature.

Optimization and analysis of Si/SiGe strained vertically stacked heterostructure on insulator FeFinFET for high performance analog and RF applications

As semiconductor technology advances, the exploration of novel materials and device architectures becomes imperative to meet the growing demands of integrated circuits for analog and radio-frequency (RF) applications. In this paper, various advanced technologies have been amalgamated such as integration of ferroelectric layer in multigate FinFET along with the adaptation of SOI technology. Further strain technology is also used which employs a tri-layered strained-silicon channel system with the help of SiGe to form Vertically Stacked Heterostructure on Insulator Ferroelectric based FinFET (VS-HOI-FeFinFET) and on comparison with baseline FeFinFET, it is found to show remarkable improvements in terms of various measured parameters such as drain current, switching ratio, threshold voltage and subthreshold swing. Subsequently, gate stacking architecture is incorporated in VS-HOI-FeFinFET to further optimize the device performance. The four different configurations C1 to C4 are taken in terms of four different combinations of gate stack materials considered for gate oxide such as C1(SiO2+Al2O3), C2(SiO2+HfO2), C3(Al2O3), and C4(Al2O3+HfO2). It is found that the static and analog performance of VS-HOI-GS-FeFinFET enhance sequentially from configuration C1 to C4 such as switching ratio is enhanced upto around 5 times, DIBL and quality factor are improved by around 41% and 58% respectively along with significant improvement in device efficiency, early voltage, intrinsic gain, output conductance and output resistance. Subsequently performance optimization of VS-HOI-GS-FeFinFET with variation in mole fraction of germanium is also explored for various analog metrics. Further, several RF parameters are also explored and it is observed that the gain frequency product (GFP) and gain transconductance frequency product (GTFP) are augmented by around three times in magnitude along with 16% reduction in the unity gain cut off frequency in C4 configuration, exhibiting its ability of high frequency amplification with minimized noise distortion thus makes the device suitable for various high performance Analog and RF applications.

Characterization and modeling of the mobility, threshold voltage, and subthreshold swing in p-GaN gate HEMTs at cryogenic temperatures

This study presents a comprehensive investigation of the electrical properties of p-GaN gate HEMT devices under cryogenic operations, spanning a temperature range from 300 K all the way down to 10 K. We report achievement of a low sub-60 mV/dec sub-threshold swing (SS) (33.2 mV/dec at 10 K), a high ION/IOFF ratio (∼3.5 × 1010 at 10 K), and a remarkable ID,max (∼358 mA/mm at 10 K) in p-GaN gate HEMTs operating under cryogenic conditions. Furthermore, the mobility, threshold voltage shifts, and SS characteristics at cryogenic temperatures are modeled in p-GaN HEMTs. In summary, p-GaN gate HEMTs are promising for cryogenic applications due to their low SS, high gm,max, impressive ION/IOFF ratio, and substantial ID,max. Furthermore, the modeling achieved in this work can pave the way for future characteristic prediction in p-GaN HEMTs at cryogenic temperatures.

Core-shell architecture and channel suppression: unleashing the potential of SC_RCS_DGJLFET

In this investigation, a suppressed channel-rectangular core–shell double gate junctionless field effect transistor (SC_RCS_DGJLFET) is simulated to enhance the junctionless device’s performance. This study leverages a core–shell architecture and channel suppression technique to improve the gate controllability over the channel region which helps in substantial depletion of the shells in the OFF state of the device. When compared to conventional double gate JLFETs (C_DGJLFET) and rectangular core–shell double gate JLFETs (RCS_DGJLFET), the performance of the SC_RCS_DGJLFET is superior in terms of IOFF, ION/IOFF ratio, DIBL and subthreshold slope (SS). The SC_RCS_DGJLFET achieves an ultra-low IOFF of 7.033 × 10−16 A, indicating a low leakage current with an impressive ION/IOFF = 5.092 × 1011 . Other performance parameters such as subthreshold slope and DIBL has also been improved for the SC_RCS_DGJLFET device. Subthreshold slope has been decresesd by 4.76% whereas the DIBL decreased by 33.82% when compared to existing RCS_DGJLFET. Additionally, to analyze the effect of doping on the device performance, the core doping in SC_RCS_DGJLFET is varied for fixed shell doping. The study found that fixing core doping to an appropriate value is a crucial parameter to achieve good device performance. The impact of variation of oxide extension towards the source and drain LextS/LextD in SC_RCS_DGJLFET is also studied for the first time in the core–shell architecture which has further improved the device’s performance. Finally, a CMOS inverter is designed using the proposed device that provides valuable insights into its suitability for digital circuit applications and verifies its performance benefits compared to existing transistor technologies. The SC_RCS_DGJLFET based CMOS inverter shows a sharp transition in voltage transfer characteristics (VTC), indicating fast switching speed and precise signal processing capabilities when compared to a CMOS inverter based on a conventional double gate junctionless field effect transistor (C_DGJLFET). Moreover, the transient characteristics of the SC_RCS_DGJLFET based CMOS inverter exhibit an improved output voltage swing, suggesting enhanced dynamic behaviour and stability during logic state transitions.

Reversible Switching of Light‐Gated Organic Transistors Employing Dihydroazulene/Vinylheptafulvene Photo‐/Thermochromic Molecules

AbstractAn innovative possibility to introduce additional functionality to organic field‐effect transistors (OFETs) is to employ photochromic molecules, which undergo reversible isomerization under applied stimuli such as irradiation with specific wavelengths. As a result, the transistors not only can be switched on/off by the applied voltages, they can also be programmed by alternate triggers, such as light. Here, reversible switching of OFETs is presented by blending various dihydroazulene/vinylheptafulvene photoswitches into polythiophene‐based conjugated polymers. In result, the transfer characteristics of the transistors are altered significantly through UV irradiation. In contrast to current literature on different photoswitches such as spiropyrans or diarylethenes, the backreaction is induced thermally and not via visible light irradiation and reproducibly yields the pristine transistor characteristics. This reversible switching upon alternating UV irradiation and thermal annealing is quantified by figures of merit such as the magnitude of drain current, threshold voltage, and subthreshold swing. Irradiating the devices with different doses of UV light shows that the magnitude of switching directly depends on the respective UV dose, hence enabling a multi‐level electronic system. Furthermore, long‐term cyclability over 100 steps of repeated UV light exposure and thermal annealing is demonstrated.

DC and RF analysis of ScAlN/GaN/β-Ga2O3 and ScAlN/InGaN/GaN/β-Ga2O3 HEMTs on SiC substrate

Scandium aluminum nitride (ScxAl1-xN) is a promising material among group III nitrides, offering outstanding polarization properties resulting in very large carrier densities. We report the comparative analysis of Sc0.18Al0.72N/GaN/β-Ga2O3 and Sc0.18Al0.72N/InGaN/GaN/β-Ga2O3 HEMTs on Silicon carbide substrate. LG = 55 nm, Sc0.18Al0.72N/GaN/β-Ga2O3 HEMT demonstrated maximum current density (IDS) of 4.38 A/mm, very large carrier density (ns) of 2.34 × 1013 cm−2, large breakdown voltage (74 V) with low on-resistance (Ron ∼ 0.2 Ω mm), and cut-off frequency (fT)/maximum oscillation frequency (fmax) of 220/242 GHz. Introduction of a very thin 5 nm In0.1Ga0.9N layer in the channel, further improves the 2DEG (two-dimensional electron density), drain current, breakdown voltage. Furthermore, Sc0.18Al0.72N/InGaN/GaN/β-Ga2O3 heterostructure shows stable transconductance (gm) over wide gate bias. A gate voltage swing (GVS) of 7.72, IDS of 6.08 A/mm, and VBR of 105 V with Ron ∼ 0.138 recorded. These findings show the merits of scandium aluminium nitride barrier material, which enables the HEMTs for next generation radar and telecommunications.

Demonstration of normally-off p-channel GaN transistor with high threshold voltage and low subthreshold swing based on single p-GaN

Demonstration of normally-off p-channel GaN transistor with high threshold voltage and low subthreshold swing based on single p-GaN

A High Gain, Low Power Operational Transconductance Amplifier Capable of Recording and Processing ECG Signals

Based on high output resistor current mirrors and differential pair inputs, a new operational transconductance amplifier (OTA) is designed in this paper that can collect, filter, denoise and amplify electrocardiogram (ECG) signals. The OTA is designed on a 0.18μm CMOS process with a supply voltage of 1.8V. In this experiment, the ECG signal generated by the human model is first simulated, which has a noise of 50 Hz from electromagnetic interference, especially the electrical power lines. The differential input pair is then connected to the model, and it is proved that it can denoise the common-mode noise. Finally, the designed OTA is connected to the manikin, and the experimental results are compared with the traditional OTA. The design achieves a differential-mode gain of 43.56dB and a common-mode gain of -31.36dB while maintaining a differential input voltage swing of 1Vpp. Experimental results show that the OTA can denoise and amplify the ECG signal without distortion.

Compact modeling of short-channel effects in back-gated 2D negative capacitance (NC) FETs

The negative capacitance field-effect transistor with 2D channel material (2D NC-FET) holds significant promise for low-power applications owing to its remarkable resilience against short-channel effects (SCEs) and favorable noise characteristics. In this study, we establish a compact current–voltage (I–V) model for short-channel back-gated 2D NC-FETs with metal-ferroelectric-metal–insulator–semiconductor structure by self-consistently solving the two-dimensional Poisson, drift–diffusion and Landau–Khalatnikov equations. The proposed model is valid and continuous throughout the entire operating regime, including the fully-depleted region, partly-depleted region, and accumulation region. Furthermore, we derive analytical equations for the threshold voltage ( VTH ) and subthreshold swing ( SS ) of back-gated 2D NC-FETs based on the developed I–V model. Lastly, we elucidate the influence mechanisms of various device parameters and voltage bias on the subthreshold characteristics of short-channel back-gated 2D NC-FETs using the proposed I–V model in conjunction with analytical expressions of VTH and SS . Our findings reveal that back-gated 2D NC-FETs shows unconventional degradation behavior in VTH and SS, resulting from the competition between traditional SCEs and novel negative capacitance effects.

An improved microgrid energy management system based on hybrid energy storage system using ANN NARMA-L2 controller

This research describes an intelligent Energy Management System (EMS) for a microgrid application that employs a Nonlinear Autoregressive Moving Average Level 2 (NARMA-L2) artificial neural network (ANN). The hybrid energy resources (PV/WIND), a hybrid energy storage system (HESS) with batteries and supercapacitors (SC), and loads are all integrated into the microgrid. Maximum Power Point Tracking (MPPT) in a photovoltaic (PV) system is based on the Nonlinear Autoregressive with exogenous inputs (NARX) approach. The flowchart, rules, memberships, and scenarios that allocate energy among various components based on battery State of Charge (SoC), PV/wind power, and load factors are described in the article. To validate the EMS's effectiveness, simulation tests under various conditions are presented. Supercapacitors (SCs) reduce DC bus voltage swings, lowering battery stress and extending battery life, it has been demonstrated using various load variations, as well as various sun irradiation and wind speed values under various conditions. The simulation results in the MATLAB/Simulink environment, validate the effectiveness of the proposed approach and produce effective DC BUS stabilizing and maintaining frequency stability of system that shows the importance and efficiency of the control strategy used.

Influence of Doping Engineering in 1 μm Drift Layer Quasi‐Vertical Fin Field‐Effect Transistor for Achieving >139 V Breakdown Voltage

A quasi‐vertical gallium nitride (GaN) fin field effect transistor (FinFET) is designed and analyzed to assess the performance of electrical parameters. The device is deployed on a silicon carbide (SiC) substrate and analyzed using technology computer‐aided design (TCAD). The donor concentration in the critical regions is identified as a significant limiting factor for FinFET electrical properties. Hence, the influence of channel and drift layer doping concentrations (Nd) on performance characteristics is investigated in this work. The electrical characteristics such as threshold voltage, ION/IOFF ratio, subthreshold swing (SS), specific ON‐resistance, and breakdown voltage (VBV) are evaluated for various doping profiles. The doping profile with channel and drift layer concentration of 4 × 1015 cm−3 for a 300 nm fin width and 1 μm thick drift layer exhibits normally OFF behavior with a threshold voltage (Vt) of 1.5 V. It also demonstrates a VBV of 139 V. The corresponding doping profile reveals a low SS of 61 mV dec−1, which is comparable to other similar power devices. This demonstrates the significant potential of the device for medium‐power switching applications.

A High-Speed Silicon Ring Modulator with a Large Working Wavelength Range

With the advantages of high speed, small size, and easy integration, the silicon photonic resonant ring modulator has gradually become a critical device for emerging integrated optical platforms. Ring modulators are primarily used in optical communications, optical computing, artificial intelligence, and other fields. In this work, the proposed ring modulator can operate in both the O- and C-bands. The 3 dB electro-optical (EO) bandwidth of the ring modulator is 39 GHz and 34 GHz at −4 V in the O-band and C-band, respectively. The modulation efficiency of the device is 0.92 V·cm and 0.95 V·cm in the O-band and C-band, respectively. The eye diagram of an optical output signal from the device is tested using a 100 Gbit/s non-return-to-zero (NRZ) input signal with a 2.5 Vpp in both the O-band and C-band. The modulation speed can reach 140 Gb/s and 120 Gb/s in the O-band and C-band with four-level pulse amplitude modulation (PAM-4) formats at a voltage swing of 2.5 Vpp, respectively.

Investigation on palladium gate electrode-based SOI junctionless FET for hydrogen gas sensing

This study provides a comprehensive investigation on palladium (Pd) gate electrode-based silicon on insulator (SOI) junctionless field-effect transistor (JLFET) for hydrogen gas (H2) sensing (Pd–SOI-JLFET). The device has a gate dielectric stack consisting of silicon dioxide (SiO2) and hafnium dioxide (HfO2). An extensive analysis was conducted to detect and identify the presence of hydrogen gas by examining several electrical characteristics such as drain current (IDS), transconductance (gm), output conductance (gd), energy band diagram (E), gate-to-source capacitance (CGS), and surface potential (Φs). Furthermore, a comprehensive investigation was conducted to examine the impact of the presence of H2 gas and variations in temperature on important parameters associated with the short channel effects (SCEs) including off-state current (IOFF), on-state current (ION), subthreshold swing (SS) and threshold voltage (Vth). In addition, the sensitivity analysis of the off-state current (IOFF) by considering process variation effect has been done. Sensitivity is also calculated at various temperatures for the detection of hydrogen gas molecule. At the temperature of 300K, the sensitivity values were obtained as 1.50083, 3.21754, 27.71483, 152.39617 and 2052.8 for pressure values 10−14 Torr, 10−13 Torr, 10−12 Torr, 10−11 Torr and 10−10 Torr, respectively. This analysis provides a thorough examination of the performance and efficacy of the Pd–SOI-JLFET hydrogen gas sensor highlighting its potential for a wide range of hydrogen sensing applications.

Statistical analysis of vertically stacked nanosheet complementary FET based on polycrystalline silicon with multiple grain boundaries

In this study, a complementary field-effect transistor (CFET) based on a polycrystalline silicon (poly-Si) stacked-nanosheet (NS) structure with a grain boundary (GB) is designed and analyzed using a technology computer-aided design (TCAD) simulation. The advantage of the CFET using a poly-Si is that the active cell region can be reduced by 50 % because the p-type transistors are vertically stacked on the n-type transistors. In addition, it is possible to replace the conventional CMOS process and fabricate a three-dimensional vertically stacked structure at a low cost. To consider the effect of the GB in poly-Si, we assumed that there is a single GB at the center of the body region. By optimizing the geometrical parameters of the proposed CFET, the transfer characteristics of the NMOS and PMOS transistors, such as the threshold voltage (Vth), on current (Ion), off current (Ioff), and subthreshold swing (SS), are symmetrical. The proposed CFET demonstrated a superior logic performance of NML = 0.299 V and NMH = 0.297 V at an operation voltage of VDD = 0.65 V. To consider random GBs in the poly-Si, we assumed that five GBs existed in the proposed CFET, and the variation in CMOS logic inverter characteristics are statistically analyzed. As a result, the RSDs for Vm of the NMOS and PMOS transistors are 2.067 % and 0.293 %, and the RSDs of the pull-down delay time (tpHL) and pull-up delay time (tpLH) are 5.320 % and 3.244 %, respectively. An acceptor-like traps with high trap density are dominant in the proposed CFET, and this trend is similar across the 1024 samples. Nevertheless, most of the differences are within 5 % and the proposed CFET exhibited stability against GBs and the potential to replace the conventional CMOS logic inverters.

Electrical characteristics of Si0.7Ge0.3/Si heterostructure-based n-type GAA MOSFETs

Electrical characteristics of Si0.7Ge0.3/Si heterostructure-based n-type gate-all-around MOSFETs (GAA MOSFETs) are reported in this work through experimental and numerical simulation data. N-type GAA MOSFETs of varying lengths (60 nm to 160 nm) and widths (20 nm to 42 nm) are fabricated and measured to extract key electrical parameters like ON current, ON-to-OFF current ratio, threshold voltage, DIBL, and subthreshold swing. Moreover, the influence of tensile strain on carrier transport parameters in the buried Si layer is examined in this work. The Ge mole fraction in SiGe is raised from 0.2 to 0.3, and the corresponding changes in XX-stress, and current density are analyzed using a TCAD simulator. The performance of the proposed device has also been compared with unstrained SiGe/Si, all Si, and SiGe-based GAA MOSFETs.

Dynamic scheduling of electricity demand for decentralized EV charging systems

The rapid growth of electric vehicles (EVs) has brought forth new challenges to the power grid. Further, the simultaneous charging of EVs could lead to peak demand, potentially causing overloading, voltage swings, and other grid-related problems. To address these issues and lower the high energy costs faced by EV owners and grid operators, EV charging must be optimized. The study proposes an innovative strategy that utilizes decentralized charging systems to lessen the impact of EVs on the grid. A decentralized EV scheduling strategy offers scalability. Thus, making it suitable for a large EV population and it remains resilient to the dynamic arrivals of the EVs. The approach aims to balance the load on the grid and improve the effectiveness of charging operations. To achieve this, a convex optimization problem has been developed to effectively regulate the charging procedure, taking into account the distinct attributes of each EV. The mechanism operates by dividing time into several intervals. Each electric vehicle in the system autonomously adjusts its charging rate during the assigned time slots, with the goal of minimizing individual charging expenses. Moreover, the system demonstrates flexibility in deciding when to charge and discharge, allowing prioritization based on individual EV battery levels and power grid conditions. As a result, the cost analysis was conducted using the number of EVs and the average group size. A comparison of computational times between centralized and decentralized systems was undertaken to demonstrate the efficacy of the system.

Effect of electron mobility variation on short channel effects in nanoscale double gate FinFETs: A comparative study

This work investigates the impact of electron mobility variations on short channel effects (SCEs) in different semiconductor materials using FinFETs. Using PADRE simulator, the work examines Gallium Arsenide (GaAs), Gallium Antimonide (GaSb), Gallium Nitride (GaN), and Silicon (Si) FinFETs, analyzing performance metrics such as Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS) and Threshold Voltage roll-off. The result shows that GaN-FinFET exhibits lowest subthreshold swing of 63 mV/dec at electron mobility of 10000 cm2/Vs, and threshold voltage of 0.44V at electron mobility of 10000 cm2/Vs, while Si-FinFET exhibits lowest DIBL of 3 mV/V at (4000-10000) cm2/Vs. This finding contributes to advancing the understanding of short channel effects in nanoscale FinFETs and provides valuable insights for optimizing device performance in future semiconductor technologies.

Performance optimization of AlGaAs and Al x Ga 1−x As based SM-TM-DG-JL-TFET for an analog/RF applications

This study aims to enhance the efficiency of the Double Gate-Junctionless-Tunnel Field Effect Transistor (DG-JL-TFET) by optimizing the utilization of AlGaAs and GaAs/Si/AlGaAs-based Single Material and Tri-Material (SM and TM) configurations.In order to overcome the drawbacks of present TFET architectures, such as their limited ability to drive current and their ambipolar behaviour, and to enhance the on-state current, To execute our suggested SM-TM-DG-JL-TFET configuration. The TM structure exhibits a greater on-state current (I on ) and a lower SubthersholdSwing (SS) in comparison to SM structures. This study quantifies the Unit-gain-current-cut-off-frequency (f t ) and Maximum oscillation frequency fmax by manipulating geometric parameters such as gate length(l g ), gate-oxide thickness, and Channel thickness. The TM structure exhibits a significantly greater on-state current (I on ) of 14 × 10−3 A. Compared to SM structures, while simultaneously reducing the off-state current (I off ), subthreshold swing (SS), and threshold voltage (V t ). TM structures exhibit higher values of f t and fmax in DG-JL-TFET due to their enhanced output conductance compared to SM structures. The device exhibits potential for future low-power-RF applications due to its significant values of f t and fmax .

DC and RF performance analysis of enhancement mode fin-shaped tri-gate AlGaN/GaN HEMT and MOSHEMT with ultra-thin barrier layer

The DC and RF assessment of critical barrier-AlGaN/GaN nano channel tri-gate fin-shaped High Electron Mobility Transistor (FinHEMT) is investigated for Enhancement-mode (E-mode) operation. We propose and analyze critical barrier layer (CBL) and critical-strained barrier layer (CSBL) FinHEMT for a fixed fin-shaped channel width (W fin = 160 nm) and height (H fin = 70 nm). The CBL FinHEMT ensures an E-mode operation by depleting two-dimensional electron gas (2DEG) near the channel region between AlGaN and GaN hetero-junction. The extracted threshold voltage (V T ) in CBL FinHEMT is 0.4 V as compared to −0.2 V obtained in CSBL FinHEMT. However, increased gate leakage current density and poor gate voltage swing in CBL FinHEMT is improved through a metal-oxide-semiconductor FinHEMT (FinMOSHEMT) structure by the incorporation of Al2O3 gate oxide layer between the tri-gate and CBL AlGaN layer. It results in a stable positive VT of 0.5 V due to the negatively charged Al2O3/barrier interface fixed charge density ( NAl2O3 ). The proposed CBL FinMOSHEMT has also been studied for different atomic layer deposition Al2O3 process-dependent variations in NAl2O3. The maximum on-state drain current and transconductance of 1.01 A mm−1 and 430 mS/mm have been extracted respectively with NAl2O3 of −9.2 × 1012 cm−2. Further, the RF analysis of the proposed CBL FinMOSHEMT structure with the same dimension exhibits improved f T and f max responses with 27 GHz and 90 GHz respectively over CBL FinHEMT. The results of the frequency responses obtained for the proposed design make it suitable for power electronics applications.