Multilevel Voltage Source Inverter Research Articles

Performance comparison of series and parallel damped LCL filters using 5-level voltage source converter

The high harmonic content produced by conventional converters has resulted in the increased system size and cost, due to the need for large-sized low-order harmonic passive filters and cooling system requirement. Given that, multilevel inverters and special modulation techniques were developed to suppress or eliminate the low-frequency harmonics and the left behind high-order ones are eliminated using a high-frequency small-sized filter. Hence, this paper designs and compares the total harmonic distortion (THD) and efficiency values of three set of filters, namely LCL filter, LCL with series and parallel resistance on a novel five-level multilevel voltage source inverter topology. The novelty lies with the proposed inverter, which, apart from using a single direct current source, it can extend it elimination capability beyond the normal five level using the concept of multiple switching per step and an optimised selective harmonic elimination pulse width modulation. The converter can eliminate eleven lower-order odd nontriplen harmonics, hence making the 37th harmonic at 1.85 kHz to be the first dominant harmonic. At 2-kW loading, two of the filters have THD below 5%, therefore satisfying the IEEE 519 standard. The parallel resistance damped filter (LCL-P-R) has less THD value but poor efficiency due to the resistance introduced into the circuit. The study was carried out using PSIM and MATLAB software.

A Three-Phase Hybrid Cascaded Multilevel Inverter with Multicarrier PWM technique

Multilevel voltage source inverter has drawn tremendous importance in the area of high power applications. This paper presents a three-phase modified hybrid cascaded multilevel inverter incorporating a standard three-leg inverter with H-bridge cells in series with each leg. The switching scheme with the multicarrier level shifted sinusoidal PWM is implemented to produce the five-level voltage at the output. Simulations have been performed using MATLAB to study voltage levels, modulation scheme, and THD. Finally, the possibilities of future works are addressed.

A Framework for Optimum Determination of LCL-Filter Parameters for N-Level Voltage Source Inverters Using Heuristic Approach

The use of voltage source multilevel inverters (VS-MLIs) has grown enormously over the last decade, and it is expected that these inverters will be deployed in future power grids (smart grids), especially for medium voltage–high power applications. This paper investigates the application of passive power filters (PPFs) for harmonic mitigation at the output of VS-MLIs for more efficient grid integration of renewable energy sources. It proposes a generic model, using a heuristic approach, for the optimum design of an LCL power filter at the output of VS-MLIs. The proposed model transforms the LCL filter design problem into an optimization problem and applies a genetic algorithm (GA) to solve it. The objective function to be optimized is a multi-objective function based on inverters’ total harmonic distortion and energy losses. The optimization problem is subject to applied design constraints. As a main optimization objective, a precise evaluation methodology for the inverter power losses is presented, which was built according to a practical switching device datasheet. The method is applicable to any VS-MLI topology and any number of levels (N). As a case study, the proposed design optimization approach was implemented to optimally design the LCL filter at the output of a grid connected 11 KV, 5 MVA 7-level cascaded H-bridge multilevel invert (CHB-MLI). The IGBT module Device IGBT of type FZ400R65KE3 by Infineon was used for simulation. MATLAB-SIMULINK is used for the modelling and simulation. We found that the proposed design approach is more generic, efficient, and simple to apply than conventional design approaches which requires more system detail, relies more on the designer’s experience, and normally does not results in optimum design. The proposed approach is generic and can be applied for different VS-MLIs topologies and for any number of levels (N).

Performance Comparison of Five-Phase Three-Level NPC to Five-Phase Two-Level VSI

A multiphase multilevel voltage source inverter (VSI) offers excellent advantages over the traditional three-phase counterparts. Low-order harmonic components with reduced switching losses, lower common-mode voltage (CMV), and the optimum use of dc-link voltage constitute the critical performance indicators for high-efficiency VSI evaluation. Various approaches for carrier-based pulsewidth modulation (CPWM) generation are available in the literature along with space vector pulsewidth modulation (SVPWM) techniques. Comparative analysis shows that the majority of SVPWM strategies have enormous potential than CPWM to achieve the aforementioned performance indices. The main objective of this article is to provide a common platform for the selection of available five-phase VSIs for various industrial applications. For this, a comparative study is carried out to examine in various aspects like CMV, voltage and current total harmonic distortion (THD), switching, conduction losses, and efficiency under the steady-state and dynamic loading conditions over a wide range of the modulation index. It is observed that the five-phase three-level neutral-point-clamped (NPC) VSI has better performance than the five-phase two-level VSI. Experimental results are provided to verify the performance indices of both topologies at steady-state and dynamic conditions.

Selective harmonic elimination (SHE) based 3-phase multilevel voltage source inverter (VSI) for standalone applications

The breakthroughs in power electronics semiconductor technology have led to the raised in popularity of Multi-level Voltage Source Inverters, which is the reason industries and researchers are relentlessly working towards extending it to both medium and high-power applications. Consequently, this paper presents a modified Selective Harmonic Elimination Pulse Width Modulation (SHE-PWM) controlled three-phase 5-level Multi-level Inverter (MLI) topology. The work is an extension of a single-phase topology proposed by the authors. The uniqueness of the proposed topology is that it comprises of six Cascaded H-bridge modules (two modules per phase) that are powered through a single direct current (DC) source, hence eliminating the need for multiple DC sources. In addition, conventional 5-level MLI has two switching angles (n = 2), which restricts its harmonic elimination capability to one (n = 1) lower order harmonics. This study removes that restriction by utilising the concept of multiple switching per step, resulting in the superimposing of 12 notches (n = 12) on the output voltage at the 3/9 distribution ratio. With the fundamental switching SHE-PWM, twelve non-linear, transcendental equations are generated, and they are optimally solved using the Hybrid Coded Genetic Algorithm to eliminate 11 (n − 1) lower-order harmonics. The low-switching frequency results in less electromagnetic interference as well as reduced switching loss, which improves the overall inverter efficiency. The topology has less output Total Harmonics Distortion, fewer components, and lower weight and cost than conventional topologies. The circuit was designed and validated through simulations performed in PSIM software.

Review of Multilevel Voltage Source Inverter Topologies and Analysis of Harmonics Distortions in FC-MLI

We review the most common topology of multi-level inverters. As is known, the conventional inverters are utilized to create an alternating current (AC) source from a direct current (DC) source. The two-level inverter provides various output voltages [(Vdc/2) and (−Vdc/2)] of the load. It is a successive method, but it makes the harmonic distortion of the output side, Electromagnetic interference (EMI), and high dv/dt. We solve this problem by constructing the sinusoidal voltage waveform. This is achieved by a “multilevel inverter” (MLI). The multilevel inverter creates the output voltage with multiple DC voltages as inputs. Many voltage levels are combined to produce a smoother waveform. During the last decade, the multilevel inverter has become very popular in medium and high-power applications with some advantages, such as the reduced power dissipation of switching elements, low harmonics, and low EMIs. We introduce the information about several multilevel inverters such as the diode-clamped multilevel inverter (DC-MLI), cascaded H-bridge multilevel inverter (CHB-MLI), and flying-capacitor multilevel inverter (FC-MLI) with Power systems CAD (PSCAD) simulation. It is shown that THD is 28.88% in three level FC-MLI while THD is 18.56% in five level topology. Therefore, we can decrease the total harmonic distortion adopting the higher-level topology.

Comparison of Different Multilevel Voltage Source Inverter Topologies on Induction Motor Energy Quality

Comparison of Different Multilevel Voltage Source Inverter Topologies on Induction Motor Energy Quality

Common mode voltage suppression in three‐phase voltage source inverters with dynamic load

This study proposes a novel pulse width modulation (PWM) algorithm to mitigate the common mode voltage (CMV) in a multi-level voltage source inverter feeding an electric machine. Dead-time effect frequently prevents the CMV not to reach zero in several switching periods. Then the electromagnetic interference noise is generated and causes bearing failure and overvoltage stress on winding insulations. The proposed strategy compensates the dead-time effect that alleviates the high-amplitude rectangular pulses with extreme range of variations during high-frequency switching transitions. The existing PWM methods reduce the CMV to ±V dc /6, however by utilising the presented approach, CMV can be reduced to zero. However, the total harmonic distortion will be increased 0.3% at fundamental current harmonic rather than conventional state PWM method, which could be neglected. Simulation results and efficiency analysis imply on worthy performance of the proposed strategy to eliminate the CMV.

A comparative study of cascade H-bridge multilevel voltage source inverter and parallel inductor multilevel current source inverter

This paper presents the analysis study between multilevel inverters that are often classified into multilevel voltage source and multilevel current source inverters. For multilevel voltage source inverter (MVSI), the specific topology studied for this work is the Cascaded H-Bridge MVSI. Whereas, the multilevel current source inverter (MCSI) is based on Paralleled Inductor Configuration MCSI. For this study, the analysis between these converters are done with respect to the number of components, the advantages and disadvantages of each converters during performing inverter operation. In term of output voltage and current quality, the percentage of the Total Harmonic Distortion (THD) are measured and compared for both topologies. MATLAB/Simulink software has been used in this research to design and simulate in order to study the performances of both inverters.

Modeling and Simulation of Five-Phase Induction Motor Fed With Pulse Width Modulated Five-Phase Multilevel Voltage Source Inverter Topologies

This paper presents modelling and simulation of five-phase induction motor fed with pulse width modulated five-phase multilevel voltage source inverter. The conventional and diode clamped multilevel five-phase inverter configurations are reviewed with pulse width modulation (PWM) techniques. A hybrid three-level inverter topology with less number of components count is proposed for five-phase induction motor drive. The dynamic analysis of five-phase voltage equations in d-q axis of the induction motor are stated and modelled using Matlab/Simulink/Simscape blocks. The simulation results based on conventional and threelevel five-phase inverters are displayed while the hybrid inverter topology showed some better performance based on the following: : at 0.0127secs maximum torque of 34.54Nm occurred, maximum stator current occurred for 0.18secs with a value of 10A, 9.99% total harmonic distortion was obtained and 15KW power rating was obtained.

Multi‐channel VSI fed large variable speed asynchronous hydro‐condenser: fault analysis, fault diagnosis and fault tolerant control

Multi-level voltage source inverter (VSI) fed doubly fed induction machine (DFIM) has gained prominence in large rated hydro-generating unit (HU) since it provides part load operation with reduced power converter rating and high dynamic stability. Power converters connected in rotor side control real and reactive power of the unit. This study discusses the condenser operation of variable speed HU (250 MW), to be commissioned in Tehri plant (India), with the power flow diagram. Further, it provides dynamic behaviour and survivability status of the DFIM unit during power converter and control circuit faults where power converter redundancy is not available in large rated DFIM unit. Economic analysis of 250 MW HU under power converter and control circuit failures are also investigated. The present work also explores fault tolerant operation of a 250 MW DFIM unit at open switch fault in converters to increase the continuity of the unit operation which provides additional 2% of reactive power support to the grid compared to the DFIM without power converter redundancy operation. Open switch fault is detected through Park's vector phase currents technique and variation in DC link voltage. The computer simulation results are validated in an experiment carried on 2.2 kW DFIM in the laboratory.

Reduction of circuit devices in symmetrical voltage source multilevel inverter based on series connection of basic unit cells

In this study, a novel modular configuration for symmetrical multilevel inverter is proposed. The proposed topology consists of basic unit cells which are enclosed by series connected six power semiconductor switches. In contrast with contemporary topologies, the proposed topology offers same voltage level with a lower number of power switches thereby reducing the number of gate driver circuits, which in turn reduce the size and cost of the inverter circuit. The proposed topology is efficient to generate 9 and 11-levels of output voltage with only ten power semiconductor switches. In addition, the proposed topology offers less number of ON state switches to reduce the power loss. The proposed topology using universal switching scheme based on modified sinusoidal pulse width modulation is verified through simulation and feasibility of topology has been validates experimentally on laboratory prototype using dSPACE real-time controller.

A Survey of Multilevel Voltage Source Inverter Topologies, Controls, and Applications

Multi-level converters are every day attracting research interest due to it tremendous positive contributions they are making in the power industries. The converter has put hope in the minds of power electronic engineers that a time will come when it will break a record by providing an efficient means of utilizing the abundant renewable energy resources.<strong> </strong>The paper presents a review of multilevel voltage source converters that are widely being used in engineering applications. It reports the technological advancements in converter topologies of Flying Capacitor (FC), Neutral Point (NPC) /Diode Clamped, and Cascaded H-Bridge (CHB) with their respective advantages and disadvantages. Recent customized/hybrid topologies of the three-phase multilevel inverter with reduced component count and switching combination are reported. The paper also reviewed different modulation techniques such as the multilevel converter carrier base PWM, Space Vector Modulation techniques (SVM), and Selective Harmonic Elimination method (SHE-PWM). Finally, various multilevel converters areas of application were highlighted. This review will expose the reader to the latest developments made in the multi-level topologies, modulation techniques, and applications.

New advanced concept of the flying capacitor asymmetric multilevel voltage source inverter

PurposeTo improve the voltage quality in AC adjustable high-power-speed-drive applications, the purpose of the paper is to provide a large number of output levels without increasing the number of commutation cells in the three-phase, n-cells flying capacitor voltage source asymmetric Multilevel Inverter (MI). The concept is based on the selection of different ratios between the breakdown voltages of two successive power devices. The new mathematical model is developed under various ratios, allows a thorough investigation of the harmonic distortions, flying capacitor energy storage, flying capacitor voltage balancing controllability and blocking voltage insulated gate bipolar transistor (IGBT) capability.Design/methodology/approachThe asymmetrical design provides a large number of output levels without increasing the number of commutation cells. The important new analytical expression of capacitors voltage distribution is derived and extended to any ratio between the switch breakdown voltages of two successive power devices.FindingsThe detailed simulation study of the proposed concept has been carried out using MATLAB/Simulink. The power switches control of the three-phase three-cell MI is assured by new phase-shifted-multi-carrier pulse width modulation. The space vector representation is used to show the regular and irregular step output voltage in the complex plan (α,β).Originality/valueIn the paper, the n cells flying capacitor inverter, which typically operates in the (n + 1) levels mode, was extended to (n + 2), (n + 3) … until 2n levels with regular or irregular step output voltage. Consequently, the claimed advantages of the asymmetric MI are to improve power quality by reducing harmonic distortions and to reduce the requirement on capacitive energy storage in the circuit.

Simulation and Study of Multilevel Inverter System Fed By Photovoltaic Source

This paper proposes a simulation of Photovoltaic energy used to supply an induction motor with acomparison of two types of inverters.In general, the greater number of motorswhich"are used incommercial and industrial applicationsare"induction motors. To use PV source to run the induction motor, an interface circuits are used which are a dc-dc"converter and an inverter, the PV cell has nonlinear behavior,"adc-dc converter is used along with Maximum Power Point Tracker controllerto improve theefficiency by boosting the output voltage of the PV module and to match the load demand."The dc output voltage of PV modulethen"converted to AC, two types of inverter are presented, A conventional Voltage Source Inverter system and multilevel inverter system which employselective harmonic eliminationmethod fed three phase induction motor, these two types of inverters are simulated using Matlab/Simulink and their results are presented. The FFT spectrum is presented of the output currents to analyze the harmonics reduction, which shows that the"multilevel inverter is better than VSI system"according to harmonics reduction and increment in output voltage and power.

Time‐domain characterisation of multicarrier‐based digital SPWM of multilevel VSI

The effect of sampling frequency on digital sinusoidal pulse width modulated (SPWM) output of phase-shifted carrier-based multilevel voltage source inverter (VSI) and the characteristics of output voltage and load current has been discussed here. The generalised equation of digitally controlled phase-shifted carrier-based multilevel VSI output voltage is derived using double Fourier integral solution. The Jacobi–Anger expansion has been used to obtain the integral solution. Time-domain analysis has been used to establish the relation between sampling frequency, carrier frequency, and fundamental frequency, at different modulation indices for n-level VSI. The load current of VSI is stepped in nature due to stepped variation in the output of the digital SPWM. Therefore, the low-frequency harmonic components closer to the fundamental frequency appear in the frequency spectrum. The variation of total harmonic distortion with respect to multisampling factor (sampling to carrier frequency ratio) has been discussed at different modulation indices for multicarrier-based multilevel inverter. The analytical results are verified through simulation and laboratory experimental results.

A developed single-phase cascaded multilevel inverter with reduced number of circuit devices

ABSTRACTIn this paper, an advanced configuration for multilevel voltage source inverters is proposed. The proposed topology can be used as symmetric and asymmetric inverter. In asymmetric mode, DC sources’ magnitudes are defined in a way that the number of output voltage levels gets more than the case when the symmetrical DC sources are applied. In this regard, to calculate the magnitudes of required DC voltage sources, several different solutions are proposed. In multilevel inverters, the overall cost, circuit size and so installation area, complexity of control scheme and reliability are directly dependent on the number of circuit devices needed. The provided comparison study among suggested inverter in all defined solutions, CHB and recently proposed converters validates that the proposed modular inverter uses reduced number of circuit devices. The provided simulation and experimental results confirm the feasibility of the proposed structure and show that the obtained results are in good agreements.

Symmetric hybridised design for a novel step‐up 19‐level inverter

Nowadays, reduction in number of dc voltage sources alongside boosting property of the output voltage with reduced circuit components are counted as the most important topological features for the new structures of multilevel voltage source inverters. Considering the above, this study presents a new configuration of such converters which can produce a step-up 19-level waveform of the output voltage with a contribution of only two same (symmetric) values of dc voltage sources and 12 power switches. The proposed structure is composed of a switched-capacitor (SC) and a floating-capacitor-based (FCB) cell integrated into two isolated sub-units that have been series with each other as an hybridised platform. Herein, the relevant involved switches of the SC and FCB sub-units are modulated on the basis of an hybridised pulse width modulation technique which facilitates a significant degradation in the total power loss dissipation. An appropriate boosting feature with a self-charge balancing capability of all integrated capacitors, reasonable number of required semiconductor devices, higher efficiency and less complexity are other advantages of the proposed step-up 19-level inverter. To verify the precise performance of the proposed topology under different types of loading conditions, apart from the theoretical analysis, several simulation and experimental results will also be presented.

Harmonics elimination PWM based direct control for 23-level multilevel distribution STATCOM using differential evolution algorithm

This work describes the application of a soft computing technique—known as the differential evolution (DE) to implement the harmonics elimination pulse-width modulation (HEPWM) for the direct control of distribution static synchronous compensator (D-STATCOM). The main contribution of the work is the application of DE to solve eleven HEPWM switching angles to synthesize a 23-level cascaded multilevel voltage source inverter (MVSI). The key feature of this algorithm is the wide modulation index (MI) range that can be produced (i.e. 5.40–8.15p.u) with very small step size (0.01), while maintaining the total harmonic distortion (THD) of the MVSI output voltage below 5%. Furthermore, the utilization of high levels MVSI allows for the output voltage of the D-STATCOM to be sufficiently high, thus avoiding the use of step-up transformer. The correctness of the computed HEPWM angles is validated using single phase 23-level cascaded MVSI experimental rig. Then, the proposed method is compared to the phase-shifted PWM (PS-PWM) using a ±6.5 MVAr/11kV D-STATCOM modelled in MATLAB-Simulink. For the same switching frequency, the HEPWM switching results in a superior harmonics spectra and lower switching losses. Furthermore, if the switching frequency is fixed to a particular value, the size of the series coupling inductor can be reduced to at least half. Dynamically, the steady state value of the reactive current (iCq) is reached in less than one mains cycle when a transition from the full inductive to full capacitive modes is imposed.

Survey on Power Factor Correction in both Multilevel Inverter and Voltage Source Inverter

Survey on Power Factor Correction in both Multilevel Inverter and Voltage Source Inverter