Voltage Source Inverter Topology Research Articles

Capacitor sizing of three‐level neutral point clamped voltage source inverter for electric vehicles: Effects of modulation and motor characteristics

AbstractA three‐level neutral point clamped (3L‐NPC) voltage source inverter (VSI) topology can be advantageous in electric vehicles with a high DC‐link voltage and a high switching frequency. A bulky DC‐link capacitor is not an option; thus, the DC‐link capacitor's sizing considering the traction system characteristics is an important design step. This paper investigates how the DC‐link capacitor size of a 3L‐NPC VSI gets affected by the combination of the interdependent characteristics of an electric drive, such as its power factor, modulation index, current, and fundamental frequency, with the effects of the modulation methods. Five pulse width modulation (PWM) methods, of which three of them have an active neutral point potential control, are compared in terms of their neutral point potential (NPP) oscillations. Then, the size of the DC‐link capacitor is determined for each PWM method so that the NPP ripple is kept under desired limits at all operating conditions. It is shown that both the modulation technique and the electric machine characteristics influence the capacitor size. For example, electric machine design modifications can introduce more than a 30% reduction in capacitor size. Finally, DC‐link and NPP oscillations with different PWM methods are experimentally validated in a scaled‐down 3L‐NPC inverter.

Power quality enhancement using a novel SAPF control scheme employing high selectivity filter

Abstract Severe issues such as degradation of power quality and efficiency have surfaced in past few years due to extensive use of power electronic converters for conversion and control in power system. The shunt active power filter (SAPF) has gained attention as a competent solution among researchers. However, most SAPF control schemes render ineffective results under non-ideal supply conditions. A novel single-phase p–q scheme based on high selectivity filter (HSF) for extraction of reference compensation currents is proposed in this paper. A three H-bridges (3HB) voltage source inverter (VSI) topology of SAPF is considered and its dc-link voltage is regulated using an Enhanced Bacterial foraging optimization (BFO) based PI controller. This topology along with the proposed SAPF control scheme can guarantee improved APF performance as each phase of the three-phase four-wire system can be controlled independently. Extensive investigations are carried out using MATLAB/Simulink simulations followed by real-time performance verification in Opal-RT Lab. The effectiveness is assessed in terms of current harmonics, excessive neutral current and current unbalance compensation. The results obtained with proposed scheme when compared with conventional three-phase and single-phase p–q schemes employing low-pass filters (LPF) yield remarkably superior results under ideal, distorted and unbalanced supply and unbalanced loading conditions.

Grid Interconnection Modeling of Inverter Based Resources (IBR) Plant for Transient Analysis

The increase in penetration levels of inverter-based resources (IBRs) is changing the dynamic performance of power grids of different parts of the world. IBRs are now being more and more integrated into the grid at a single connection point as an IBR plant. Due to the complex nature and dynamicity of each inverter model, it is not realistic to build and analyze full complex models of each inverter in the IBR plant. Moreover, simulating a large plant including detailed models of all the IBRs would require high computing resources as well as a long simulation time. This has been the main issue addressed in the new IEEE Std 2800-2022. This paper proposes a novel approach to model an IBR plant, which can capture the transient nature at the plant level, detailed IBR control at the inverter level, interactions of multiple IBR groups in a plant structure, and a collector system connecting the IBRs to the grid. The IBRs in the plant use a voltage source inverter topology combined with a grid-connected filter. The control structure of the IBR includes a cascaded loop control where an inner current control and outer power control are designed in the dq-reference frame, and a closed-loop phase-locked loop is used for the grid synchronization. The mathematical study is conducted first to develop aggregated plant models considering different operating scenarios of active IBRs in an IBR plant. Then, an electromagnetic transient simulation (EMT) model of the plant is developed to investigate the plant’s dynamic performance under different operating scenarios. The performance of the aggregated plant model is compared with that of a detailed plant model to prove the effectiveness of the proposed strategy. The results show that the aggregated EMT simulation model provides almost the same result as the detailed model from the plant perspective while the running time/computation burden is much lower.

A Non-singular Fast Terminal Sliding Mode Approach to Improve the Network Stability of Wind Rich Power Grids

The increased penetration of wind energy conversion systems (WECS) into the grid creates many challenges for maintaining grid stability, reliability and efficiency. This paper proposes an approach that integrates the robustness and fast convergence capability of non-singular fast terminal sliding mode control (NFTSMC) with the fast current support of static synchronous compensators (STATCOM) to improve the dynamic stability of wind energy systems during network disturbances. The NFTSMC control approach is designed for the inner current control loop of a STATCOM with voltage source inverter topology. Its main objective is to support both the active and reactive currents and thereby effectively regulate the system's frequency and bus voltage. The proposed approach was implemented to a WECS-based test microgrid subject to sudden load variations and mismatched disturbances. The obtained results confirmed its effectiveness in properly mitigating dynamic instabilities stemming from grid disturbances and maintaining the voltage and frequency within their rated values. Further comparison between the performance of the proposed NFTSMC and that of a standard SMC approach showed better performance and reduced chattering compared to the standard SMC.

A Novel Single-Stage Buck–Boost Inverter

Traditional nonisolated multilevel inverters based on the buck–boost principle usually have some disadvantage such as necessary dead time or capacitor precharging. To overcome these, a new transformerless single-stage buck–boost voltage source inverter topology and its control method are proposed. In addition, the proposed topology has greater advantages in cost and loss. In this letter, the topological characteristics and working mode of the inverter are analyzed, and a modulation scheme that can ensure the balance of the output capacitor voltage is designed. Finally, a hardware experimental prototype is built, and the proposed scheme is experimentally verified based on DSP TMS320F28335 and FPGA XC6SLX9-2TQG144C digital controller.

DC Current Harmonics Reduction in Multi-Inverter Topology

This letter presents a Space Vector Pulse Width Modulation (SVPWM) strategy for reducing the DC-link current harmonics in a multi– Voltage Source Inverter (VSI) topology with common DC-link bus. The DC current harmonic reduction is achieved by phase-shifting the PWM pattern of individual VSIs, with the inverters sharing the system total power. Simulation and experimental results are shown to validate the proposal.

Method for Deriving Transformerless Common-Ground Voltage Source Inverter Topologies

This article presents a method for generating a family of transformerless inverters with common ground, for the connection of photovoltaic or battery energy storage systems with the electrical grid. Using the proposed method, four common-ground buck type inverter topologies are derived from bidirectional dc–dc converters based on buck–boost, SEPIC, zeta and boost–buck converters, which have in common the static gain given by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${D \mathord{/ {\vphantom {D {(1 - D)}}} } {(1 - D)}}$</tex-math></inline-formula> . The operation of each generated topology is explained and confirmed by computer simulation results. A comparative analysis between the four generated topologies and other transformerless common-ground inverters are included, considering the number of components, voltage ratings, output power, switching frequency, reported efficiency at rated power, and the requirement for filter insertion. Experimental results obtained in the laboratory, with tests performed on a nonoptimized experimental prototype are presented, for the topology based on the bidirectional zeta converter.

Novel Three-Phase H10 Inverter Topology With Zero or Constant Common-Mode Voltage for Three-Phase Induction Motor Drive Applications

A traditional two-level 3-φ voltage source inverter topology operated with remote state pulsewidth modulation (RSPWM) can achieve constant common-mode voltage (CMV) without using additional passive components. However, apart from the poor harmonic performance, this topology suffers from the drawbacks of reduced dc bus utilization, increased semiconductor requirement, and higher losses. To address these issues, this letter presents a new H10 inverter topology for two-level three-phase inverter applications. The proposed topology can achieve constant CMV or zero CMV without requiring additional passive components. Compared with the RSPWM approach, the proposed H10 topology has 50% higher dc bus utilization, superior harmonic performance, reduced semiconductor requirement, and lower losses. A comparison of the proposed topology with the existing two-level solutions for CMV reduction reveals that the proposed H10 has the lowest total switch voltage rating and phase current total harmonic distortion (THD), considering zero CMV performance. Various experimental results obtained from a laboratory prototype are presented to validate the theoretical claims.

Design and Development of a Multiphase Inverter for Automotive Applications

This work describes the development of a multiphase inverter that can operate as a platform for driving and testing electrical machines with up to 15 phases, in addition, it can operate with a fundamental frequency of up to 1 kHz and a switching frequency of 100 kHz. Therefore, a multiphase voltage source inverter (VSI) topology using SiC MOSFETs and approved components for automotive applications was designed and constructed. The developed platform is composed of independent power modules and a control module with technology that uses only a single microcontroller capable of generating all signals with pulse width modulation (PWM). To validate the inverter, experimental tests were carried out with a YASA (Yokeless and Segmented Armature) machine that can operate with 3, 5, or 15 phases and also with multi-star connections, one with three independent systems of five phases and another with five independent three-phase systems. Experimental results show that the inverter is capable of driving and testing multiphase machines with a wide variety of electrical connections using high fundamental and carrier frequencies. Therefore, the developed platform is an important tool that allows the testing of multiphase and multi-star electrical machines operating under the most diverse configurations and operating conditions.

Novel multi-device unified powerquality conditioner for powerquality improvement

This paper describes the customizable multi-device unified power-quality conditioner (MD-UPQC) is designed especially for multi-feeder distribution networks. The proposed MD-UPQC can exchange the power between the multi-feeders and proficiently mitigates all voltage-current associated power-quality problems, make sure to maintain balanced power-flow to consumers. At recent days, various manufacturers recommend the provision of multilevel inverters in mid-range customized compensation devices with desirable control schemes. In distinct, the 5-level diode-clamped multi-level inverter (DCMLI) is best suited for MD-UPQC over traditional 3-level voltage source inverter (VSI) topology for attaining enhanced features. In this paper, MD-UPQC has been proposed with three 5-level DCMLI modules interfaced as back-to-back with a common direct current (DC) capacitor. The simplified phase-dispositional modulation technique is easily assembled with proposed universal voltage-current reference controller for significant functioning of DCMLI-MDUPQC device. The operation and performance of proposed model and its control scheme is evaluated with MATLAB/Simulink computational tool, simulation results are presented.

Design and Hardware Implementation of an IGBT-Based Half-Bridge Cell for Modular Voltage Source Inverters

This article presents the design and hardware implementation of an IGBT-based half-bridge voltage source inverter (VSI) to be used as a basic cell to assemble VSIs of different topologies in modular ways. Herein, we have presented the design methodology and utilized techniques for reducing stray inductances and EMI radiation on the printed circuit board, as well as the way to calculate and select the main electronic components. For the design of the circuit board, local regulations for grid interconnection and international standards were considered in order to obtain a safe and reliable electronic power cell. The developed hardware was subjected to different tests using AC electric motors as loads to validate its design. Two VSIs topologies were evaluated: a single-phase two-level full-bridge inverter and a three-phase two-level inverter. The experimental results validated the theory and demonstrated the excellent performance, reliability, and high efficiency of the developed half-bridge power cell for modular VSIs.

New Three-Phase Current Reconstruction for PMSM Drive With Hybrid Space Vector Pulsewidth Modulation Technique

Current sensing techniques with reduced number of sensors attract a high interest from industry, for the possibility of cost reduction and sampling mismatch reduction. This article puts forward a new single current sensor (SCS) method for a permanent magnet synchronous motor three-phase current reconstruction, with a novel hybrid pulsewidth modulation (PWM) technique introduced. This method is implemented by changing the position of SCS from dc bus to a current branch, and a modified space vector PWM technique is employed to realize the phase current reconstruction. Compared with traditional SCS control methods, the proposed method can relieve the measurement dead-zones at sector boundary region without introducing extra compensation algorithms. Besides, this method can be realized not only with a single hall-effect current sensor but also a single shunt resistor, which further expands the applications and increases the system reliability as well. This method is also available in other motor control with a two-level three-phase PWM voltage source inverter topology. The accuracy and feasibility of the proposed method is validated by the simulation and experimental results.

Performance comparison of series and parallel damped LCL filters using 5-level voltage source converter

The high harmonic content produced by conventional converters has resulted in the increased system size and cost, due to the need for large-sized low-order harmonic passive filters and cooling system requirement. Given that, multilevel inverters and special modulation techniques were developed to suppress or eliminate the low-frequency harmonics and the left behind high-order ones are eliminated using a high-frequency small-sized filter. Hence, this paper designs and compares the total harmonic distortion (THD) and efficiency values of three set of filters, namely LCL filter, LCL with series and parallel resistance on a novel five-level multilevel voltage source inverter topology. The novelty lies with the proposed inverter, which, apart from using a single direct current source, it can extend it elimination capability beyond the normal five level using the concept of multiple switching per step and an optimised selective harmonic elimination pulse width modulation. The converter can eliminate eleven lower-order odd nontriplen harmonics, hence making the 37th harmonic at 1.85 kHz to be the first dominant harmonic. At 2-kW loading, two of the filters have THD below 5%, therefore satisfying the IEEE 519 standard. The parallel resistance damped filter (LCL-P-R) has less THD value but poor efficiency due to the resistance introduced into the circuit. The study was carried out using PSIM and MATLAB software.

Review of Multilevel Voltage Source Inverter Topologies and Analysis of Harmonics Distortions in FC-MLI

We review the most common topology of multi-level inverters. As is known, the conventional inverters are utilized to create an alternating current (AC) source from a direct current (DC) source. The two-level inverter provides various output voltages [(Vdc/2) and (−Vdc/2)] of the load. It is a successive method, but it makes the harmonic distortion of the output side, Electromagnetic interference (EMI), and high dv/dt. We solve this problem by constructing the sinusoidal voltage waveform. This is achieved by a “multilevel inverter” (MLI). The multilevel inverter creates the output voltage with multiple DC voltages as inputs. Many voltage levels are combined to produce a smoother waveform. During the last decade, the multilevel inverter has become very popular in medium and high-power applications with some advantages, such as the reduced power dissipation of switching elements, low harmonics, and low EMIs. We introduce the information about several multilevel inverters such as the diode-clamped multilevel inverter (DC-MLI), cascaded H-bridge multilevel inverter (CHB-MLI), and flying-capacitor multilevel inverter (FC-MLI) with Power systems CAD (PSCAD) simulation. It is shown that THD is 28.88% in three level FC-MLI while THD is 18.56% in five level topology. Therefore, we can decrease the total harmonic distortion adopting the higher-level topology.

Comparison of Different Multilevel Voltage Source Inverter Topologies on Induction Motor Energy Quality

Comparison of Different Multilevel Voltage Source Inverter Topologies on Induction Motor Energy Quality

Manitoba Inverter—Single-Phase Single-Stage Buck-Boost VSI Topology

The paper presents a new transformerless single-phase single-stage buck–boost grid-connected voltage source inverter (VSI) topology. The topology can achieve efficient power conversion with a wide input voltage range, number of magnetic devices reduction and low leakage current. The proposed VSI topology consists of high frequency semiconductors for shaping inductor currents, and low frequency semiconductors to form grid CL filter structure for different conditions. This CL filter uses the same buck–boost inductor, thus no additional line frequency inductor is required. Besides, common mode voltage, a main problem of transformerless grid-connected VSI, is mitigated, since the capacitor in the CL filter clamps the voltage between the grid and the bus terminal. The performance of the proposed VSI is experimentally verified. The results show that the proposed VSI guarantees sinusoidal output current and wide input voltage range, and has a good agreement with the theoretical findings.

Cascaded H-Bridge MLI and Three-Phase Cascaded VSI Topologies for Grid-Connected PV Systems with Distributed MPPT

Cascaded multilevel inverter topologies have received a great deal of attention for grid-connected PV systems. In this paper, three-cascaded multilevel inverter configurations are proposed for grid-connected PV applications. These are the three-phase cascaded H-bridge multilevel inverter topology, three-phase cascaded voltage-source inverter topology using inductors, and three-phase cascaded voltage-source inverter topology using coupled transformers. Distributed maximum power point tracking (MPPT) of PV modules using perturbation and observation algorithm is used for all presented topologies. In all presented configurations, each PV module is connected to one DC-DC isolated Ćuk converter for best MPPT achievement. Simulation is achieved by using the SIMULINK environment. The simulation results show that the three proposed topologies function well in improving the grid’s power quality. The grid currents are kept in phase with the grid voltage to ensure unity power factor, and the THD of the grid currents are within the acceptable range. The proposed topologies are experimentally implemented in the lab, and the switching pulses are generated with the help of the MicroLabBox data acquisition system. Comparing the three topologies according to the number of switches, voltage, and current stresses on switches and THD of the generated voltages and grid currents and according to the efficiency has been achieved in this paper, both experimentally and by simulation. The simulation and experimental results and comparisons are presented to verify the proposed topologies’ effectiveness and reliability.

Battery Losses In a MMC for BEVS Application

Objective:This paper analyses the Modular Multilevel Converter (MMC) topology, where each individual Sub Module (SM), in half bridge configuration, is directly fed by an elementary electrochemical cell.Methods:The aim is to investigate how the reference voltages influence the cells currents waveforms, determining how the active powers and the losses are distributed among the cells. Considering a 2-level Voltage Source Inverter (VSI) topology working in the same conditions, the ratio between the MMC total cells losses and VSI total cells losses is calculated. After showing the system architecture and mathematical model, the cells current waveform investigation is presented and detailed both for triangular and sinusoidal voltage reference waveform.Results:Finally, the results are critically discussed with particular focus on the comparison between the MMC and the VSI topologies.

A Survey of Multilevel Voltage Source Inverter Topologies, Controls, and Applications

Multi-level converters are every day attracting research interest due to it tremendous positive contributions they are making in the power industries. The converter has put hope in the minds of power electronic engineers that a time will come when it will break a record by providing an efficient means of utilizing the abundant renewable energy resources.&lt;strong&gt; &lt;/strong&gt;The paper presents a review of multilevel voltage source converters that are widely being used in engineering applications. It reports the technological advancements in converter topologies of Flying Capacitor (FC), Neutral Point (NPC) /Diode Clamped, and Cascaded H-Bridge (CHB) with their respective advantages and disadvantages. Recent customized/hybrid topologies of the three-phase multilevel inverter with reduced component count and switching combination are reported. The paper also reviewed different modulation techniques such as the multilevel converter carrier base PWM, Space Vector Modulation techniques (SVM), and Selective Harmonic Elimination method (SHE-PWM). Finally, various multilevel converters areas of application were highlighted. This review will expose the reader to the latest developments made in the multi-level topologies, modulation techniques, and applications.

PLL-Less Three-Phase Four-Wire SAPF with STF-dq0 Technique for Harmonics Mitigation under Distorted Supply Voltage and Unbalanced Load Conditions

This paper presents a non-iterative technique that generates reference current to manage operation of a three-phase four-wire shunt active power filter which employs a three-leg split capacitor voltage source inverter (VSI) topology. The proposed technique integrates together a self-tuning-filter (STF) and direct-quadrature-zero (dq0) principle (referred here as STF-dq0), allowing the controlled shunt active power filter (SAPF) to perform effectively under distorted source voltages and unbalanced load conditions. Unlike the previous technique developed based on the standard dq0 principle, the proposed technique does not require any service from a phase-locked loop (PLL) where two STFs are applied to separate harmonic and fundamental elements for the purpose of generating synchronization phases and reference current, respectively. Simulation work which includes connection of the SAPF circuits, design of control techniques and all the necessary assessments are conducted in MATLAB-Simulink platform. Performance achieved by the SAPF while utilizing the proposed technique is thoroughly investigated and benchmarked with that demonstrated by the SAPF while using the standard dq0 technique, to evaluate the inherent advantages. Exhaustive simulation results are provided and thoroughly discussed to support design concept, effectiveness, and benefits of the proposed technique.