Voltage Slope Research Articles

In Operando Visualization of Cation Disorder Unravels Voltage Decay in Ni-Rich Cathodes.

Despite the high energy density of Ni-rich layered-oxide electrodes, their real-world implementation in batteries is hindered by the substantial voltage decay on cycling, which mainly originates from bulk and surface structural degradation. Here, in operando observation of cation disorder, a major origin of structural degradation, reveals the voltage decay mechanism in Ni-rich cathode. Viewed along [1 1-0] and [110] orientations by scanning transmission electron microscopy, it is demonstrated that transition metal (TM) migration gives rise to the drastic fluctuation of interlamellar spacing and NiO bond length, but almost exerts no influence on atom site in ab plane. Density functional theory calculations reveal that the fluctuation of the NiO bond length triggers voltage decay via lifting the energy level of the antibonding (3dz2 -2p)* orbits. Broadening bands by a shorter NiO bond increase the voltage slope of battery, which will reduce the accessible Li capacity within the stable voltage range of the electrolyte. Furthermore, a collaborative path of TM migration triggered by oxygen vacancy is verified to account for the TM migration. The finding provides insights into new chemistry to be explored for developing high-capacity layered electrodes that evade voltage decay.

Ambipolar Deep-Subthreshold Printed-Carbon-Nanotube Transistors for Ultralow-Voltage and Ultralow-Power Electronics.

The development of ultralow-power and easy-to-fabricate electronics with potential for large-scale circuit integration (i.e., complementary or complementary-like) is an outstanding challenge for emerging off-the-grid applications, e.g., remote sensing, "place-and-forget", and the Internet of Things. Herein we address this challenge through the development of ambipolar transistors relying on solution-processed polymer-sorted semiconducting carbon nanotube networks (sc-SWCNTNs) operating in the deep-subthreshold regime. Application of self-assembled monolayers at the active channel interface enables the fine-tuning of sc-SWCNTN transistors toward well-balanced ambipolar deep-subthreshold characteristics. The significance of these features is assessed by exploring the applicability of such transistors to complementary-like integrated circuits, with respect to which the impact of the subthreshold slope and flatband voltage on voltage and power requirements is studied experimentally and theoretically. As demonstrated with inverter and NAND gates, the ambipolar deep-subthreshold sc-SWCNTN approach enables digital circuits with complementary-like operation and characteristics including wide noise margins and ultralow operational voltages (≤0.5 V), while exhibiting record-low power consumption (≤1 pW/μm). Among thin-film transistor technologies with minimal material complexity, our approach achieves the lowest energy and power dissipation figures reported to date, which are compatible with and highly attractive for emerging off-the-grid applications.

Low Temperature and High Pressure Oxidized Al2O3as Gate Dielectric for AlInN/GaN MIS-HEMTs

Low temperature (LT) and high pressure oxidized (HPO) Al2O3 is investigated as a gate dielectric for AlInN/GaN MIS-HEMTs. The time and temperature of the oxidation process was optimized for best performance. X-ray photoelectron spectroscopic (XPS) studies confirmed the near complete oxidation of Al to form Al2O3. MIS-HEMTs with 7 nm thick LT-HPO Al2O3 showed six orders reduction in gate leakage current and five orders improvement in ${I}_{D,ON}$ / ${I}_{D,OFF}$ ratio compared to the reference HEMT. Also, these MIS-HEMTs proved to be significantly better than HEMTs in terms of maximum drain current, subthreshold slope and off-state breakdown voltage. Reliability studies under constant voltage stress conditions show that the threshold voltage variation is within acceptable limits. Interface trap charges were estimated with the help of dynamic capacitance dispersion technique. The improved current collapse in MIS-HEMTs over HEMTs indicates the good quality of the interface between the dielectric and barrier layer.

An AMOLED Pixel Circuit With a Compensating Scheme for Variations in Subthreshold Slope and Threshold Voltage of Driving TFTs

This article proposes an active-matrix organic light-emitting diode (AMOLED) pixel circuit for mobile displays with high resolution to improve the image quality of the display panel. The proposed pixel circuit, which consists of six low-temperature polycrystalline silicon thin-film transistors (TFTs) and two capacitors, compensates for variations in the threshold voltage (Vth) and subthreshold slope (SS) of driving TFTs at low gray levels. Such compensations are achieved by extending the compensation time in the diode-connection scheme, resulting in a reduction in the OLED current error (OCE) of the proposed pixel circuit. In addition, the proposed pixel circuit connects two capacitors in parallel to the gate node of the driving TFT, thus increasing the total storage capacitance value in a given capacitor area in the emission phase, resulting in a reduction in voltage distortion at the gate node. Moreover, the OCEs caused by the IR drop of ELVDD and the crosstalk due to parasitic capacitances are thoroughly investigated and analyzed. The measurement results of the proposed pixel circuit show that the OCEs at the 64th and 128th gray levels are reduced from ±3.5 and ±6.5 to ±2.0 and ±0.8 LSB, respectively, by extending the compensation time from 6.5 to 195 $\mu \text{s}$ . Therefore, the proposed pixel circuit is highly suitable for mobile AMOLED displays requiring high image quality.

Using the Hexagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments

This paper describes an experimental comparative study of the matching between conventional (rectangular gate shape) and Diamond (hexagonal gate geometry) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) technology and exposed to different X-rays Total Ionizing Doses (TIDs). The results indicate that the Diamond layout style with alpha () angle equal to 90˚ for MOSFETs is capable of boosting the device matching by at least 17% regarding the electrical pa-rameters studied (Threshold Voltage and Subthreshold Slope) as compared with the conventional MOSFET counterparts, considering that they present the same gate area, channel width, bias conditions and for the same TID. This is due to the Longitudinal Corner Effect (LCE). Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) present in the structure of Diamond MOSFETs. Therefore, the Diamond layout style can be consid-ered an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS inte-grated circuits (ICs) applications.

Implementation of PSO MPPT Technique for Wind Energy Conversion Systems

One major advantage of renewable energy is that it is sustainable and will never run out. They provide clean energy because they are non-pollutant and non-contributor to greenhouse effects and global warming. Renewable energy facilities generally require less maintenance than traditional generators. Their fuel being derived from natural and available resources reduces the costs of operation. The proposed PSO algorithm uses the dc current as the perturbing variable. The algorithm detects sudden wind speed changes indirectly through the dc-link voltage slope. The voltage slope is also used to enhance the tracking speed of the algorithm and to prevent the generator from stalling under rapid wind speed slow down conditions. The proposed method uses two modes of operation: A PSO mode with adaptive step size under slow wind speed fluctuation conditions, and a prediction mode employed under fast wind speed change conditions. The dc-link capacitor voltage slope reflects the acceleration information of the generator, which is then used to predict the next step size and direction of the current command.

Dispersion effects in on‐state resistance of lateral Ga 2 O 3 MOSFETs at 300 V switching

Static characterisation and fast switching processes of lateral β-Ga2O3 metal oxide semiconductor field-effect transistors (MOSFETs) are presented. The investigated transistors with 10 mm gate width and 6 µm gate drain distance achieve on-state resistances of 5 Ω and saturation currents above 2.4 A. Hard switching in a double pulse test setup with an inductive load results in voltage slopes up to 65 V/ns at 300 V input voltage. After longer blocking times and higher DC voltages, a strong dynamic increase in on-state resistance occurs. Switching with an ohmic load and different load currents reveals only minor influence of the hot electron mechanism during the hard turn on. However, a clear influence of the turn-on gate drive voltage on the dynamic increase is observed, indicating a shift of the transfer characteristic due to charge trapping in the gate region.

Electrostatic-Doped Nanotube TFET: Proposal, Design, and Investigation with Linearity Analysis

In this paper, the proposed architecture of electrostatic doped based nanotube tunnel field-effect transistor (NT-TFET) has been discussed. The proposed architecture of NT-TFET structure showed improved performance as compared to nanowire TFET (NW-TFET) with the same physical parameters. To analyze the performance of electrostatic doped based NT-TFET, different parameters like device parameter, analog parameter and linearity parameter have been discussed. Electron/hole concentration, electric field, electric potential, energy band diagram and non-local band-to-band tunneling rate (BTBT) have been analyzed as several device parameters. The tunneling rate and tunneling area are greater in NT-TFET as compare to NW-TFET. Analog parameters include drain current, ON-current (ION), OFF-current (IOFF), ION/IOFF, intrinsic gain, output conductance, sub-threshold slope, and threshold voltage have been analyzed. The Drain current (IDS) of value 3*10−5 A/μm, OFF-current is of the order of ~ 10−19 and higher ION/IOFF current ratio of 2*1012 are obtained. The proposed architecture of electrostatic doped based nanotube TFET (NT-TFET) has improved the drain current, steep sub-threshold, OFF-current, and ION/IOFF current ratio.

Optimization of gate-bias stability and gas-sensing properties of triethylsilylethynyl anthradithiophene micro-strip field-effect transistors by incorporating insulating polymer

Abstract The control of the microstructure and patterning of 5,11-bis(triethylsilylethynyl)anthradithiophene (TES-ADT) film is essential for high-performance TES-ADT field-effect transistors (FETs) as a NO2 gas sensor. In this study, a binary blend film based on TES-ADT and insulating polymer was annealed by solvent vapor with patterned PDMS molds. The solvent-containing PDMS mold led to the TES-ADT crystallization under the phase-separation between TES-ADT and PMMA. This resulted in highly crystalline micro-strip films where TES-ADT and the insulating polymer were phase-separated on top and bottom, respectively. The micro-strip structures can have superior gas sensor performance because they have additional gas diffusion paths compared to non-patterned structures. Initial investigations to clarify morphology and microstructure of the films revealed that lateral phase separation got dominant with increasing the portion of the insulating polymer. The blended films were then used as the active layer in the FET-based gas sensors. The use of blended films instead of non-blended TES-ADT film in FETs is advantageous in reducing both the threshold voltage and subthreshold slope while compromising the field-effect mobility. The sensing response as the gas sensors is slightly lower in the blended TES-ADT FET than in the non-blended TES-ADT FET. However, the utilization of blended films significantly enhanced the bias-stress stability. Accordingly, a uniform baseline of the sensor performance was achieved in TES-ADT: insulating polymer blended FETs. This trend was in contrast to an abrupt decrease in the sensing signals of the non-blended TES-ADT FETs. The enhanced bias stability of the blended FETs was exhibited as a result of covering the silanol groups in SiO2 with a phase-separated insulating polymer. Our results provide a route for to the optimization of bias stability and response in TES-ADT micro-strip gas sensors through the application of a one-step blend technology.

Analytical determination of the turn-to-turn capacitances for the prediction of voltage peaks in a PWM-fed motor winding

The number of inverter-fed motors is increasing due to the good controllability of the motor and the meanwhile low acquisition costs. The steep voltage slopes of the converters lead to an uneven voltage distribution along the winding and thus to voltage peaks between the conductors, which stresses the insulation. The voltage distribution can be predicted by means of equivalent circuit diagrams, which take into account the capacitive coupling between the conductors. This paper presents a novel approach for an analytical determination of the turn-to-turn capacitances, which, in addition to the geometry and the placement of the conductors, considers the influence of materials with different permittivities.The conductors are simulated by means of line charges discretely placed inside the electrodes and receptor points attached to the conductor surfaces. The capacitances are determined by means of the Maxwell capacitance matrix. The method is validated by means of FEM simulations for different geometries and materials.

Avoiding overvoltage problems in three‐phase distributed‐generation systems during unbalanced voltage sags

During voltage sags, distributed generation systems must fulfil specific grid-code requirements for reactive current injection. This ancillary service can produce overvoltage problems in networks operating in unbalanced conditions when the amplitude of one of the phase voltages is higher than the others and a balanced reactive current is injected through large grid impedance. This study proposes a control scheme to avoid these overvoltage problems, thus reducing the risk of cascade disconnection that this incident may produce. The derivation of the control scheme starts from the flexible oscillating-power control, introduces the necessary modifications so that this control meets the grid-code requirements for current injection and combines it with a slope voltage control to achieve a good voltage regulation. A theoretical analysis is included to determine the expressions that quantify the voltage support characteristics of the proposal. Finally, selected experimental results are reported to validate the characteristics of the proposed control.

Toward an In-Depth Understanding of the Commutation Processes in a SiC MOSFET Switching Cell Including Parasitic Elements

This article provides in-depth insight into the commutation processes of high-speed SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s and investigates how they are influenced by various parasitic inductances. The switching dynamics of wide-bandgap power semiconductor devices are significantly larger compared to those of silicon devices. Therefore, the parasitic elements in the switching cell become increasingly important, as they limit the current and voltage slopes and cause oscillations. A thorough understanding of these effects is necessary for the design of highly efficient and integrated next-generation power electronic converters. However, the means of modeling hard-switched transitions, e.g., equivalent circuits, have not been adapted sufficiently compared to existing models on relatively slow-switching devices. This article presents the theory of commutation in high-speed semiconductor devices and outlines its key differences to traditional commutation models. These new insights are used to analyze the influence of parasitic inductances on the switching transitions. The theory is validated experimentally by double-pulse tests with variable parasitic inductances, performed on a test printed circuit board equipped with SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> s. The results are in good agreement with the theoretical findings.

Condition Assessment of Low Voltage Photovoltaic DC Cables under Thermal Stress Using Non-Destructive Electrical Techniques

The output power of the photovoltaic system is heavily dependent on the low voltage (LV) DC cables which are exposed to multiple stresses such as climatic, mechanical, electrical, and thermal stress, hence makes them more exposed to aging as compared to other components in the system. Accordingly, it is essential to monitor the state and know the real cause of the insulation degradation of the cable. The physio-chemical changes inside the insulation during service is attributed to the thermal stress, which the cable has to endure constantly. Traditionally, destructive test techniques have been adopted to study the aging phenomenon in the cable insulation, making them unsuitable for on-line condition monitoring. This research work has been aimed to study the degradation in LV photovoltaic DC cables under thermal stress by measuring the dielectric properties; complex permittivity, tanδ with the change in frequency and decay and return voltage slopes using extended voltage response method. The non-destructive diagnostic methods used are based on the phenomenon of polarization and conduction in the insulation material. The noteworthy change in the values of the imaginary part of permittivity, tanδ at low frequencies, and the overall decrease in the values of return voltage slope showed the change in the structure of the polymer matrix under the stress which was related to the cross-linking based chemical reactions. The results show that the techniques can be adopted for the on-line condition monitoring of the cable for the PV system and the dielectric parameters can be used to study the chemical and physical changes happening inside the material effectively.

High Energy Polyanion Cathode for K-Ion Batteries: KVPO4F

The development of high-energy cathode materials is crucial for the commercialization of emerging K-ion batteries (KIBs). While layered potassium-transition-metal-oxides (K x MO2, M=transition metals) have been investigated as potential cathodes, they have two intrinsic challenges. First, most of the K-layered oxides have K-poor composition (x<1.0 in K x MO2) and it leads practical difficulty of realizing KIBs because all the K ions should come from the cathode in a rocking-chair KIB.[1-6] Second, K-layered oxides have too high a voltage slope, resulting in low specific capacity and average voltage. Both the problems are attributable to much stronger K+-K+ interaction than Na+-Na+ and Li+-Li+ in the layered oxide structure.[2, 4] In contrast, polyanion cathodes can be better alternatives because 3-dimensional arrangement of K ions in their frameworks can significantly reduce the strength of effective interaction between K ions. As a result, polyanion cathodes can have K-rich (or K-stoichiometric) composition and high working voltage.In this work, we demonstrate that KVPO4F, a polyanion compound, is a high-energy cathode of KIBs. The KVPO4F cathode delivers a reversible capacity of ~105 mAh g−1 with an average voltage of ~4.3 V (vs. K/K+) (Figure 1), which is the highest among the K-cathodes developed up to date.[7] The specific energy (a gravimetric energy) of KVPO4F reaches ~450 Wh kg−1. Ex-situ X-ray diffraction characterization and ab-initio calculations demonstrate reversible multiple phase transitions of K x VPO4F during electrochemical cycling. K x VPO4F goes through various intermediate phases at x = 0.75, 0.625, and 0.5 upon K extraction and reinsertion. We further explain the role of oxygen substitution in KVPO4+xF1−x: the oxygenation of KVPO4F leads to an anion-disordered structure which prevents the formation of K+/vacancy orderings without electrochemical plateaus and hence to a smoother voltage profile.

New Digital Control Method for Improving Dynamic Response of Synchronous Rectified PSR Flyback Converter With CCM and DCM Modes

In order to improve the dynamic response of synchronous rectified primary-side regulation (PSR) flyback converter with CCM and DCM modes, a novel digital control method is proposed. In a dynamic process, when output voltage is detected to fluctuate greatly, two special working modes called light-to-heavy mode and heavy-to-light mode are introduced. The output capacitor will be quickly charged and discharged by an optimized control scheme to make the output voltage's dynamic fluctuation smaller. On the other hand, during the dynamic process control, for eliminating overshoot and oscillation when the output voltage returns to the reference voltage, the load is detected by the output voltage slope to determine the appropriate operating mode. With the proposed control method, the dynamic performance can be greatly improved. An field programmable gate array (FPGA)-controlled 20-V/5-A synchronous rectified PSR flyback converter is established to verify the proposed control scheme. In the prototype test, compared to the traditional multimode control, the undershoot voltage and overshoot voltage of the proposed control scheme are improved from 5.02 to 1.63 V and 3.15 to 1.73 V, respectively. The undershoot and overshoot recovery times are reduced from 83.43 to 1.79 ms and 40.32 to 1.85 ms, respectively.

EMI-optimized driver for high-frequency boost converter

For power-efficient electronic systems, the most suitable supply generation can be obtained with switch mode power supplies (SMPS). However, due to the inherent noise of SMPS, the electromagnetic emission (EME) is strongly affected by the switching activity, especially for applications with high EME requirements, e.g., in the automotive or medical field. One method of EME reduction influencing the high-frequency spectra content is the control of SMPS switching activity. This paper presents the integrated circuit (IC) implementation of a gate driver with adaptive current source control for a high-frequency boost converter with external switch based on the gate voltage slope information. The advantage of this suggestion concerning previous solutions is the ability to adjust gate driver currents based on the gate voltage slope information without the need for a complex digital computation scheme nor the need for digitized information about the switch current, switching node voltage or gate voltage. Also, the implementation eliminates the impact of the external parameters (temperature, input voltage, load current). The proposed concept was examined based on an 8 V output voltage, 500 kHz switching frequency boost converter.

The pulsed mode of negative DC corona in nitrogen at atmosphere pressure: Comparison with Trichel pulses in air

The pulsed mode of negative DC corona discharge in nitrogen at atmosphere pressure is investigated in needle–plate electrodes and compared with Trichel pulses in air. Current/voltage waveforms and time-resolved discharge pictures are recorded experimentally. It is found that the pulsed mode only appears in the presence of a large ballast resistor. The slope of pulsed mode time-averaged voltage–current curve is negative, in contrast to that of Trichel pulses. A transition of slope from negative to positive is tracked by increasing the oxygen fraction. The development of pulse discharge in nitrogen can be divided into three stages: (1) current raising stage, (2) current falling stage, and (3) charging stage. At stage 1, the current raises and forms a peak. The leading edge lasts for dozens of nanoseconds, similar to that of Trichel pulses in air. At stage 2, the voltage decreases monotonically, where a second hump can appear in the current waveform. Through intensified charge coupled device (ICCD) pictures and fluid model simulation, the hump is attributed to the further development of temporal glow discharge. The relative value and occurrence time of this hump are shown to be affected by a parallel capacitor, the space between electrodes, and the applied source voltage. At stage 3, the current remains constant, combined with a rise of gap voltage. Meanwhile, the stray capacitor is charged, which is analyzed by an equivalent circuit model. Through this experiment and simulation, we further clarify the mechanisms of pulses in nitrogen and differences between pulses in nitrogen and Trichel pulses in air.

Impact of process variability in junctionless FinFETs due to random dopant fluctuation, gate work function variation, and oxide thickness variation

In this paper, process variability such as random dopant fluctuation (RDF), work function variation (WFV), and oxide thickness variation (OTV) in 14 nm node junctionless (JL) FinFETs is investigated using the impedance field method (IFM). Effects of doping concentration, gate metal grain-related parameters, and device parameter scaling on RDF, WFV, and OTV induced variability are studied using the standard deviations of threshold voltage (σVth) and subthreshold slope (σSsub). As a result, we find that a relatively low doping concentration helps alleviate process variability. As average grain size increases, different mechanisms of σVth and σSsub degradation are analyzed for WFV and OTV induced variability. Compared to WFV and OTV, RDF is revealed as the most significant source of variability as devices scale down. It is observed that fin width (Wfin) and oxide thickness (tox) scaling leads to the reduction of RDF induced variability, whereas channel length (L) and fin height (Hfin) scaling results in aggravation of RDF, WFV, and OTV induced variability.

Reducing Common-Mode Voltage and Bearing Currents in Quasi-Resonant DC-Link Inverter

In this article, a concept of separation of an inverter-fed induction motor drive from its mains supply by two transistor switches inserted in the dc-link circuit is re-examined based on the proposed parallel quasi-resonant dc-link inverter (PQRDCLI). The objective of the article is to show an advantage of the proposed topology in limiting high-frequency common-mode voltage and bearing currents. In the laboratory setup, an induction machine was equipped with hybrid ceramic bearings and an insulated clutch to measure the shaft-to-frame bearing voltage and the shaft-grounding current. Experimental tests of the PQRDCLI confirm significant reduction of common-mode voltage and shaft-to-frame bearing voltage at dc-link zero voltage notches. By controlling the output voltage slopes, the shaft-grounding brush current and the ground leakage current are also reduced. The efficiency measurement and evaluation of the proposed topology, as compared with a two-level hard switched inverter, reveal comparable efficiency of around 95% and indicate loss distributions in both inverters.

Electronic circuit for measuring the current slope (dI/dt) and the post-arc current in gas-filled circuit breakers.

We have developed an electronic circuit for measuring the slope of the current near the current-zero crossing of an alternating current (dI/dt) and the post-arc current in gas-filled circuit breakers. The dI/dt and the post-arc current are measured in the current injection loop of a Weil-Dobke circuit (a synthetic test circuit that consists of a loop to generate a high short-circuit current at a relatively low voltage and a separate loop to generate high voltage after the short-circuit current is interrupted). The arc voltage and the dI/dt can be used to calculate the arc resistance of a breaker; the arc resistance and the post-arc current of the breaker provide important information about its interruption performance. The dI/dt and the post-arc current are measured with a commercially available high frequency coaxial shunt. The output voltage of the shunt is limited by using an electronic circuit to achieve better accuracy in the low current regime. The limited voltage signal is amplified with an operational amplifier that acts as a line driver. The prototype has a bandwidth of 12 MHz (+0.005 dB/-0.1 dB) and a propagation delay time of 10 ns. The nominal input voltage is ±50 V, and the maximum dU/dt (slope of the input voltage) that can be measured is 700 mV/μs with a linear range of ±0.6 V. Post-arc currents down to 200 mA can be measured.