Voltage Resolution Research Articles

Capacitance-controlled oscillator optimization for integrated capacitive sensors with time/frequency-based conversion

Technology scaling improves timing resolution, but diminishes voltage resolution, so time-/frequency-to-digital conversion is gaining popularity. In traditional amplitude-based converters, the sensor signal typically has to be pre- processed (amplified, filtered, etc) before feeding it to the converter. In the context of time-based converters, the conversion of the sensor to a frequency/time signal can be seen as pre-processing, after which it is fed to the time-to- digital converter. This paper focuses on the optimized conversion of a capacitive sensor (MEMS) to a time/frequency signal by using a Capacitance-Controlled Oscillator (CCO). In this way the sensor is directly converted to a usable time signal, so other pre-processing such as amplification and filtering can be avoided. Different oscillator topologies are investigated, designed in UMC130 CMOS technology, and compared to each other, based on key parameters such as tuning range, linearity, phase noise and power consumption. It is indicated which oscillators are suited for which applications.

A Hybrid Cascade Converter Topology With Series-Connected Symmetrical and Asymmetrical Diode-Clamped H-Bridge Cells

A novel H-bridge multilevel pulsewidth modulation converter topology based on a series connection of a high-voltage diode-clamped inverter and a low-voltage conventional inverter is proposed in this paper. A dc link voltage arrangement for the new hybrid and asymmetric solution is presented to have a maximum number of output voltage levels by preserving the adjacent switching vectors between voltage levels. Hence, a 15-level hybrid converter can be attained with a minimum number of power components. A comparative study has been carried out to present high performance of the proposed configuration to approach a very low total harmonic distortion of voltage and current, which leads to the possible elimination of the output filter. Regarding the proposed configuration, a new cascade inverter is verified by cascading an asymmetrical diode-clamped inverter, in which 19 levels can be synthesized in output voltage with the same number of components. To balance the dc link capacitor voltages for the maximum output voltage resolution as well as synthesize asymmetrical dc link combination, a new multi-output boost converter is utilized at the dc link voltage of a seven-level H-bridge diode-clamped inverter. Simulation and hardware results based on different modulations are presented to confirm the validity of the proposed approach to achieve a high-quality output voltage.

Nanoscale Quantitative Measurement of the Potential of Charged Nanostructures by Electrostatic and Kelvin Probe Force Microscopy: Unraveling Electronic Processes in Complex Materials

In microelectronics and biology, many fundamental processes involve the exchange of charges between small objects, such as nanocrystals in photovoltaic blends or individual proteins in photosynthetic reactions. Because these nanoscale electronic processes strongly depend on the structure of the electroactive assemblies, a detailed understanding of these phenomena requires unraveling the relationship between the structure of the nano-object and its electronic function. Because of the fragility of the structures involved and the dynamic variance of the electric potential of each nanostructure during the charge generation and transport processes, understanding this structure-function relationship represents a great challenge. This Account discusses how our group and others have exploited scanning probe microscopy based approaches beyond imaging, particularly Kelvin probe force microscopy (KPFM), to map the potential of different nanostructures with a spatial and voltage resolution of a few nanometers and millivolts, respectively. We describe in detail how these techniques can provide researchers several types of chemical information. First, KPFM allows researchers to visualize the photogeneration and splitting of several unitary charges between well-defined nano-objects having complementary electron-acceptor and -donor properties. In addition, this method maps charge injection and transport in thin layers of polycrystalline materials. Finally, KPFM can monitor the activity of immobilized chemical components of natural photosynthetic systems. In particular, researchers can use KPFM to measure the electric potential without physical contact between the tip and the nanostructure studied. These measurements exploit long-range electrostatic interactions between the scanning probe and the sample, which scale with the square of the probe-sample distance, d. While allowing minimal perturbation, these long-range interactions limit the resolution attainable in the measurement of potentials. Although the spatial resolution of KPFM is on the nanometer scale, it is inferior to that of other related techniques such as atomic force or scanning tunneling microscopy, which are based on short-range interactions scaling as d(-7) or e(-d), respectively. To overcome this problem, we have recently devised deconvolution procedures that allow us to quantify the electric potential of a nano-object removing the artifacts due to its nanometric size.

A High-Throughput On-Chip Variation Monitoring Circuit for MOSFET Threshold Voltage Using VCDL and Time-to-Digital Converter

A high-throughput on-chip monitoring circuit with a digital output is proposed for the variations of the NMOS and PMOS threshold voltages. A voltage-controlled delay line (VCDL) and a time-to-digital converter (TDC) are used to convert a small difference in analog voltage into a large difference in time delay. This circuit was applied to the transistors of W = 10µm and L = 0.18µm in a 16 × 16 array matrix fabricated with a 0.18-µm process. The measurement of the threshold voltage shows that the maximum peak-to-peak intra-chip variation of NMOS and PMOS transistors are about 31.7mV and 32.2mV, respectively, for the temperature range from −25°C to 75°C. The voltage resolutions of NMOS and PMOS transistors are measured to be 1.10mV/bit and 3.53mV/bit at 25°C, respectively. The 8-bit digital code is generated for the threshold voltage of a transistor in every 125ns, which corresponds to the 8-MHz throughput.

Very high voltage power supply system for the ring imaging Cherenkov detectors of the LHCb experiment

A modular power supply system is described, for use in the Ring Imaging Cherenkov Detectors of the LHCb experiment. The main characteristics of the supply are very good time stability and voltage resolution, full programmability, floating supplies, self protection and remote control. The choice of a commercial HV module with standard control inputs allows easy customisation to adapt our design to different requirements. The realisation shown here supplies voltages up to 20 kV with a maximum current of 0.5 mA and up to 32 channels on a single crate.

Switchable wiring for high-resolution electronic measurements at very low temperatures

Low-temperature transport measurements with high energy resolution require effective filtering of high-frequency input. The high dc resistance of standard RC filters results in considerable heat input and hampers measurements with high currents or voltages. We developed a wiring scheme that incorporates a commercial latching relay at very low temperature between two sets of wires. In our application one set of wires comprises a voltage divider and a high-Ohmic reference resistance at low temperature as well. The other set has low dc resistance and no voltage divider. Both sets are high frequency filtered with very robust and compact filters, though, for insuring effective damping at gigahertz frequencies. We demonstrate that with the first set, we obtain a voltage resolution of 6 microV and a current resolution of 100 pA, which is sufficient for the recording and analysis of multiparticle transport in superconducting point contacts. The second set is used for electromigration experiments on superconducting point contacts and allows application of currents up to 1 mA and voltages up to 20 V, while the sample is at 1 K. More versatile applications of the scheme are possible.

Multilevel, one‐phase inverter with unequal voltage distribution

PurposeThe purpose of this paper is to introduce a unique multilevel, one‐phase inverter (in the multiplied full‐bridge configuration, cascaded‐type) with unequal voltage distribution among the voltage levels.Design/methodology/approachNumerical and experimental results are discussed and the topology thereafter evaluated.FindingsUnequal voltage distribution among voltage stages of the converter leads to increase of the output voltage resolution while simplifying the converter construction and minimizing the power switch losses. Simplorer numerical analyses as well as test stand measurements were led in order to verify properties of the system. Using the voltage distribution in the proportion of 6/2/1 leads to improved utilisation of power switches used in the means of voltage, current and switching frequency. FFT analysis was implemented in order to explore the frequency domain properties of the control apparatus.Practical implicationsThe results allow improvement of power switch utilisation and output voltage resolution of cascaded, three‐stage multilevel converter topologies and voltage output filter optimisation for multilevel power electronic converters.Originality/valueA new concept of voltage distribution is provided and described, a dedicated DSP‐based control system was developed as well as a small‐scale converter prototype, test stand measurement results are provided.

Characterization of Fast Relaxation During BTI Stress in Conventional and Advanced CMOS Devices With $\hbox{HfO}_{2}/\hbox{TiN}$ Gate Stacks

We evaluate the performance of a novel fast characterization methodology for NBTI and PBTI measurements. We show that the use of a programmable PCI card in combination with linear current amplifiers provides the following means: (a) to perform short BTI stresses down to ~ 30 mus; (b) to perform fast sensing with delay times tdelay ~ 30 mus and a voltage resolution of ~ 1 mV; and (c) to use arbitrary programmable stress-and-sense sequences covering many decades in time. We used the fast PCI card-based measurement system for fast NBTI-relaxation measurements in SiON/poly-Si gate stacks, as well as for a systematic study of PBTI relaxation with HfO2/ TiN gate stacks. We show for the first time that the Vt relaxation after PBT stress in nFETS with HfO2/TiN gate stacks and the Vt relaxation after NBT stress in pFETs with SiON/poly-Si gate stacks exhibit strong similarities: We found the time dependence of both types of relaxation to exhibit to first order a log(t) dependence over seven orders of magnitude in time, suggesting that both phenomena are governed by charge removal by tunneling and that tunneling front-based modeling may be used to quantify the observations.

A Time-Based Bandpass ADC Using Time-Interleaved Voltage-Controlled Oscillators

In this paper, a bandpass analog-to-digital converter (ADC) based on time-interleaved oversampled ADC is introduced. Unlike previous delta-sigma bandpass ADCs that require accurate digital-to-analog converters and high-speed analog circuits, the proposed architecture provides bandpass function by time-interleaving first-order voltage-controlled-oscillator (VCO)-based ADCs. The use of VCO-based ADC has the advantage that its resolution is determined by the time resolution rather than the voltage resolution, thus making it attractive for future low-voltage CMOS processes. The performance of the proposed ADC is theoretically analyzed and simulated in ideal condition, as well as in nonideal condition, in the presence of nonlinearity, sampling clock jitter, and mismatch.

Study on the position resolution of resistive plate chamber

A prototype RPC detector with a 2-mm readout strip pitch has been built for research into its position resolution. After determining the optimal threshold and working voltage, the efficiency and position resolution of this prototype RPC detector have been studied carefully. Using cosmic-ray muons with different directions and incident positions, we have obtained less than 0.5-mm average statistical errors of position resolution for two different RPC readout structures: 1- and 1.7-mm readout strip widths. The results show that the RPC can also give high position resolution with very little variation from its traditional structure. This will lead to possible applications of the RPC in medical imaging and other domains.

70-GHz Effective Sampling Time-Base On-Chip Oscilloscope in CMOS

This paper examines a time-base measurement system for on-chip digitization. Undersampling, combined with single-path time-domain amplification and processing, is used to perform the embedded measurement in a time-efficient manner. The proposed system relies on simple circuit components while performing high-speed measurements. Additionally, ease of calibration with minimal silicon area overhead renders the system attractive from a design-for-test perspective. The circuit was implemented in a 0.18-mum standard digital CMOS process using a single 1.8-V supply. On-chip interconnect crosstalk generation with variable strength is included on chip for characterization, and successfully measured using the prototype chip. An effective 70-GHz sampling rate is experimentally obtained from the implemented on-chip oscilloscope, with a voltage resolution of 4 mV. The estimated static power dissipation is ~3.5 mW, with a total active area of 0.45 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> taken up by the associated test and calibration vehicles.

Characterisation of a semi 3-D sensor coupled to Medipix2

A 300 μ m thick semi-3D Si sensor has been characterised after bump-bonding to a Medipix2 read-out chip. The bonding quality measured using a 90Sr-source was found to be excellent ( > 99.9 % ) . Comparative measurements with respect to a standard planar 300 μ m Si sensor comprising IV-curves, depletion voltage and energy resolution have been performed. IV-curves and depletion voltages correspond to the values expected from the sensor geometry. The depletion voltage of the semi-3D sensor is significantly lower than the one of the planar sensor. The energy resolution of the semi-3D device has been found to be lower. The uniformity of the pixel response has been measured using a pulsed 1060 nm laser.

On-Chip Multi-Channel Monitoring for Analog Circuit Diagnosis in Systems-on-Chip Integration

A highly multi-channel on-chip signal monitor and off-chip waveform acquisition processor established analog circuit diagnosis against environmental disturbances in SoC. An array of 53 distributed probes followed by a single shared waveform acquisition kernel is embedded in a 0.18-μm CMOS experimental on-chip test bench. In combination with the off-chip processor materialized in FPGA and a host PC, fully automated on-chip waveform monitoring achieves high-throughput data acquisition of 300ms per sample point with adaptive 10-bit timing and voltage resolutions at a minimum LSB of 100ps and 400μV, respectively. Analog signals of interest in a 1.5-bit conversion stage of a pipeline ADC were evaluated in terms of their response to substrate noises that globally existed in a chip. On-chip diagnosis derives in-depth findings relating to dynamic, large-signal, and sensitive behaviors of analog circuits in a real SoC environment, far beyond simulations with inevitably limited capacity.

A Compact and Versatile Scanning Tunnelling Microscope with High Energy Resolution for Use in a 3He Cryostat

We present a simple design for a very-low temperature STM for the investigation of mesoscopic superconductors. The nonmagnetic microscope operates in a conventional 3He cryostat at T = 240 mK and in magnetic fields up to B = 1 T. Efficient filtering of all electrical lines at base temperature results in a voltage resolution ≈ 20μ V, which has been tested by measuring the differential conductance of superconducting aluminium. The successful operation in magnetic field is demonstrated by spectroscopy on superconducting aluminium as well as by demonstrating atomic resolution of HOPG.

All-Digital PLL With Ultra Fast Settling

A fully digital frequency synthesizer for RF wireless applications has recently been proposed. At its foundation lies a digitally controlled oscillator with sufficiently fine frequency resolution to avoid analog tuning. The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop filter. When implemented in highly scaled digital CMOS processes, the proposed architecture is more advantageous over conventional charge-pump-based phase-locked loops (PLLs) since it exploits signal processing capabilities of digital circuits and avoids relying on the fine voltage resolution of analog circuits. In this brief, we present novel techniques used in the all-digital PLL to achieve an ultra-fast frequency acquisition of <50 mus while maintaining excellent phase noise and spurious performance during transmission and reception. This approach has been validated and incorporated in commercial single-chip Bluetooth and Global System for Mobile Communications radios realized in deep-submicrometer CMOS

Low voltage and ultra-high resolution BSE imaging of ultramicrotomed, cross-sectional surfaces

Low voltage and ultra-high resolution BSE imaging of ultramicrotomed, cross-sectional surfaces

Characterization of the ADII‐33 diamond detector

Dosimetry characteristics of the ADII-33 diamond detector were investigated. Sensitivity, stability, bias voltage, hardening, dose rate, energy dependence, and spatial resolution were examined. Current generated in the detector was found to be proportional to the bias voltage applied to the detector with stability degrading as a function of the bias voltage. The average current increased with increasing bias voltage. The statistical fluctuation in current was less than 0.3% regardless of the applied bias voltage. The optimal bias voltage, at which the current uncertainty is negligible, was found to be 125+/-25 V. The detector was hardened up to 85 kGy without significant degradation in output signal. A sub-linearity in the current as a function of dose rate was observed when the dose rate varied from 600.0 to 11.1 cGy/min. A fitting parameter of delta=0.978 was observed in the power relationship of IinfinityDdelta. When comparing the diamond detector readings to corrected ion chamber readings over a wide energy range of electron beams, differences of only 0.2% were observed suggesting no energy dependence for electron beam. PDD curves for a 10 x 10 cm2 field for 6 and 20 MV photon beams measured with the diamond detector and the farmer type ion chamber were also compared and they closely agreed up to a depth of 14 cm. Beyond a depth of 14 cm, diamond detector starts to overestimate the PDD curve reaching difference of 1.90% and 1.0% at 18 cm depth for 6 and 20 MV, respectively, to those values measured with the ion chamber. The diamond detector presents slightly better spatial resolution than the Exradin A16 microchamber. We conclude that at the optimal bias voltage, this new diamond detector is stable and the uncertainties in the current will not affect its suitability for clinical use. If compared against a calibrated ion chamber to correct any energy and dose rate dependence and considering any radiation damage effect, this diamond detector can be used to measure absolute and relative dose.

Multichannel Data Acquisition System for Mapping the Electrical Activity of the Heart

Details of the electrical conduction pattern of the heart are revealed to the electrophysiologist when multichannel data are used for activation mapping. Commercial electronic systems are available for simultaneous acquisition of many surface electrograms; however, the cost of these systems may be prohibitive and they can be mostly inflexible for adaptation to other research projects. Furthermore, the hardware and software design is often proprietary. In this article we describe the in-house design and implementation of a 320-multichannel acquisition system for animal electrophysiologic research. Several modules comprise this system. The multichannel data are first preprocessed by amplification, filtering, and analog multiplexing. An algorithm for automatic adjustment of signal gains is implemented to maximize the voltage resolution and minimize noise pickup. Signals are then digitized, and sequenced to order the multichannel data and to add markers required for analysis. The digital data are streamed to archival storage media. Additionally, the electrocardiogram (ECG), blood pressure, and stimulus channel signals are stored simultaneously. Selected signals are then displayed in real-time for measurement and analysis and as a check of the system integrity. Examples of multielectrode arrays and surface recordings are provided. Costs for building such a system are estimated. Multichannel data acquisition systems that are designed and constructed in-house have several advantages over turnkey commercial systems, including the potential for considerable cost savings, flexibility in acquiring data, and the ability to subsequently add additional components.

Practical High-Resolution Programmable Josephson Voltage Standards Using Double- and Triple- Stacked&amp;lt;tex&amp;gt;$rm MoSi_2$&amp;lt;/tex&amp;gt;-Barrier Junctions

We have developed vertically stacked superconductor normal-metal-superconductor Josephson junction technology for the next-generation quantum voltage standards. Stacked junctions provide a practical way of increasing the output voltage and operating margins. In this paper, we present fully functioning programmable voltage standard chips with double- and triple- stacked MoSi/sub 2/ barrier Josephson junctions with over 100 000 junctions operating simultaneously on a 1 cm /spl times/ 1 cm chip. The maximum output voltages of the double- and triple-stacked chips were 2.6 V and 3.9 V, with respective operating current margins of 2 mA and 1 mA. A new trinary-logic design is used to achieve higher voltage resolution. Thermal transport in these high-density chips will be briefly discussed.

2.6-V High-Resolution Programmable Josephson Voltage Standard Circuits Using Double-Stacked MoSi&amp;lt;tex&amp;gt;$_2$&amp;lt;/tex&amp;gt;-Barrier Junctions

Using a new circuit design and double-stacked junction technology we have demonstrated fully functional high-resolution programmable voltage standard chips with 67 410 junctions that operate up to a maximum output voltage of 2.6 V. The circuit uses double-stacked junctions, where two junctions are fabricated in each stack, in order to increase the output voltage. We have also improved the voltage resolution at fixed frequencies 16-fold by using a circuit optimized for three voltage states and 128-fold below 2 V by oppositely biasing two large arrays whose junction counts differ by a single stack. These circuits operate over a frequency range from 14 GHz to 19 GHz with a 2-mA maximum operating current range.