Voltage Controlled Ring Oscillator Research Articles

A Compact, Low-Power, and Low-Jitter Fractional-N Phase-Locked Loop with a Single-Ended Ring Voltage-Controlled Oscillator in a 12 nm CMOS FinFET

PLLs with small areas, low power consumption, and low jitter are crucial for mobile applications. Hence, achieving a balance between the area, power consumption, and noise of a PLL is a significant issue. In this work, a compact, low-power, and low-jitter fractional-N PLL using Ring-VCO is introduced. In order to reduce area and power consumption, a single-ended Ring-VCO is implemented. Additionally, novel resistance matrixes are proposed to decrease phase noise. The resistor matrix creates 13 frequency tuning curves with close VCO gain and different initial frequencies, reducing the VCO gain and thus the overall noise while maintaining high tuning linearity. The proposed PLL is fabricated based on 12 nm FinFET technology with a 0.078 mm2 area. It achieves a 2.702 ps RMS jitter at 5.76 GHz while consuming 6.4 mW. Moreover, it maintains a low power consumption and a low RMS jitter across the entire frequency range.

An Energy-Efficient 12-Bit VCO-Based Incremental Zoom ADC with Fast Phase-Alignment Scheme for Multi-Channel Biomedical Applications

This paper presents a low-power, energy-efficient, 12-bit incremental zoom analog-to-digital converter (ADC) for multi-channel bio-signal acquisitions. The ADC consists of a 7-stage ring voltage-controlled oscillator (VCO)-based incremental ΔΣ modulator (I-ΔΣM) and an 8-bit successive approximation register (SAR) ADC. The proposed VCO-based I-ΔΣM can provide fast phase-alignment of the ring-VCO to reduce the interval settling time; thereby, the I-ΔΣM can accommodate time-division-multiplexed input signals without phase leakage between consecutive measurements. The SAR ADC also adopts splitting unit capacitors that can support VCM-free tri-level switching and prevent invalid states from the phase frequency detector with minimal logic gates and switches. The proposed ADC has been fabricated in a standard 180 nm standard 1P6M CMOS process, exhibiting a 67-dB peak signal-to-noise ratio, a 74-dB dynamic range, and a Walden figure of merit of 19.12 fJ/c-s, while consuming a power of 3.51 μW with a sampling rate of 100 kS/s.

SET sensitivity of a VCRO-based PLL for HL-LHC ATLAS HGTD

We report the characterization of the Single Effect Transient (SET) sensitivity of an analogue Phase Locked Loop (PLL) based on a Voltage Controlled Ring Oscillator (VCRO) under a proton beam. The clock generator is embedded in a front-end ASIC, namely ALTIROC designed in CMOS 130 nm, reading out Low-Gain Avalanche Diode (LGAD) matrices for the High-Luminosity Large Hadron Collider (HL-LHC). We detail the methodology developed to study such events that could degrade the targeted time resolution of 35 ps per hit. Observed SET-induced phase jumps allow the estimation of the total cross-section of the PLL. The results are extrapolated to the HL-LHC radiation conditions.

Novel six‐phase ring voltage controlled oscillator with wide frequency tuning range

SummaryThis paper presents more compatible three‐stage inverter‐based ring voltage controlled oscillators (VCOs) by modifying the current‐starved delay cell to oscillate with high tuning range. Unlike some ring structures in which extra transistors are used as current boosting to enhance the frequency tuning range, no extra elements are used in the proposed three‐stage VCOs for increasing the tuning range. Besides, a new method is introduced to couple two proposed ring VCOs for designing a six‐phase ring VCO. The coupling method can be generalized to some other ring VCOs to generate multiphase signals. The proposed circuits have wide frequency tuning ranges and show good noise performances. The proposed six‐phase VCO can oscillate from 1.62 GHz to 3.45 GHz, which illustrates 72.2% tuning range. The phase noise of the proposed VCO is −97.5 dBc/Hz at 1 MHz offset frequency. The circuit figure of merit is −181.5 dBc/Hz. The post‐layout simulation results of the proposed six‐phase VCO are provided based on the TSMC 0.18 μm CMOS process.

A Dual-Path Subsampling PLL With Ring VCO Phase Noise Suppression

This article presents a 2-GHz dual-path subsampling phase-locked loop (SSPLL) with ring voltage-controlled oscillator (VCO) phase noise suppression (PNS). In addition to the conventional subsampling charge pump (SSCP), a high-pass path from the subsampling phase detector (SSPD) to the low-pass filter (LPF) is implemented in the proposed SSPLL. Due to this dual-path architecture, a new in-band zero and pole are introduced into the open-loop transfer function (zero frequency is smaller than the pole frequency), which extends the open-loop unit-gain bandwidth without sacrificing the phase margin. Consequently, the phase noise contribution of the ring VCO is suppressed while the loop stability is ensured. Meanwhile, the phase noise contribution of the high-pass path is negligible compared to the reference and ring VCO’s contribution. Measurement results show that the SSPLL’s closed-loop bandwidth is extended to around 6 MHz with a reference of 20 MHz and the jitter is reduced by 1.34 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> (from 3.52 to 2.63 ps) with a maximum noise suppression of 6.5 dB at the 1.1-MHz offset. The PNS path consumes 0.16 mW and no delay line or calibration is needed, which results in a relatively high FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{PNC}}$</tex-math> </inline-formula> value of 40.5 dB.

Design and analysis of PVT tolerant hybrid current starved ring VCO with bulk driven keeper technique at 45 nm CMOS technology for the PLL application

This article introduces a novel approach of hybrid current-starved ring voltage-controlled oscillator (VCO) to overcome the challenges present in the Phase-locked loop (PLL) in high-frequency applications. In this, two novel VCO designs are proposed. The first design is the current starved pull-up sleepy ring VCO which offers improved frequency of oscillation and reduced phase noise. The second design utilizes a hybrid current starved ring VCO with the bulk-driven keeper technique which yields better results by reducing the power consumption and mitigating leakage current. The proposed circuit is analysed with various process corners and performs parametric analysis and Monte-Carlo analysis to verify the robustness of the circuit using Cadence Virtuoso tool with 45 nm gpdk library. The average power of the proposed −2 circuit is 7.38 µW, and it achieves an oscillation frequency of 6.965 GHz at 1 V supply. It has low phase noise of −121.49dBc/Hz at 1 MHz, and the output noise of −166.42 dB. The obtained figure of merit (FOM) is −185.95dBc/Hz. The proposed design exhibits a frequency tuning range of 92.8 %. The results clearly demonstrate that the proposed design is extremely tolerant to PVT (process, voltage, and temperature) variations making it well suitable for high-frequency PLL applications.

A Single-Chip Single-Antenna Radar for Remote Vital Sign Monitoring

This article proposes an effective way to use self-injection locking (SIL) in a radar system to detect human chest cavity movement for vital signs monitoring with minimal hardware. The proposed approach expands the idea of using a phase-locked loop (PLL) system as a demodulator and a single antenna, making the system more compact. The system includes on-chip dc offset cancellation for system initialization. This work investigates and compares an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$LC$</tex-math> </inline-formula> -based voltage-controlled oscillator (LCVCO) and a ring voltage-controlled oscillator (RVCO) in terms of primary sensitivity for motion detection and phase noise. A study of injection-locking of both the LCVCO and RVCO is also established. The study shows that the RVCO is superior to the LCVCO in terms of sensitivity while the phase noise does not differ significantly as the frequencies of interest are very small, i.e., heart rate and respiration are bandwidth-limited to a few hertz. To verify the proposed idea, a design of both systems, an LCVCO-based PLL and an RVCO-based PLL, was implemented in 65 nm CMOS technology at 1.5 GHz. The simulation and measurement results confirm the idea proposed: the RVCO shows better performance across all metrics, e.g., higher sensitivity by 4 dB, lower power consumption by 30%, and reduced area (almost half) compared to the LCVCO.

Performance study of wide tuning range and low phase noise differential ring voltage control oscillators (DRVCO) for wireless communications

This article mostly emphasize on the study and characterization of CMOS differential ring voltage control oscillator (DRVCO). There are numerous DRVCO with various kinds of delay cells which are associated with the parameters like oscillation frequency, wide tuning range, power utilization & area for the applications like wireless and communications systems. These results shows less phase noise and extensive tuning range can be accomplished by the dual control voltages across the delay stages. This article helps the designers to choose the suitable DVCRO for their definite applications.

Voltage controlled ring oscillator with large frequency range and variable duty cycle

Voltage controlled ring oscillator with large frequency range and variable duty cycle

An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies

This paper presents a design automation methodology for ring voltage-controlled oscillators (RVCOs) with their realistic and physical characteristics captured. With multiple sets of input constraints such as target frequency, phase noise, and control voltage range, the proposed algorithm automatically finds the design candidates that satisfy the target constraints, by running iterative post-layout simulations with auto-generated layouts and testbenches. The number of post-layout simulations is significantly reduced by the backtracking algorithm that observes the simulation results and determines the search direction. The proposed algorithm is applied to generate RVCOs in 40-nm planar and 7-nm FinFET technologies for DDR5 applications, and it turns out the proposed methodology produces sets of design parameters that meet the target specification in multiple technologies.

A heterogeneous integrated self-powered IoT system of an LiNbO3 device and CMOS readout circuit

A self-powered IoT system with high integration, robust performance, and adaptability to complex environments is one of the current research hotspots. Piezoelectric materials have been widely used in pressure sensing and energy harvesting due to their stable output electrical properties. In this paper, a heterogeneous integrated self-powered IoT system based on a lithium niobate (LiNbO3) piezoelectric device and CMOS readout circuit is proposed. The piezoelectric sensor is fabricated by depositing electrodes on the surface of the 36°Y-cut LiNbO3 piezoelectric material. The sensitivity of the fabricated sensor is 17.5 mV/kPa. Based on the CSMC 0.18 μm BCD process, a ring voltage-controlled oscillator (VCO) based on the current starvation delay element is designed as a wireless data transmission unit. The oscillator has two tuning terminals, which can realize frequency alignment and voltage threshold judgment. Using photolithography, wire bonding technology, etc., the heterogeneous integration of the Si-based chip and LiNbO3 piezoelectric device is realized. The experimental results show that below 1.8 V supply voltage, the oscillation frequency of the chip increases with the increase in the control terminal voltage, which provides an idea for solving the energy supply problem of an IoT system. This system has great application potential in the field of self-powered sensing.

A 50-ps Gated VCRO-Based TDC With Compact Phase Interpolators for Flash LiDAR

This article describes a small footprint, low power gated voltage-controlled ring oscillator (VCRO)-based Time-To-Digital converter (TDC) for Flash Light Detection and Ranging (LiDAR) applications. A group of compact local phase interpolators (PIs) are used to improve the resolution, which is highly area-saving and compatible with in-pixel TDC structure. A non-reset operation mode is introduced to increase the linearity by taking advantage of the dynamic element matching (DEM) property. The proposed TDC has been fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> HV-CMOS technology in a 32 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times32$ </tex-math></inline-formula> array, achieving a resolution of 50 ps. A Phase Lock Loop (PLL) is adopted to track the process, voltage, and temperature (PVT) variations and make the resolution tunable. A power-saving analog buffer is used to distribute the stable control voltage to all the in-pixel TDCs. Measurements show a good linearity performance and array uniformity (a deviation of only 0.89 ps), making it suitable for Flash LiDAR applications.

Design of a high‐performance advanced phase locked loop with high stability external loop filter

For this task, an improved phase locked loop (PLL) was developed using a more sophisticated phase-frequency detector with multiband flexible dividers that provide enhanced frequency resolution, a better spectrum, and a better output signal. Great timing jitter was the problem for the old PLL designs because of the unbalanced frequency transfer function caused by the voltage-controlled oscillator and noise introduced by increases in supply voltage. A new design was suggested for the phase-frequency detector (PFD) such that PLL lock times are reduced while maintaining a low level of phase jitter. This way, they used fewer transistors, used less power, and had lower propagation holdup and smaller size compared to static PFDs. Additionally, forward ring voltage-controlled oscillator may improve the resolution of frequency and phase variation errors owing to supply noise by balancing driving force ratios in the feed-forward and feedback paths. Additionally, there is a dynamic sense flexible divider with several bands for separating special divisions (divide-by-47 and divide-by-48) that lacks a few extra flip-flops which save considerable power and improves the frequency difficulties of the multi-band divider. The advanced phase locked loop (ADPLL) has integrated phase and frequency errors, where the ADPLL excels. The supply noise is decreased by three reference clock cycles and the effect is that the measurement of jitter is better. Advanced Phase Locked Loop oscillates at frequencies ranging from 500 MHz to 4 GHz. A root mean square jitter of 1.29 ps is observed at 1 GHz. Our PLL is rated at 92.1-μW, with power used at 0.31 mW/GHz. The aim of this article is to design a 180 mm CMOS-based PLL circuit with a 400 MHz clock and a 0.65 V supply at a fast, dynamic phase frequency detector for resolution and stability.

Design of a fully integrated VHF CP‐PLL frequency synthesizer with an all‐digital defect‐oriented built‐in self‐test

This paper presents the design of an on-chip charge pump phase-locked loop (CP-PLL) with a fully digital defect-oriented built-in self-test (BIST) for very-high frequency (VHF) applications. The frequency synthesizer has a 40–100 MHz tuning range and uses a ring voltage-controlled oscillator for frequency synthesis. The PLL exhibits a phase noise of −132 dBc/Hz at 1 MHz and consumes 1.8 mW on a 3 V supply. The BIST implementation uses fewer external input or output, is capable of efficient fault diagnosis, and is compact, posing a low area overhead. The integrated circuit design was realized in the AMI 0.6μ complementary metal-oxide-semiconductor process.

Low-Power Low-Complexity FM-UWB Hybrid Transceiver for Communication and Ranging

A frequency-modulated ultrawideband (FM-UWB) hybrid transceiver, with a high system reuse ratio up to 90%, is fabricated in the 65-nm CMOS process for both short-range wireless communication and high-resolution radar ranging. The radio frequency (RF) front-ends (RFFEs) based on module stacking and current reuse achieve significant RF power savings of about 30% and 50% for the transmitter and the receiver (RX), respectively. The presented IF zero-crossing delay discrimination benefits a high radar resolution less than 1 cm. A multimode relaxation oscillator (OSC) for the reconfigured triangular subcarrier generation and a dual-path ring voltage-controlled oscillator (VCO) for the linear FM, stacked by a wideband push–pull power amplifier (PA), generate an FCC-compliant UWB signal. An active balun embedded low-noise amplifier (LNA) and two symmetric-detuning band-passed filters (BPFs) are stacked with the bandwidth extension to linearly demodulate the UWB FM signal. Experimental results show that the 3.75–4.25-GHz hybrid transceiver has an energy efficiency of 1.9 nJ/bit with an active area of 0.7 mm2 and a power dissipation of 1.9 mW and achieves the RX sensitivity of −71 dBm and the transmitted power of −14.1 dBm, with a bit error rate (BER) of 10−4 at a distance of 4 m under the data rate (DR) of 0.1–1.0 Mbps. The transceiver also achieves the noise figure (NF) of 4.8 dB and the phase noise of −78.6 dBc/Hz at 1-MHz offset frequency.

Supply less sensitive ring voltage-controlled oscillator for microwave L-band frequencies

PurposeThe primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.Design/methodology/approachFirst, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.FindingsThis work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm2 compared to contemporary designs.Originality/valueThe proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent.

A Programmable Multiple Frequencies Clock Generator With Process and Temperature Compensation Circuit for System on Chip Design

This article presents a programmable multiple frequencies clock generator with a process and temperature compensation circuit design. The proposed clock generator can achieve a stable and wide frequency range output for a single input frequency by using digital control codes as well as process and temperature compensation mechanisms. In our approach, the first step is to adjust the duty-cycle of the input clock by using a digitally controlled pulsewidth modulator (DCPWM) to generate an output clock signal with a duty-cycle of 20% to 80%. Second, the various duty-cycle clock outputs of the DCPWM are integrated by the duty-cycle-to-voltage converter to generate analog voltage signals to control the succeeding voltage-controlled ring oscillator (VCO). Through the use of various control voltages, different VCO output frequencies are generated. Finally, by using the process and temperature compensation circuit, the proposed clock generator can provide a stable and wide frequency range. The proposed chip is fabricated in a 180-nm CMOS process and has an output frequency range of 35–138 MHz at a supply voltage of 0.9 V. At 120 MHz, the power dissipation and rms jitter are 224.3 μW and 7.84 ps, respectively. The active area of the chip is 0.62 mm × 0.76 mm.

A 500 kHz to 150 MHz Multi-Output Clock Generator Using Analog PLL and Open-Loop Fractional Divider with 0.13 μm CMOS

Clocks are widely used in multimedia and electronic devices, and they usually have different frequency demands. This paper presents the design of a multi-output clock generator using an analog integer-N phase-locked loop (PLL) and open-loop fractional dividers. The PLL based on a three-stage ring voltage-controlled oscillator (VCO) is used to transform the lower frequency reference into a high-frequency intermediate clock (600 MHz–900 MHz). Then, relying on the open-loop fractional divider, a wide frequency range of 500 kHz to 150 MHz can be generated. Due to the open-loop control characteristic, the clock generator has instantaneous frequency switching capability. In addition, phase-adjusting circuits added to the divider greatly improved the jitter performance of the output clock; its RMS jitter is 5.2 ps. This work was conducted with 0.13 μm CMOS technology. The open-loop divider occupies an area of 0.032 mm2 and consumes 7.7 mW from a 1.2 V supply.

A 1.15-mW Low-Power Low-Complexity Reconfigurable FM-UWB Transmitter

A 1.15-mW 3.75–4.25-GHz frequency-modulated ultrawideband (FM-UWB) transmitter (TX) is fabricated in 65-nm CMOS, with digitally reconfigurable subcarrier frequencies, UWB bandwidth, and radio frequency (RF) frequency band. Low-complexity submodules are utilized with significant power savings. An ultralow-current hybrid module is for bandgap reference (BGR) and power-ON reset (POR), and a single-ended crystal oscillator (XO) generates a 12-MHz clock reference. A dual-path ring voltage-controlled oscillator (VCO) conducts linear RF FM, followed by a push–pull power amplifier (PA) for 100-kb/s wireless data transmission. A differential relaxation oscillator (OSC) is for subcarrier generation, and an intermittent dual-mode frequency calibration loop ensures system robustness. Experimental results show that the presented FM-UWB TX successfully generates an Federal Communications Commission (FCC)-compliant UWB signal, with an energy efficiency of 11.5 nJ/bit and an active area of 0.21 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> from a 1-V supply. The 2.25- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> hybrid BGR and POR achieves a temperature coefficient of 32 ppm/°C, a line regulation of 2.3%/V, a supply-ramp-rate-tolerant power-ON, and brown-out function. The 40- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> XO features a low-frequency inaccuracy of 4 ppm/V. The 40- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> relaxation OSC provides the reconfigured two-frequency shift keying (FSK) triangular amplitude and frequency. The 2.79–5.18-GHz 0.6-mW ring VCO is capable of providing the phase noise performance of −77 dBc/Hz at the 1-MHz offset, followed by the 0.45-mW PA having the output power higher than −14 dBm and the peak power-added efficiency (PAE) of 29.6%. All these benefit low-power low-cost TX implementation, where the carrier and subcarrier frequencies are calibrated by an intermittent digital loop with omitted power dissipation.

Comprehensive Analytical Comparison of Ring Oscillators in FDSOI Technology: Current Starving Versus Back-Bias Control

Back-bias control is a new degree of freedom brought by fully-depleted silicon-on-insulator (FDSOI) CMOS technologies, which can be used to control the oscillation frequency of voltage-controlled ring oscillators (VCROs). The resulting VCRO architecture is called a back-bias-controlled oscillator (BBCO). This paper compares it with the conventional current-starved ring oscillator (CSRO) topology in terms of power consumption and phase noise figure-of-merit (FoM), while taking practical design constraints of process-voltage-temperature (PVT) robustness and frequency tuning range into account. The proposed comprehensive analysis takes advantage of relevant and compact analytical models, as well as extensive pre-layout simulation results. The comparison is made at four different target oscillation frequencies, which are representative of frequency synthesis for WiFi/Bluetooth/LPWAN wireless communications and of clock generation for smartphone/Internet-of-Things processors: 300 MHz, 868 MHz, 2.45 GHz, and 5.18 GHz. In 28-nm FDSOI technology, the results demonstrate that BBCOs can intrinsically reach 1.69 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.63\times $ </tex-math></inline-formula> lower minimum power consumption and slightly better FoM values than CSROs.