Phase Noise Of Voltage-controlled Oscillator Research Articles

K-band CMOS voltage-controlled oscillator using tail current modulation with half-output frequency

A CMOS voltage-controlled oscillator (VCO) using half-oscillation frequency signals as switched biasing is proposed to simultaneously improve the phase noise and DC-to-RF conversion efficiency. The effect of the flicker noise caused by the tail current source, which is the dominant factor of the VCO phase noise, can be reduced by the modulation using the half-frequency signals of the output. The conversion efficiency of the proposed VCO is improved by the leakage of the second harmonics of the modulation signal at the drain node of the current source, which is the same as the oscillation frequency of the VCO, thereby increasing the output power. The differential half-frequency signals are generated in the frequency divider, designed with the current-mode logic for minimizing the effect of parasitic components at high-frequency operation, which constitutes the frequency synthesizer without any additional circuits. The proposed VCO with the divider was fabricated on the size of 0.4 × 0.61 mm2 using a 65-nm CMOS process, including all pads. The measurement results showed a tuning range of 11.2% at the K-band and a phase noise of –109.86 dBc/Hz at the 1-MHz offset. The peak output power and DC-to-RF efficiency were measured to be 0.95 dBm and 16.64%, respectively, at the supply voltage of 1.2 V. A figure of merit of the proposed VCO was calculated to be –188.03 dBc/Hz.

180 nm NMOS voltage-controlled oscillator for phase-locked loop applications

<p>The voltage-controlled oscillator (VCO) is the primary device in the phase-locked loop (PLL) to produce the local oscillator frequency. The excessive phase noise of VCOs is the primary cause of PLL performance loss. This paper proposes the design and optimization of low phase noise and low power consumption for a 180 nm N-channel metal-oxide semiconductor NMOS VCO for PLL applications with P-channel metal-oxide semiconductor PMOS varactors and spiral inductors. At 2 V supply voltage, the optimized NMOS VCO has a power consumption of 21 mW, a phase noise of -130 dBc/Hz at 1 MHz offset and a total harmonic distortion (THD) of 3.9%. The proposed design is verified by PSpice simulations. A new criterion is proposed for optimizing NMOS LC oscillators.</p>

A Low-Voltage Class-D VCO with Implicit Common-Mode Resonator Implemented in 55 nm CMOS Technology

This paper presents a Class-D voltage-controlled oscillator (VCO) with a hybrid switch capacitor array. In order to reduce the phase noise of the oscillator, an implicit common-mode resonance technique is used, effectively suppressing the conversion of power supply noise to VCO phase noise. At the same time, due to the use of a transformer in implicit common-mode resonance technology, the core area of the oscillator is not significantly increased compared with the traditional Class-D VCO. Based on the proposed technology, the proposed VCO exhibits lower phase noise compared to the original Class-D VCO, and also has many different advantages compared to low-voltage VCOs produced by similar technological processes. The proposed VCO was designed in a 55 nm CMOS process. Simulation results show that this VCO has an operating range from 4.36 to 6.43 GHz, resulting in the frequency tuning range (FTR) of 38.5%. In addition, its power consumption was 3.46 mW, the phase noise at 4.36 GHz was −124.2 dBc/Hz@1 MHz, and the figure of merit (FoM) was −191.6 dBc/Hz@1 MHz. The core area is 0.15 mm2.

A Ka -Band Colpitts–Clapp VCO With 30% Tuning Range and High Output Power

This letter presents a systematic design strategy for SiGe bipolar voltage-controlled oscillators (VCOs) with a wide tuning range (TR). As a proof of concept, a Colpitts–Clapp VCO with an ultra-wide continuous TR of 30.2% and center frequency of 35.5 GHz is presented in a 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> SiGe BiCMOS technology. The measured phase noise of the free-running VCO at 1 MHz offset is better than −99 dBc/Hz over the entire TR. A peak output power of 12.6 dBm is measured with 19.8% of DC-RF efficiency. The VCO exhibits a figure-of-merit (FoMPT) of −193 dBc/Hz. To the best of the authors’ knowledge, the proposed VCO shows the best FoMPT, highest output power and DC-RF efficiency among the reported SiGe VCOs at this frequency range.

Design of 50-GHz Low Phase Noise VCO Employing Two-Branches DGS Resonator in 0.18-μm CMOS Technology

This letter presents a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> -band low phase noise voltage-controlled oscillator (VCO) design using a novel integrated two-branches defected ground structure (DGS) resonator in 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> complementary metal-oxide-semiconductor (CMOS) technology. The proposed DGS resonator is realized in the top metal layer (M6) which has not only a higher quality factor than its predecessors but is also effective to reduce the length of interconnects. The measured carrier frequency and phase noise are 49 GHz and −122.05 dBc/Hz (−102.58 dBc/Hz) at 10-MHz (1-MHz) offset frequencies, respectively. The VCO core consumes 5.5 mW of dc power from the dc supply, which results in a figure of merit (FoM) of −189 dBc/Hz. The proposed VCO using the two-branches DGS resonator may give an alternative low-cost solution for designing a high-performance VCO or frequency synthesizer at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> -band and beyond.

A Broadband 77/79 GHz Transmitter With Dual VCOs and Third Harmonic Signal Extraction in a 28 nm CMOS Technology

A broadband 77/79 GHz transmitter (TX) front-end for automotive long range radar (LRR) and short range radar (SRR) applications is presented in this paper. To achieve the best system performance one new TX architecture with two specifically designed voltage controlled oscillators (VCOs) is implemented in a 28 nm CMOS technology. Furthermore, the degradation of the VCO phase noise due to the TX integration is analyzed in detail and solutions to minimize the impacts are proposed and verified. Experimental results of a 20 GHz push-push VCO1 measured at the 77 GHz TX output show a continuous tuning range of 4.75 GHz, a coarse tuning range of 3.2 GHz and an average phase noise of −100 dBc/Hz @ 1 MHz, while a 26 GHz VCO2 with third harmonic signal extraction achieves a continuous and coarse tuning range of 7.5 GHz and 4.2 GHz with an average phase noise of −96 dBc/Hz @ 1 MHz at 79 GHz TX output. Moreover, a record pushing performance of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\rm {&lt;\!\pm }$</tex-math></inline-formula> 100 MHz/V at 77/79 GHz TX output has been achieved according to the authors’ best knowledge. The whole TX chip consumes about 860 mW from a single 2.1 V supply while providing more than 16 dBm output power over the whole frequency band.

A Low-Phase-Noise CMOS Ring Voltage-Controlled Oscillator Intended for Time-Based Sensor Interfaces

We describe in this paper an improved ring voltage-controlled oscillator (VCO) showing a reduced phase noise while allowing an extended frequency tuning range. The phase noise improvement is obtained through the minimized contribution of tuning line noise while maintaining a rail-to-rail swing. The proposed VCO features a linear tuning characteristic yielding a constant gain over a wide range of operating frequencies. An analytical model is extracted resulting in closed-form expressions for the VCO phase noise. Employing the analytical expressions, the contributed noise and phase noise limitations are fully addressed, and all the effective factors are investigated. The VCO prototype was fabricated in a 0.35 μm CMOS process. It consumes 0.903 mW from a 3.3 V supply when running at its maximum oscillation frequency of 9.37 MHz. The measured VCO phase noise is -147.57 dBc/Hz at 1 MHz offset from the 9.37 MHz oscillation frequency, and the circuit occupies a silicon area of 0.005 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . A state-variable Matlab® model of a time-based sensor interface has been developed including the impact of phase noise nonideality. The system-level simulations demonstrate that the PLL-based sensor interface exploiting the proposed VCO characteristics can achieve a 88.43 dB signal-to-noise ratio over a 1-kHz bandwidth.

Phase noise optimization of integrated ring voltage-controlled oscillators by metaheuristics

&lt;abstract&gt;&lt;p&gt;Real applications of integrated circuits (ICs) require satisfying strong target specifications, which challenge is focused on trading off specifications that are in conflict, i.e. improving one characteristic can degrade other(s). This is the case of designing a ring voltage-controlled oscillator (VCO) using IC nanometer technology, with the goal to accomplish a wide frequency and voltage-control tuning range, low silicon area, among others. For real ring VCO applications, an open challenge is guaranteeing minimum phase noise, which is in conflict with main dynamical characteristics when maximizing frequency range, voltage-control range, gain, and minimizing silicon area and power consumption. To cope with these design problems, we show the minimization of the phase noise of a ring VCO applying two metaheuristics, namely: Differential evolution (DE) and particle swarm optimization (PSO), which have the ability to handle constraints that are relevant to generate optimal solutions. The results show that both DE and PSO are effective in the optimization of the ring VCO. The comparison of the best phase noise results obtained with DE (-129.01 dBc/Hz @1MHz) and PSO (-124.67 dBc/Hz @1MHz) algorithms, not only show that the DE solution being lower by 4.34 dBc/Hz with respect to the best solution provided by PSO, but also it is quite satisfactory in contrast to similar works. Finally, the optimized ring VCO characteristics are compared herein with several designs considering a figure of merit, gain, frequency and voltage-control ranges.&lt;/p&gt;&lt;/abstract&gt;

A 92 fs&lt;sub&gt;rms&lt;/sub&gt; jitter frequency synthesizer based on a multicore class-C voltage-controlled oscillator with digital automatic amplitude control

This letter presents a frequency synthesizer based on a multicore Class-C voltage-controlled oscillator (VCO) with a digital automatic amplitude control (AAC) loop. A novel digital tail current estimation is adopted to mitigate the risks of unexpected VCO oscillation failure, due to current shortage during frequency calibration. Meanwhile, a digital amplitude recalibration is proposed to provide continuous amplitude control, avoiding noise distortion resulted from amplitude drift after a conventional disposable amplitude calibration. The digital AAC loop achieves a specific VCO amplitude with good stability and introduces no extra noise. Fabricated in a 28 nm CMOS process, the presented frequency synthesizer occupies an active area of 1.43 mm2. By measuring a 3 GHz carrier, the open loop VCO phase noise is -132 dBc/Hz at 1 MHz offset and the close loop root mean square jitter is 81 fs.

Frequency‐domain behavioural noise analysis of analogue phase‐locked loops

A frequency-domain approach for phase noise analysis of integer-N multiplier-type phase-locked loops (PLLs), based on the conversion matrix approach, is introduced that can take all non-linearities in the loop into account. It can also characterise all kinds of power spectral densities and correlation between variables and all aspects of phase noise-to-phase noise or amplitude noise-to-phase noise (AN–PN) conversions. The noise transfer between various sidebands is also taken into account. This is especially important for characterising the folding of the voltage-controlled oscillator's phase noise which results in the phase noise augmentation at small frequency offsets. Unlike the linear phase-domain models, the stochastic phase noise local maxima at large offset frequencies are also accurately characterised. Giving the phase/amplitude noise spectra of various PLL blocks, this approach computes the resulting output phase noise spectrum. The validity of the new approach is verified by comparing its results with those of a numerical time-domain stochastic simulation. The proposed method has far much faster runtimes, independent of the time constants in the system, compared to the corresponding time-domain methods that allow a convenient simulation-based design of PLLs especially at radio frequencies.

A new tail-switching superharmonic multiphase LC-VCO

PurposeMultiphase and quadrature voltage-controlled oscillators (QVCOs) play key roles in modern communication systems and their phase noise performance affects the performance of the overall system. Different studies are devoted to efficient quadrature signals generation. This paper aims to present a new low-phase noise superharmonic injection-locked QVCO.Design/methodology/approachThe proposed QVCO is comprised of two identical inductor-capacitor circuit (LC)-voltage-controlled oscillators (VCOs) in which second harmonics, with 180° phase shift, are injected from one core VCO to the gate of tail current source of the other VCO via a coupling capacitor. Using second harmonics with high amplitude will switch the tail from the inversion to the accumulation, and therefore, flicker noise is reduced. Also, because of the use of lossless and noiseless coupling elements, that is, coupling capacitors, and also because of the existence of an inherent high-pass filter, the proposed LC-QVCO has a good phase noise performance.FindingsThe introduced technique is designed and simulated in a commercial 0.18 µm radio frequency complementary metal oxide semiconductor (RF-CMOS) technology and 10 dB improvement of close-in phase noise is achieved (compared to the conventional method). Simulation results show that the phase noise of the proposed QVCO is −130.3 dBc/Hz at 3 MHz offset from 5.76 GHz center frequency, while the total direct current (DC) current drawn from a 0.9-V power supply is 4.25 mA (figure of merit = −190.2 dBc). Monte Carlo simulation results show that the figure of merit of the circuit has a Gaussian distribution with mean value and standard deviation of −189.97 dBc and 0.183, respectively.Originality/valueThis technique provides a new simple but efficient superharmonic coupling and noise shaping method that reduces close-in phase noise of superharmonic multiphase VCOs by switching of tail transistors with 2 ω0 (second harmonic of oscillation frequency). No extra devices such as area-consuming transformer or additional power-hungry oscillator are used for coupling.

A Modified Darlington-Based Class-C VCO With Simultaneous Optimization of Phase Noise/FoM in GaAs Technology

This letter presents a modified Darlington-based (DB) class-C voltage-controlled oscillator (VCO) topology which achieves a cooptimization of phase noise and figure of merit (FoM) in GaAs technology. Both the Darlington pair and noise shifting techniques are introduced to improve the phase noise in class-C VCOs. Balanced and differential architectures are used to absorb the strength of both the Colpitts and class-C VCO topology with a simple trick of two cascaded stages in the VCO core, which elevates the VCO driving capability with no degradation of power efficiency. In addition, the startup conditions and capacitive feedback factors are derived and compared in both mathematical and simulation manners, which proves the superiority of the topology. The proposed VCO is fabricated in a GaAs bipolar high electron mobility transistor (BiHEMT) technology which demonstrates a frequency range of 2.76–2.91 GHz with a current consumption of 9.5 mA at 5 V supply, a phase noise of −138.6 to −135.9 dBc/Hz at 1 MHz offset from the carrier, an output power of −3.06 to −4.18 dBm, and a peak FoM of −191.2 dBc/Hz at 1 MHz offset. To the best of the authors’ expertise, the proposed DB class-C VCO achieves both exceptional phase noise and FoM, which far outweigh that of the existing GaAs.

Low-Noise Voltage Controlled Oscillator with Coupled Microstrip Lines of Different Lengths

Introduction. Coupled two- or three-wire microstrip lines are often used to reduce a phase noise of voltage-controlled oscillators (VCOs). Unfortunately, the phase noise was not optimized depending on the lengths of a three-wire coupled microstrip lines. Aim. For the three-wire coupled microstrip structure, the task of determining of the optimal lengths of its stabs was set. The stabs were corresponded to the reduced phase noise of the selected VCO. Materials and methods . In the oscillator example, the resonator model with three electromagnetically coupled microstrip lines was studied. Herein the second line from the first and the third from the second line differed by the same physical length. The widths of the first and of the third lines were the same, and their coupling clearances with the second line were the same too. On the one hand, in this three-wire microstrip line short-end modes with a common ground electrode were implemented. On the other, at the ends of the first and of the third lines open-end modes were implemented. The free end of the second line is line input. Results. For the considered oscillator, the basic formulas for calculating its frequency-setting elements and resonator model parameters were obtained. By these formulas the estimation of base contours impedances for two oscillators with three-coupled microstrip lines of the same and different lengths, and also for the oscillator using a two-coupled microstrip line was given. For comparison, the proposed VCO near the optimal difference in the three-wire line microstrips lengths had the base contour impedance phase steepness 2...4 times greater, as well as its modules graphs had the width 4...10 times less. Conclusion. In comparison with the known VCOs, the possibility of obtaining lower phase noise spectrum levels at 6...10 dB/Hz in the designed oscillator with the calculated lengths of the selected three-coupled line microstrips was experimentally confirmed.

A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology

This paper aims at designing a digital approach based low jitter, smaller area and wide frequency range phase locked loop (PLL) to reduce the design efforts and power which can be used in System-on-chip applications for operating frequency in the range of 0.025–1.6[Formula: see text]GHz. The low power, scalable and compact charge pump is proposed which reduces the overall power consumption and area of proposed PLL. A frequency phase detector (PFD) based on inverters and tri-state buffers have been proposed for the PLL. It is fast which improves the locking time of PLL. Also, pseudo-differential voltage controlled oscillator (VCO) is designed with CMOS inverter gates. The inverters are used as phase interpolator to maintain the phase difference of 180∘ between two outputs of VCO. Also, the inverters are used as variable capacitors to vary the frequency of proposed VCO with control voltage. It demonstrates the good phase noise performance enabling proposed PLL to have low jitter and wide frequency range. All the major blocks like PFD, charge pump and VCO are designed using digital gate methodology thus saving area and power and also reduce design efforts. Also, these digitally designed blocks enable the PLL to have low jitter small area and wide range. The proposed PLL is designed in a 0.18-[Formula: see text][Formula: see text]m CMOS technology with supply voltage of 1.8[Formula: see text]V. The output clocks with cycle-to-cycle jitter of 2.13[Formula: see text]ps at 1.6[Formula: see text]GHz. The phase noise of VCO is [Formula: see text]137[Formula: see text]dBc/Hz at an offset of 100[Formula: see text]MHz and total power consumed by the proposed PLL is 2.63[Formula: see text]mW at 1.6[Formula: see text]GHz.

A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

K-Band Low Phase Noise VCO Based on Q-Boosted Switched Inductor

In this article, the development of the K-band low phase noise voltage-controlled oscillator (VCO) based on Q-boosted switched inductor is presented. Compared with the conventional switched inductor, the eddy current will be decreased using a 2-turn secondary coil, and then the dissipated power from the switch on-resistance will also be decreased, leading to a boosted inductor Q at switch ON-state. The equivalent inductance, quality factor, and self-resonance frequency at switch ON/OFF states are analyzed and derived. For comparison, K-band VCOs have been designed and fabricated in a 130nm BiCMOS process with the Q-boosted and conventional switched inductors. Measured results show that the phase noise has been typically improved by 2–5dB at 100 kHz and 1 MHz offset at switch ON-state, using the Q-boosted switched inductor.

28-GHz CMOS VCO With Capacitive Splitting and Transformer Feedback Techniques for 5G Communication

This paper presents a 28-GHz low phase noise voltage-controlled oscillator (VCO) in a 65-nm CMOS process for 5G communication applications. With the capacitive splitting and transformer feedback techniques, theoretical analysis and simulations are undertaken for the proposed oscillator, proving that its negative G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> can be enhanced over the interested frequency range and reduced at the harmonic frequencies. Moreover, the proposed oscillator startup performance is analyzed, and its tank quality factor, transient and phase noise performance are simulated. With 4-bit switch capacitors and varactors, the proposed VCO achieves a tuning range from 25.7 to 29.7 GHz, consuming 10.8 mW from a 0.9-V supply voltage. With a wideband common-source buffer, the output signal power is around 1 dBm. At 26.5 GHz, the proposed VCO achieves low phase noise of -105.8 dBc/Hz at 1-MHz offset and -130 dBc/Hz at the 10-MHz offset, respectively.

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

Numerical Jitter Minimization for PLL-Based FMCW Radar Systems

This paper presents a time-domain simulation methodology for FMCW radar systems using a noisy phase-locked loop (PLL) for frequency generation. A stochastic differential equation (SDE) is employed to describe both the high-pass filtered noise in the voltage-controlled oscillator (VCO) and the low-pass filtered input noise. The exact solution of this SDE is used to directly generate the PLL phase on a discrete time grid from VCO phase noise, input noise level, and loop bandwidth. For both heterodyne and homodyne radar systems using an overdamped PLL, the simulated steady-state phase noise spectra and rms phase jitter are in excellent agreement with an analytical model. The phase jitter and rms error in a target distance measurement are minimized by optimizing the PLL loop bandwidth as a function of the target distance. The non-stationary phase noise during a linear FMCW sweep is calculated in the time domain from circuit parameters. The PLL settling time is minimized by optimizing the loop filter capacitance for a given ramp slope.

Performance Limitation Analysis of Highly-Digital Time-Based Closed-Loop Sensor-to-Digital Converter Architectures

This brief presents the theoretical and comparative analysis of two major time-based architectures for sensor interfaces. Both use a voltage-controlled oscillator (VCO) to achieve a highly-digital scalable implementation. The first architecture is based on a phase-locked loop, while the second one is count-based. Both systems are closed loop to efficiently mitigate the VCO nonlinearity. They show inherent first-order quantization noise shaping thanks to the use of an oscillator and phase detection. The two systems having a different working principle leads to different VCO requirements in terms of gain linearity (V-to-f or V-to-T linearity). Formulas are derived to predict the maximum SQNR for both architectures. Equations for the achievable maximum SNR taking into account the VCO phase noise are also derived, since this is the limit to the SNR in practical implementations. State-variable-based simulation results are presented, confirming the theoretical analysis and emphasizing the different design trade-offs and practical considerations.