Design Of Voltage Controlled Oscillator Research Articles

Design and Simulation of VCO for RF Transceivers with Low Power, Low Phase Noise and Wider Tuning Range using Silterra 130nm CMOS Technology

The performance of low-power transceivers is required to meet stringent specifications for an advanced wireless radio frequency (RF) application. The design topology in this paper is simulated to meet the specifications and operation of VCO for low power, low phase noise and wide tuning range in complementary metal oxide semiconductor (CMOS) 130nm technology for RF transceivers. The relationship between the phase noise, power consumption and frequency turning range is fully analyzed to further improve the performance of the voltage-controlled oscillator (VCO). The architecture of the VCO employs two sets of symmetrical cross-couple split NMOS and PMOS with biased current sources operating in the triode region, and a resonator tank that achieves the desired low phase noise performance of about -110 dB/Hz at a tuning range of 4.1 to 4.5 GHz with a supply of 0.9 V. The control of the DC bias point reduces the conduction angle, which improves the current efficiency, power consumption and phase noise. The topology generates sufficient –gm for the oscillator incorporation to mitigate the start-up issue of the VCO. At the center frequency of 4.38 GHz, the VCO serves as a promising solution for improving low power and low phase for wireless communication systems and RF transceiver applications. The design consumes a very low power of 0.138 mW, achieves a phase noise of -110.53 dBc/Hz at 1 MHz offset, and a figure of merit (FoM) of -191.90 dBc/Hz.

Design and Analysis of a Low-Voltage VCO: Reliability and Variability Performance.

This paper investigates an adaptive body biasing (ABB) circuit to improve the reliability and variability of a low-voltage inductor-capacitor (LC) voltage-controlled oscillator (VCO). The ABB circuit provides VCO resilience to process variability and reliability variation through the threshold voltage adjustment of VCO's transistors. Analytical equations considering the body bias effect are derived for the most important relations of the VCO and then the performance is verified using the post-layout simulation results. Under a 0.16% threshold voltage shift, the sensitivity of the normalized phase noise and transconductance of the VCO with the ABB circuit compared to the constant body bias (CBB) decreases by around 8.4 times and 3.1 times, respectively. Also, the sensitivity of the normalized phase noise and transconductance of the proposed VCO under 0.16% mobility variations decreases by around 1.5 times and 1.7 times compared to the CBB, respectively. The robustness of the VCO is also examined using process variation analysis through Monte Carlo and corner case simulations. The post-layout results in the 180 nm CMOS process indicate that the proposed VCO draws a power consumption of only 398 µW from a 0.6 V supply when the VCO frequency is 2.4 GHz. It achieves a phase noise of -123.19 dBc/Hz at a 1 MHz offset and provides a figure of merit (FoM) of -194.82 dBc/Hz.

Systematic Design of a Pseudodifferential VCO Using Monomial Fitting

Digital integrated electronics benefits from its higher abstraction level, allowing optimisation methods and automated workflows. However, analogue integrated circuit design is still predominantly done manually, leading to lengthy design cycles. This paper proposes a new systematic design approach for the sizing of analogue integrated circuits to address this issue. The method utilises a surrogate optimisation technique that approximates a simple monomial function based on few simulation results. These monomials are convex and can be optimised using a simple linear optimisation routine, resulting in a single global optimal solution. We show that monomial functions, in many cases, have an analytic relation to integrated circuits, making them well suited for the application. The method is demonstrated by designing a 14 MHz pseudodifferential voltage-controlled oscillator (VCO) with minimised current consumption and is manufactured in a 180 nm process. The measured total current matches the predicted and is lower than that for other similar state-of-the-art VCOs.

Design and analysis of PVT tolerant hybrid current starved ring VCO with bulk driven keeper technique at 45 nm CMOS technology for the PLL application

This article introduces a novel approach of hybrid current-starved ring voltage-controlled oscillator (VCO) to overcome the challenges present in the Phase-locked loop (PLL) in high-frequency applications. In this, two novel VCO designs are proposed. The first design is the current starved pull-up sleepy ring VCO which offers improved frequency of oscillation and reduced phase noise. The second design utilizes a hybrid current starved ring VCO with the bulk-driven keeper technique which yields better results by reducing the power consumption and mitigating leakage current. The proposed circuit is analysed with various process corners and performs parametric analysis and Monte-Carlo analysis to verify the robustness of the circuit using Cadence Virtuoso tool with 45 nm gpdk library. The average power of the proposed −2 circuit is 7.38 µW, and it achieves an oscillation frequency of 6.965 GHz at 1 V supply. It has low phase noise of −121.49dBc/Hz at 1 MHz, and the output noise of −166.42 dB. The obtained figure of merit (FOM) is −185.95dBc/Hz. The proposed design exhibits a frequency tuning range of 92.8 %. The results clearly demonstrate that the proposed design is extremely tolerant to PVT (process, voltage, and temperature) variations making it well suitable for high-frequency PLL applications.

A PVT tolerant low power wide tuning range differential voltage controlled oscillator design in 90 nm CMOS technology

This paper presents a three-stage low power and wider tuning range differential ring-oscillator with dual control voltages. This design permits lower tuning gain using dual control voltage (VTUNE 1 and VTUNE 2) to achieve high operation frequency. The dual voltage control enables a large bias current into the circuit. The proposed DRO has been implemented in 90 nm CMOS technology, whose performance results show a very high output frequency range which includes lower frequency band (LFB) and higher frequency band (HFB) from 0.007 GHz to 13.48 GHz. This DRO shows power consumption from 0.001 mW to 2.307 mW and phase noise of −92.27 dBc/Hz @ 1MHz offset. The figure of merit (FoM) for this DRO turns out to be −179.98 dBc/Hz. In addition, process corner analysis, Monte Carlo analysis, temperature sweep analysis, and stability analysis has been performed to find the robustness of the circuit.

Supply less sensitive ring voltage-controlled oscillator for microwave L-band frequencies

PurposeThe primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.Design/methodology/approachFirst, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.FindingsThis work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm2 compared to contemporary designs.Originality/valueThe proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in comparison with other designs. The obtained results are preserved to the fullest extent.

Heuristic Approach in Ring Voltage Controlled Oscillator Design for V.C.O. Based Analog to Digital Conterters

Abstract This paper introduces a procedure that relies on Computer Aided Design tools (industry compatible SPICE simulator and MATLAB) to get a first rapid design solution for a ring voltage controlled oscillator (VCO) that can be further analyzed and optimized for usage in a VCO based analog to digital converter (ADC). Due to the fact that linearity is a key performance metric of an ADC a special attention will be given to this characteristic during the design and for this matter control mechanism will be analyzed. To exemplify the design procedure two different delay cell topologies (simple inverter and pseudo-differential cross-coupled inverters) will be analyzed and designed in a 130 nm CMOS technology.

Physical Design of VCO with Wide Frequency Tuning Range Using Deep Submicron CMOS Technology

Abstract: This paper presents a new design approach of CMOS voltage controlled oscillator (VCO) with low power and wide frequency tuning range. A novel current starved delay cell has been proposed based on dual delay path architecture. The results have been obtained in 45 nm CMOS technology with supply voltage 1 V. The proposed VCO achieves a controllable frequency range from 1.81 GHz to 10.55 GHz with a wide tuning range. The control voltage (Vctrl) has been varied from 0.3V to 1V for obtaining the different output frequencies. The power dissipation of proposed VCO is 34.932 uW with current consumption as 0.079 mA at a control voltage of 1V and very optimised surface area as 14.8µm2. Keywords: Current starved delay cell, Low Power, Tuning range, VCO, etc.

A 0.3 THz VCO using gm‐enhanced technology in 55 nm CMOS

AbstractA power combined terahertz (THz) voltage‐controlled oscillator (VCO) is proposed to increase the output power. Based on the traditional transformer‐feedback structure, a new negative conductance enhanced (gm‐enhanced) technology is presented to enhance the start‐up of the proposed THz VCO by adding additional transistors to offset the loss of the source inductance. In addition, a short transmission line is used as a zero‐phase shifter to lock the three single‐core VCOs for consistent frequency, phase, and amplitude. The fully integrated 300 GHz VCO design is fabricated in 55‐nm complementary metal oxide semiconductor (CMOS) process. The measurement results show that by modulating the bias voltage of the transistors, the VCO can achieve a tuning range of 301.2–304.2 GHz with a maximum output power of −7.5 dBm. The chip area is only 554 μm × 530 μm.

Active inductor based low phase noise voltage controlled oscillator

This paper proposed a fully MOS-based voltage-controlled oscillator (VCO) with tuning range and low phase noise, replacing the most often used NMOS-based inductor-capacitor tank arranged in cross-coupled topology with a high-Q active inductor. This study mainly focuses on VCO design using a MOS-based active inductor and is implemented and verified using UMC 180nm CMOS technology. The proposed VCO is resistorless and consists of an active inductor, two MOS capacitors, and the buffer circuits. The fundamental principle of this MOS-based VCO concept is to use MOS based inductor to replace the passive inductor, which is an active inductor that gives less area and low power usage. At 1 MHz frequency offset, the phase noise achieved by this proposed configuration is -102.78dBc/Hz. In the proposed VCO architecture, the frequency tuning range is 0.5GHz to 1.7GHz. This VCO design can accomplish this acceptable tuning range by altering the regulating voltage from 0.7V to 1.8V. This suggested architecture of proposed VCO design has the power consumption of 9mW with a 1.8V supply voltage. The suggested VCO has been shown to be a good fit for low-power RF circuit applications while preserving acceptable performance metrics.

Design of Low Phase Noise VCO Considering C/L Ratio of LC Resonator in 0.18-μm CMOS Technology

A voltage-controlled oscillator (VCO) is usually designed by maximizing the quality (Q-) factor of the LC-tank resonator to realize a low phase noise. For the same frequency, the ratio of C/L affects the loaded Q-factor (QL) and then phase noise of the VCO. This affect has not been considered so far in the design of VCO because the conventional on-chip spiral inductor cannot be optimized for C/L ratio. This brief first investigates the effects of C/L ratio on the phase noise, and a design methodology for optimized C/L ratio using defected ground structure (DGS) resonator is presented. Then, the resonators were further evaluated based on LgL-product simulation for a fixed Ibias. Employing the proposed resonator, a very low phase noise KUband VCO is designed and implemented in 0.18-lm CMOS technology. The measurement result shows that the proposed VCO has a phase noise of -110.77 dBc/Hz at 1 MHz offset of 17.5 GHz carrier frequency and a frequency tuning range of 8.7%. The VCO consumes 2.3 mW power, which results in a figure of merit (FoM) of -191.95 dB.

Design and Performance Analysis of CMOS Tunable Active Inductor Based Voltage Controlled Oscillator

ABSTRACT The performance of a Voltage Controlled Oscillator (VCO) is critical to meet the requirements of various wireless standards. This study highlights the use of a tunable active inductor (TAI) to build a VCO with a UMC 0.18 µm process. The exclusion of the MOS varactor and the use of minimal transistors in the design provide significant improvement in the overall silicon area. The proposed single-ended TAI with the feedback resistor achieves a good quality factor (Q) and wide inductive bandwidth. The proposed tunable active inductor involves a power dissipation of 310 µW at Vb=0.8 V. The use of two symmetrical active inductors in the design of VCO gives a tuning range from 754 MHz to 1.89 GHz. The obtained tuning range can meet the requirement of L-band applications & IEEE 802.11ah standards. The total power consumption range under 1.0 supply voltage (Vdd) from 2.01 - 2.68 mW when the control voltage (Vb) is increased from 0.2 to 2.0 V. The phase noise and figure of merit (FOM) obtained at 1 MHz relative frequency from the carrier were -89.64 dBc/Hz and -150.4, respectively. The total layout area consumed by VCO with and without pad-frame was 43.03 µm 39.04 µm and 22.11 µm 15.43 µm respectively, which is very low as compared to spiral inductor based VCO. Corner analysis, Monte Carlo analysis, temperature sweep analysis, and Stability analysis were carried out to validate the reliability and robustness of the VCO.

Low power CMOS differential ring VCO designs using dual delay stages in 0.13 ​μm technology for wireless applications

This manuscript postulates two new designs of dual-delay stage for the four-stage CMOS differential ring voltage controlled oscillators (VCOs). Ring VCOs designs use dual-delay path techniques to achieve a wide tuning range with low power dissipation. The proposed VCOs are designed in TSMC 0.13 ​μm CMOS technology with a power supply of 1.3 ​V. VCO-1 generates tuning ranges from 5.188 to 7.932 ​GHz (41.82%), whereas its power dissipation varies from 1.853 to 2.711 ​mW by the change in control voltage from −1.0 ​V to 0 ​V. VCO-2 based on I-MOS varactors produces a tuning range from 4.918 to 7.268 ​GHz (38.56%) and dissipates the power from 1.853 ​mW to 2.711 ​mW. VCO-1 and VCO-2 exhibits phase-noise of −102.2 dBc/Hz and −99.5 dBc/Hz at 1 ​MHz offset from 5.834 ​GHz to 5.482 ​GHz central frequency, respectively. The figure-of-merit (FoM) of VCO-1 and VCO-2 circuit is −173.9 dBc/Hz and −171.2 dBc/Hz. Proposed VCO-1 and VCO-2 acquire an area of 247.62 μm2 and 248.04 μm2, respectively.

A Novel Approach for Low Phase Noise Voltage Controlled Oscillator Design based on TSMC 0.18 um Technology

In this paper, a new structure of Voltage Control Oscillator (VCO) to reduce the phase noise using two plans of a variable voltage capacitor is proposed. The aim of the current paper is to analyse two structure of a completely integrated 3.7 GHz LC-VCO based on TSMC 0.18 um technology. In the first plan for different voltages with variable voltage capacitors in this circuit can be achieved to a suitable phase noise of about 125 dB per Hz and in the second plan, a noise of -123 dB per Hz is achieved in the deviation frequency of 1 MHz. Also, the Figure of Merit (FOM) values for the first plan of -4/186 and for the second plan of –4/184 are achieved and the power consumption is 10 mW.

Low power wide tuning range differential ring VCO designs with I-MOS and A-MOS varactor

This manuscript reports two new designs of dual delay cells based on inversion mode MOS (I-MOS) and accumulation mode MOS (A-MOS) varactor for low power and wide tuning range differential ring voltage controlled oscillator (VCO). The new designs obtained a large tuning range by varying the capacitance of the delay stages. The change in capacitance across I-MOS and A-MOS varactor are obtained by varying the gate control voltage (Vg). The proposed VCO circuits are simulated in 0.18 µm CMOS process with a supply voltage (Vdd) of 1.8 V. The tuning ranges of VCO-I (with I-MOS varactor) and VCO-II (based on A-MOS varactor) vary from 1.697–0.714 GHz (81.54%) and 2.019–0.874 GHz (79.15%), whereas their power consumption vary from 4.347–3.507 mW and 3.713–3.063 mW respectively, by modulation of control voltage (Vc) from 0 V to 1 V. The phase noise of ring VCO-I and VCO-II is −103.1 dBc/Hz and −101.2 dBc/Hz at 1 MHz offset from 1.270 GHz and 1.516 GHz central frequency respectively. The figure of merit (FoM) of the VCO-I and VCO-II is −158.92 dBc/Hz and −159.32 dBc/Hz respectively and acquires an area of 0.381 mm2.

A Novel Varactorless Tuning Technique for Clapp VCO Design Using Tunable Negative Capacitor to Increase Frequency-Tuning Range

In this paper, a varactorless frequency-tuning method for Clapp voltage-controlled oscillator (VCO) design is proposed aiming at increasing frequency-tuning range (FTR) in comparison with the conventional varactor-based counterpart. The proposed structure uses a tunable non-Foster (negative) capacitor (TNC) to sweep oscillation frequency instead of a varactor. The analytical demonstration points that total tuning dynamic (TTD) qualitatively representing FTR is traditionally limited to varactor’s tuning dynamic (TD); while the TNC-based VCO can exhibit very-high TTD, at least over TNC’s TD capacity, if the maximum negative capacitance is appropriately designed, which can tolerate the TD requirement on the tuning component for wideband operation. Circuit realization of TNC is based on a grounded negative impedance inverter (NII) with cross-coupled transistors whose gate voltage controls capacitance. A simulation script using a real discrete transistor model with the realized TNC shows that FTR can be covered with TTD of 2.46 units while the TD of the non-Foster tuning component is only 1.32 units, validating the advantageous operation as well as practical realization possibility of the proposed VCO. In addition, phase noise performance is remained below −100 dBc/Hz for every tuning voltages at 1 MHz offset frequency, while figure of merit comprising FTR effect (FOMT) can be achieved in range of 140-180, which is similar to the existing state-of-the-art VCOs.

Design of low power VCO using FinFET technology for biomedical applications

A voltage controlled oscillator (VCO) is one of the most significant essential structure obstructs in simple and advanced circuit (CKT). In Biomedical applications the nature of the biomedical connection is resolved in huge part by the qualities of the VCO and in the present biomedical applications more prominent recurrence goes is required by the VCOs. Generally, VCOs utilizing CMOS innovation have been utilized for low recurrence applications, however 18 nm forms have permitted CMOS oscillators to accomplish frequency in the gigahertz extend. This range is made conceivable with the utilization of programmed swing control. VCO can be fabricated utilizing many CKT strategies. VCO can be built using many CKT techniques. To design improved performance VCO’s explicitly low power different techniques using latest cadence software to obtain high density and low leakage current. To optimize and design the VCs, carry out analysis and enhance the performance. To design VCO with four different techniques using latest cadence software, optimize their performance and measure it in cadence software environment.

Design of optimal high-frequency CMOS VCOs for automotive application

In this paper, a design methodology of Voltage-Controlled Oscillator (VCO) for long-range automotive RAdio Detection And Ranging (RADAR) is proposed and simulation analysis is carried out over Virtuoso SpectreRF software on Cadence tool. The frequency ranges of the mm-wave CMOS current-starved ring and LC VCOs for 45-nm CMOS technology are 24 and 76 GHz, respectively. The ring VCO at 25 GHz oscillation frequency demonstrates 2.06% tuning range, phase noise −71.61 dBc/Hz at 1-MHz offset, 3.43 mW power dissipation and layout area of $$20\times 20 \,\upmu {\mathrm{m}}^2$$ whereas cross-coupled LC VCO achieves an oscillation frequency of 76.25 GHz for frequency tuning range of 0.65%, a phase noise of −92.44 dBc/Hz at 1-MHz offset, 8.59 mW power dissipation and $$320\times 320 \,\upmu {\mathrm{m}}^2$$ layout area. The proposed design of efficient VCOs shows an excellent performance for long-range automotive RADAR.

A Design of Wide-Range and Low Phase Noise Linear Transconductance VCO with 193.76 dBc/Hz FoMT for mm-Wave 5G Transceivers

This paper presents a wide-range and low phase noise mm-Wave Voltage Controlled Oscillator (VCO) based on the transconductance linearization technique. The proposed technique eliminates the deep triode region of the active part of the VCO, and lowers the noise introduced by the gm-cell. The switch sizes inside the switched capacitor bank of the VCO are optimized to minimize the resistance of the switches while keeping the wide tuning range. A new layout technique shortens the routing of the VCO outputs, and lowers the parasitic inductance and resistance of the VCO routing. The presented method prevents the reduction of the quality factor of the tank due to the long routing. The proposed VCO achieves a discrete frequency tuning range, of 14 GHz to 18 GHz, through a linear coarse and middle switched capacitor array, and offers superior phase noise performance compared to recent state-of-the-art VCO architectures. The design is implemented in a 45 nm CMOS process and occupies a layout area (including output buffers) of 0.14 mm2. The power consumption of the VCO core is 24 mW from the power supply of 0.8 V. The post-layout simulation result shows the VCO achieves the phase noise performances of −87.2 dBc/Hz and −113 dBc/Hz, at 100 kHz and 1 MHz offset frequencies from the carrier frequency of 14 GHz, respectively. In an 18 GHz carrier frequency, the results are −87.4 dBc/Hz and −110 dBc/Hz, accordingly.

A 273.5–312-GHz Signal Source With 2.3 dBm Peak Output Power in a 130-nm SiGe BiCMOS Process

This article presents a 300-GHz signal source that consists of a 75-GHz voltage controlled oscillator (VCO), a static frequency divider-by-two circuit, a 150-GHz doubler, a 150-GHz power amplifier, and a 300-GHz doubler in a commercial 130-nm SiGe BiCMOS process. To extend the frequency tuning range, a switched substrate shield variable base inductor is adopted in the 75-GHz VCO design. The output power of the 150-GHz power amplifier is enhanced by a proposed auxiliary inductor for adjusting the phase difference of the LC balun. Besides, through systematically analyzing the influences of the input power and the base bias voltage on the output power, the 300-GHz doubler has been carefully designed for maximizing the output power. The measured peak output power is 2.3 dBm at 286 GHz and the output power is higher than 0 dBm from 282 to 312 GHz. The output frequency can be tuned from 273.5 to 312 GHz. The phase noise is measured to be $-$ 88.5 dBc/Hz @ 1 MHz at 300 GHz and better than $-$ 85.5 dBc/Hz @ 1 MHz across the whole tuning range. The total chip area is 1.254 mm $^2$ and the whole dc power consumption is 435 mW, which results in 0.4% DC-to-RF efficiency. Compared with the state-of-the-art silicon-based signal source at around 300 GHz, this article achieves the highest output power, the best tuning range, and a comparable phase noise without on-chip or free-space power combining techniques.