Output Frequency Of Voltage-controlled Oscillator Research Articles

A Multi Output Formulation for Analog Circuits using MOM-SVM

This paper proposes performance based macro modeling of analog circuit using Multi Output Modeling (MOM) with the help of Support Vector Machine (SVM). SVM models the analog circuits and provides a relation between multi-input and multi-output parameters. In this work, Voltage Controlled Oscillator (VCO) is modeled as a test circuit which is designed in Cadence Virtuoso GPDK 45nm technology. From the Spice simulation results, the feasible dataset has been extracted from the complete dataset. Then, the VCO output frequency and phase noise is modeled by the width of the transistors which are the input parameters of the transistors. After tuning the model properly by k-cross validation method, the accuracy was found to be 96.1% which is good enough to make it use for the circuit synthesis purpose.

31.1: A 3.5Gbps/Lane Intra‐panel Interface with a PVT‐robust VCO Based CDR for UD TV Applications in 0.18μm High‐voltage CMOS Technology

AbstractA CMOS voltage‐controlled oscillator (VCO) with robustness under PVT variation is proposed, and its application to a PLL‐based CDR is also presented. In the VCO design, voltage regulator is used to suppress voltage variation and improved voltage‐to‐current (V/I) converter is used to mitigate temperature variation and varactor‐tuned ring oscillator is used to reduce process variation. For broad bandwidth, comparator adopts the active negative feedback circuit and Signal Integrity (SI) on PCB channel is also improved considering via effect. Simulation and test results under 0.18‐μm high‐voltage CMOS technology show that the VCO output frequency range is from 300MHz to 700MHz and the maximum intra‐panel interface operating speed is up to 3.5Gbps per lane for UD LCD‐TV applications.

A 5.8‐GHz frequency synthesizer chip design for worldwide interoperability for microwave access application

AbstractA 5.8‐GHz frequency synthesizer using wideband LC‐tank voltage‐controlled oscillator (VCO) for worldwide interoperability for microwave access applications with a 1.8 V voltage supply has been designed and successfully implemented in TSMC 0.18 μm CMOS process. In this proposed circuit, two important ideas are applied. First, a 3‐bit binary weighted capacitor array in the VCO is adopted to extend the tuning range and reduce the phase noise. Second, a class‐AB current mode logic is utilized in first divider stage to handle the high frequency signal. Measured results show that output frequency of VCO is tunable from 5.3 to 6.1 GHz corresponding to 14.1%, and phase noise is −110.2 dBc/Hz at 1 MHz offset, output power spectrum is −9.24 dBm at frequency of 5.73 GHz, power consumption is 32 mW, and including pads, chip area is 0.53 (0.82 × 0.65) mm2. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:2931–2935, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26405

A 6 GHz low power differential VCO

AbstractThis paper presents a new differential CMOS voltage controlled oscillator (VCO). The topology of the proposed differential VCO is a combination of Colpitts CMOS VCO and cross‐coupled lateral BJT VCO. A symmetric transformer and differential differentially tuned MOS varactors are used to reduce phase noise. The VCO has been fabricated with the 0.18‐μm CMOS process. At the 1.2‐V supply voltage, the output frequency of VCO is from 5.99 to 6.43 GHz with 441 MHz tuning range and a phase noise of −118.5 dBc/Hz at the 1 MHz offset from the center frequency of 6.43 GHz. Its core current consumption is 2.8 mA and the core power consumption is 3.36 mW. The total power consumption of this VCO is 9.12 mW. The figure of merit (FOM) of this differential VCO is −189.4 dBc/Hz. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 76–79, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22043

A CMOS self-calibrating frequency synthesizer

A programmable phase-locked-loop (PLL)-based frequency synthesizer, capable of automatically adjusting the nominal center frequency of the voltage-controlled oscillator (VCO) to an optimum value is described. In fully integrated PLLs, the VCO output frequency should be tunable over a wide range of frequencies, covering the desired range of the synthesizer output frequencies, for all processing variations and operating conditions. A wide tuning range realized by making the VCO gain K/sub o/ large has the unwanted effect of increasing the phase noise at the output of the VCO, and hence the PLL as well. In this work, the wide tuning range is realized by digital control, with process variability managed through self-calibration. The PLL is only required to pull the oscillator output frequency to account for the digital quantization, temperature variations, and some margin. This allows the K/sub o/ to be small, with better noise performance resulting. The prototype self-calibrating frequency synthesizer, capable of operating from 80 MHz to 1 GHz, demonstrates a measured absolute jitter of 20-ps rms at 480-MHz operating frequency. The prototype IC is fabricated in a 0.35-/spl mu/m 3-V digital CMOS process.