Voltage Controlled Oscillator Circuit Research Articles

Implementation of a fully integrated memristive Chua’s chaotic circuit with a voltage-controlled oscillator

In this paper, a fully integrated memristive Chua’s chaotic circuit based on the voltage-controlled oscillator is proposed. The memristor replaces the nonlinear diode, and the VCO (voltage-controlled oscillator) replaces the LC oscillator, eliminating the need for diodes, resistors, capacitors, and other complex circuit structures. The proposed chaotic circuit occupies a small chip area, only 0.0045 mm2, and achieves low power consumption of 2.8267 mW. The chaotic circuit is fabricated using the SMIC 180 nm CMOS process. The simulation results demonstrate that the VCO circuit can generate a frequency output ranging from 358 MHz to 1.1 GHz by varying Vc from 0 V to 2.8 V, with a power supply of 3.3 V. The value range of the Lyapunov index is 1.015 ∼1.03. The circuit offers advantages such as a stable power supply, low power consumption, and a small chip area.

A Single-Event-Hardened Scheme for Ring Oscillator Applied to Radiation-Resistant PLL Microsystems

A voltage-controlled oscillator (VCO) is one of the key modules of the phase-locked loop (PLL) microsystem, and it is easy to bombard using high-energy particles in a radiation environment, resulting in the single-event effect. In order to improve the anti-radiation ability of the PLL microsystems used in the aerospace environment, a new voltage-controlled oscillator hardened circuit is proposed in this work. The circuit consists of delay cells with an unbiased differential series voltage switch logic structure with a tail current transistor. By reducing sensitive nodes and using the positive feedback of the loop, the recovery process of the VCO circuit to the single-event transient (SET) is reduced and accelerated, so as to reduce the sensitivity of the circuit to the single-event effect. The simulation results based on the SMIC 130 nm complementary metal–oxide–semiconductor (CMOS) process show that the maximum phase shift difference of the PLL with the hardened VCO is reduced by 53.5%, which shows that the hardened VCO structure can reduce the sensitivity of the PLL to the SET and improve the reliability of the PLL in the radiation environment.

Voltage-Controlled Oscillator Utilizing Inverse-Mode SiGe-HBT Biasing Circuit for the Mitigation of Single-Event Effects

The advantages and the tradeoffs associated with the use of inverse-mode (IM) silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) biasing circuitry in radio-frequency (RF) voltage-controlled oscillators (VCOs) have been investigated and the performance of proposed VCOs (IM VCOs) is compared with VCOs with conventional forward-mode (FM) SiGe-HBTs (FM VCOs). Where the high-frequency performance of IM VCOs is inevitably degraded due to unfavorable device optimization unlike FM VCOs, IM VCOs provide acceptable low-GHz VCO circuit performance. In terms of single-event effects (SEEs), the IM VCOs show reduced transient peaks and duration in comparison with conventional FM VCOs. In addition, the performance of the VCOs is analyzed in terms of transient error vector magnitude (TEVM) in an RF receiver (RX) using quadrature phase-shift keying (QPSK) modulation under a radiation environment. The IM VCOs in the RX circuit show better reliability under SEEs, offering 28.2% lower TEVM at a 64 Mb/s data rate, than that of the RX circuit with conventional FM VCOs. Therefore, the application of IM SiGe-HBT biasing circuits for RF VCOs can be a viable SEE-hardening technique for space-based RF systems. The VCO prototype was fabricated using IHP 130-nm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology.

Implementation of the High Speed PLL

the most multipurpose application of the phase locked loops (PLL) is for clock generation and clockrecovery in microprocessor, networking, communication systems, and digital circuit and frequency synthesizers.Phase locked-loops (PLLs) are commonly used to generate well-timed on-chip clocks inhighperformance digital systems. Modern wireless communication systems employ Phase Locked Loop (PLL) mainly for synchronization, clock synthesis, skew and jitter (deviation) reduction. Because of the increase in the speed of the circuit operation, there is a need of a PLL circuit with fasterlocking ability. Many present communication systems operate in the GHz frequency range. Hence there is a necessity of a PLL which must operate in the GHz range with less lock time.PLL is a mixed signal circuit as itsarchitecture involves both digital and analog signalprocessing units. The present work focuses on the redesign of a PLL system using the 90 nm process technology (GPDK090 library) in EDA TANNER Design Environment.Here a current starved ring oscillator has been considered for its superior performance in form ofits low chip area, low power consumption and wide tunable frequency range. Thesimulation results ofPLL are reported in this work. It is found that the designed PLL consumes 11.68mW power froma 1.8V D.C. supply and have a lock time 280.6 ns. As the voltage controlled oscillator (VCO) isthe heart of the PLL, so the optimization of the VCO circuit is also carried out using the optimization technique. The results of the VCO designed are shown. Keyword: PLL, VCO, GDPK 900, Charge pump (CP).

A high-range reference voltage low-dropout regulation design for voltage-controlled oscillator circuit

The stability of VCO as a clock recovery module in high-speed transmission circuits cannot be ignored. The LDO circuit as its power module not only needs to ensure the stability of the VCO under high-speed working conditions, but also needs to satisfy the demand for changes in its supply voltage swing. To meet the above requirements, a high-range reference voltage LDO (Low-dropout Regulator) was designed under the 28nm process. The input of the error amplifier of the LDO adopts a rail-to-rail structure, the reference voltage can be changed in a larger range, and the output voltage can also fluctuate in the range of 0.3V-0.9V. After simulation, the power supply rejection ratio (PSRR) of this LDO is 1.53MHz, the line regulation at full load is 8.29mV/V, the internal noise of the circuit is low, the transient response time from on load to full load is 42ns, and the phase margin is close to 80deg.

A 78-MHz BW Continuous-Time Sigma-Delta ADC with Programmable VCO Quantizer

This article presents a high speed third-order continuous-time (CT) sigma-delta analog-to-digital converter (SDADC) based on voltage-controlled oscillator (VCO), featuring a digital programmable quantizer structure. To improve the overall performance, not only oversampling technique but also noise-shaping enhancing technique is used to suppress in-band noise. Due to the intrinsic first-order noise-shaping of the VCO quantizer, the proposed third-order SDADC can realize forth-order noise-shaping ideally. As a bright advantage, the proposed programmable VCO quantizer is digital-friendly, which can simplify the design process and improve anti-interference capability of the circuit. A 4-bit programmable VCO quantizer clocked at 2.5 GHz, which is proposed in a 40 nm complementary metal-oxide semiconductor (CMOS) technology, consists of an analog VCO circuit and a digital programmable quantizer, achieving 50.7 dB signal-to-noise ratio (SNR) and 26.9 dB signal-to-noise-and-distortion ration (SNDR) for a 19 MHz − 3.5 dBFS input signal in 78 MHz bandwidth (BW). The digital quantizer, which is programmed in the Verilog hardware description language (HDL), consists of two-stage D-flip-flop (DFF) based registers, XOR gates and an adder. The presented SDADC adopts the cascade of integrators with feed-forward summation (CIFF) structure with a third-order loop filter, operating at 2.5 GHz and showing behavioral simulation performance of 92.9 dB SNR over 78 MHz bandwidth.

A 33 MHz Fast-Locking PLL with Programmable VCO and Automatic Band Selection for Clock Generator Application

This paper presents a prototype of an auto-ranging phase-locked loop (PLL) with low jitter noise over a wide operating frequency range using the multiband programmable voltage-controlled oscillator (VCO) gain stage with automatic band selection. We successfully reduce the VCO gain (Kvco) and retain the desired frequency band. The proposed PLL comprises a prescaler, phase frequency detector (PFD), charge pump (CP), programmable VCO and automatic band selection circuit. The PLL prototype with all subblocks was implemented using the TSMC 0.18 μm 1P6M process. Contrary to conventional PLL architectures, the proposed architecture incorporates a real-time check and automatic band selection circuit in the secondary loop. A high-performance dual-loop PLL wide tuning range was realized using an ASIC digital control circuit. A suitable way to maintain the Kvco low is to use multiple discrete frequency bands to accommodate the required frequency range. To maintain a low Kvco and fast locking, the automatic frequency band selection circuit also has two indigenous, most probable voltage levels. The proposed architecture provides the flexibility of not only band hopping but also band twisting to obtain an optimized Kvco for the desired output range, with the minimum jitter and spurs. The proposed programmable VCO was designed using a voltage-to-current-converter circuit and current DAC followed by a four-stage differential ring oscillator with a cross-coupled pair. The VCO frequency output range is 150–400 MHz, while the input frequency is 25 MHz. A sequential phase detection loop with a negligible dead zone was designed to adjust fine phase errors between the reference and feedback clocks. All circuit blocks of the proposed PLL were simulated using the EDA tool HSPICE and layout generation by Laker. The simulation and measured results of the proposed PLL show high linearity, with a dead zone of less than 10 pV. The differential VCO was used to improve the linearity and phase noise of the PLL. The chip measured results show rms jitter of 19.10 ps. The PLL prototype also has an additional safety feature of a power down mode. The automatic band selection PLL has good immunity for possible frequency drifting due to temperature, process and supply voltage variations. The proposed PLL is designed for −40 to +85 °C, a wide temperature range.

Design of power-efficient CMOS based oscillator circuit with varactor tuning control

This paper presents a low-power, wide tuning range CMOS voltage-controlled oscillator with MCML (MOS current mode logic) differential delay cell. Voltage controlled oscillator (VCO) circuit is designed in TSMC 0.25 μm CMOS process. To achieve the broad frequency range concept of variable capacitance is employed in the proposed VCO circuit. Source/drain tuning voltage (Vtune) and body bias voltage (Vb) of I-MOS varactor are used to achieve variable capacitance at different I-MOS varactor widths (W). The dual control voltage of I-MOS varactor results in a tuning range from 0.528 GHz to 2.014 GHz. VCO's figure of merit (FoM) is 152.13 dBc/Hz with phase noise of −93.77 dBc/Hz at 1 MHz offset from the oscillation frequency. The proposed VCO dissipates maximum power of 3.127 mW.

Low power wide tuning range differential ring VCO designs with I-MOS and A-MOS varactor

This manuscript reports two new designs of dual delay cells based on inversion mode MOS (I-MOS) and accumulation mode MOS (A-MOS) varactor for low power and wide tuning range differential ring voltage controlled oscillator (VCO). The new designs obtained a large tuning range by varying the capacitance of the delay stages. The change in capacitance across I-MOS and A-MOS varactor are obtained by varying the gate control voltage (Vg). The proposed VCO circuits are simulated in 0.18 µm CMOS process with a supply voltage (Vdd) of 1.8 V. The tuning ranges of VCO-I (with I-MOS varactor) and VCO-II (based on A-MOS varactor) vary from 1.697–0.714 GHz (81.54%) and 2.019–0.874 GHz (79.15%), whereas their power consumption vary from 4.347–3.507 mW and 3.713–3.063 mW respectively, by modulation of control voltage (Vc) from 0 V to 1 V. The phase noise of ring VCO-I and VCO-II is −103.1 dBc/Hz and −101.2 dBc/Hz at 1 MHz offset from 1.270 GHz and 1.516 GHz central frequency respectively. The figure of merit (FoM) of the VCO-I and VCO-II is −158.92 dBc/Hz and −159.32 dBc/Hz respectively and acquires an area of 0.381 mm2.

New low power differential VCO circuit designs with active load and IMOS varactor

In this paper, low power differential voltage-controlled oscillators (VCOs) have been reported utilizing the active load and inversion mode MOSFET (IMOS) varactor in the delay stages. VCO circuits operation is based on two NOR gates in differential mode, variations in gate control voltage of the NMOS/PMOS active load, and the varactor control voltage of IMOS. For VCO based on NMOS active load, variations in gate control voltage from 1.0 V to 2.0 V exhibit frequency variations from 6.687 GHz to 6.395 GHz. For VCO based on PMOS active load, variations in gate control voltage of PMOS active load from −0.5 V to 0.5 V provide frequency variations from 5.726 GHz to 6.142 GHz. For VCO based on IMOS varactor, variations in varactor control voltage of IMOS from 1.0 V to 2.0 V shows variations in output frequency from 3.796 GHz to 4.499 GHz with power dissipation of 2.06 mW. Proposed VCOs shows a phase noise of −76.20 dBc/Hz@1MHz for NMOS active load, −73.42 dBc/Hz@1MHz for PMOS active load and −75.63 dBc/Hz@1MHz for IMOS varactor load and the figure of merit (FoM) for the VCOs are −149.43 dBc/Hz, −145.58 dBc/Hz and −145.17 dBc/Hz, respectively.

Low power active load and IMOS varactor based VCO designs using differential delay stages in 0.18 ​μm technology

This paper proposes low power differential voltage-controlled oscillators (VCOs) with active load and IMOS varactor in delay stages. VCO circuits utilize two NOR gates in differential mode. The different levels of gate bias voltage (Vbias) of the PMOS/NMOS active load along with variations in the varactor control voltage (Vcontrol) of inversion mode MOSFET (IMOS) achieves a wide frequency tuning range. PMOS active load VCO shows the output frequency range from 4.656 ​GHz to 5.333 ​GHz and power dissipation of 2.539 ​mW. NMOS active load VCO shows the output frequency range from 4.782 ​GHz to 5.516 ​GHz and power dissipation of 2.225 ​mW. The results with different width of varactor diode and bias voltages of active load are also reported in this work. Proposed VCO circuits are showing a phase noise of −102.37 dBc/Hz for PMOS active load, and −98.63 dBc/Hz for NMOS active load at 1 ​MHz offset with the corresponding figure of merit (FoM) of −172.86 dBc and −168.41 dBc, respectively.

LOW POWER SINGLE ENDED VCO DESIGN WITH IMOS VARACTOR FOR WIRELESS APPLICATIONS

This article presents a low power single-ended voltage-controlled oscillator (VCO) design with an inversion mode MOS (IMOS) varactor in delay stages. VCO consists of two complementary metal-oxide-semiconductor (CMOS) inverters with a PMOS transistor as a bridge to create a single-ended VCO design. The output frequency tuning has been carried out at different bias voltage of bridge transistor along with the varying tuning voltage of the IMOS varactor connected at the output nodes to achieve constant power dissipation and wider tuning range. This VCO achieves a frequency tuning range of 31% from 2.335 GHz to 3.181 GHz and power dissipation of 0.710 mW for 1.8V power supply. The results with different width of the IMOS varactor show that frequency decreases with an increase in varactor width. Proposed VCO tunes the output frequency with IMOS varactor loading without changing the overall power dissipation of the circuit. The proposed VCO circuit shows a phase noise of -93.45 dBc/Hz at 1 MHz offset with the corresponding figure of merit (FoM) of -153.47 dBc. A comparison with earlier reported VCOs shows that proposed VCO provides an improvement in performance.

Wide-band multiferroic quartz MEMS antennae

We describe a pair of quartz MEMS resonators integrated into a single vacuum package for use as a wide-band RF receiver. The resonators are connected to integrated sustaining circuits for oscillator operation and are used within a phase lock loop in which one oscillator is used as the reference. The other resonator is coated with a magnetostrictive layer which induces a frequency shift proportional to an applied external magnetic field. This frequency shift is detected by the phase lock loop and its feedback signal to a voltage controlled oscillator circuit is used as the antenna output. Thus, the bandwidth of the antenna is determined by the bandwidth of the phase lock loop and not the Q of the resonator.

A wide tuning range VCO design using multi-pass loop complementary current control with IMOS varactor for low power applications

In this work a wide-bandwidth low-power voltage-controlled oscillator (VCO) design is presented using a new differential delay cell with complementary current control mechanism and inversion mode MOSFET (IMOS) varactor. The variations in output oscillation frequency of the VCO has been achieved by changing the capacitance of the delay cell with the usage of IMOS varactor containing two PMOS transistors connected in parallel. The proposed three-stage VCO has been designed with 1.8 V power supply in 180 nm CMOS technology. Capacitance of IMOS varactor has been varied by altering the source/drain voltage Vcontrol and back-gate voltage Vsb of IMOS. The variations in power supply voltage from 1 V to 2.4 V provides output frequency from 1.893 GHz to 7.926 GHz with power dissipation of 0.953 mW to 24.261 mW with IMOS varactor width of 5 µm. The results have been extended for the IMOS width of 10 µm, 15 µm and 20 µm. The tuning range of 122% has been achieved with the power supply tuning method. The variations in source/drain voltage of IMOS from 1 V to 2.4 V provides the output frequency from 6.373 GHz to 5.460 GHz with power dissipation of 9.62 mW. The tuning range of 15.7%, 22.3%, 44% and 40.6% has been obtained for IMOS with widths of 5 μm, 10 μm, 15 μm and 20 μm with the source/drain voltage Vcontrol variations. Further, frequency variation from 5.895 GHz to 6.406 GHz has been obtained with back-gate voltage Vsb tuning of IMOS varactor from 0 V to 2.4 V. The phase noise measured for the VCO is −90.67 dBc/Hz@1 MHz and the figure of merit (FoM) for the VCO is 172.86 dBc/Hz with supply voltage of 1.8 V. Proposed VCO circuit achieved a low power dissipation, wide tuning range, better phase noise and figure of merit (FoM).

A low power VCO design using composite load for delay cell with IMOS varactor for wider tuning range

In this paper, a new low-power voltage-controlled oscillator (VCO) design is presented using inductive composite load for the delay cell and inversion mode MOSFET (IMOS) varactor using 180nm CMOS technology. The output oscillation frequency of the VCO has been changed by varying the capacitance of the delay cell with the usage of IMOS varactor comprising two PMOS transistors connected in parallel. Variation in source/drain voltage (Vct) and back-gate voltage (Vsb) of IMOS changes the capacitance of IMOS resulting in variations in output oscillation frequency of VCO. Power supply voltage (Vdd) variations from 1V to 2. 4V gives output oscillation frequency from 0. 972 GHz to 4. 231 GHz and consumes power from 0. 002mW to 0. 919mW with IMOS varactor width of 2µm. The results have been drawn out for the IMOS width of 5µm, 8µm and 12µm. The source/drain voltage (Vct) variation of IMOS from 1V to 2. 4V show the output oscillation frequency from 2. 648 GHz to 3. 253 GHz and achieves power consumption of 0. 279mW. Results have been further extended for IMOS with widths of 2μm, 5μm, 8μm and 12μm and a tuning range of 21% has been obtained for source/drain voltage (Vct) variations. Further, the back-gate voltage (Vsb) tuning of IMOS varactor from 1V to 2. 4V shows frequency variations from 3. 114 GHz to 3. 282 GHz. The VCO shows a phase noise of-107. 77dBc/Hz@1MHz offset from centre frequency and the figure of merit (FoM) for the VCO is -168. 94dBc/Hz with supply voltage of 1. 8V. Proposed VCO tunes the output frequency with IMOS varactor loading without changing the overall power dissipation of circuit. Proposed VCO circuit achieved a low power dissipation, wide tuning range, better phase noise and figure of merit (FoM).

A new design of low power varactor based voltage controlled oscillator

This paper reports a new design of voltage controlled oscillator (VCO) using three transistors NOR-gate with metal oxide semiconductor (MOS) varactor tuning concept. The proposed VCO has been designed in 0.18 μm TSMC CMOS technology. Control voltage (VCT) across the MOS varactor has been varied to achieve the tuning in proposed VCO circuit. Reported VCO topology exhibits a wide tuning range from 2.781 to 4.062 GHz with the variation in control voltage (VCT) from 0 to 0.8 V with different value of supply voltage (VDD). Further, a tuning range has been observed from 1.019 to 3.777 GHz with variation in supply voltage (VDD) from 1 to 3 V. VCO shows power consumption from 0.130 to 5.685 mW with varied power supply voltage from 1 to 3 V. The proposed VCO shows phase noise of − 87.6 dBc/Hz at 1 MHz offset from the center frequency with power consumption of 1.270 mW. The figure of merit of the proposed VCO is 155.4 dBc/Hz. Proposed ring VCO shows low power consumption, wide tuning range and superior phase noise performance in comparison to the previously reported circuits.

Ionizing Radiation Effects Spectroscopy for Analysis of Total-Ionizing Dose Degradation in RF Circuits

Ionizing radiation effects spectroscopy (IRES) for the analysis of total-ionizing dose (TID) degradation in radio frequency (RF) circuits is presented. IRES is used to image the change in the operating parameters with respect to TID and for classification of the circuit’s state based on image features. Measured data from two voltage-controlled oscillators (VCOs) and two phase-locked loops (PLLs) exposed to TID are used to demonstrate the utility of IRES for radiation effects analysis. The VCO and PLL circuits were designed in a 130-nm bulk CMOS technology. The circuits were irradiated up to 300 krad(SiO2) using an Aracor X-ray source, and IRES images were developed at various TID levels based on the instantaneous frequency of the output waveforms. The IRES technique is based upon RF-distinct native attribute fingerprinting for specific emitter identification using RF waveforms in communication systems. The technique employs statistical time–frequency analyses of various signal features. The resulting statistical measures are utilized to identify the operational state of the circuit (i.e., the TID level and bias voltage) using machine learning (ML) classification. While minor increases in operating frequency were measured with dose, the technique resulted in up to 100% prediction accuracy in the identification of the operational state following an ML training set of at least 50 measured samples. Moreover, the IRES technique enhances standard measurements by capturing global parametric shifts as well as transient variation. The technique, which exploits the subtle characteristics inherent in the waveforms, shows promise in radiation dosimetry applications as well as in-situ monitoring of device and circuit operational health.

On Optimization of Manufacturing of Field-Effect Heterotransistors Framework a Voltage Controlled Oscillator Circuit, to Increase Their Density

On Optimization of Manufacturing of Field-Effect Heterotransistors Framework a Voltage Controlled Oscillator Circuit, to Increase Their Density

A low-noise voltage-controlled ring oscillator in 28-nm FDSOI technology for UWB applications

In millimeter wave systems, performance degradation mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for ultra-wide band applications identified for possible 5G usage. For this purpose, a novel differential symmetrical load delay cell based 3-stage ring oscillator has been introduced to design the ring-VCO. The 28 nm CMOS Fully Depleted Silicon On Insulator (FDSOI) technology is adopted for designing this VCO circuit with 1 V power supply while a new voltage control through the transistor body bias is implemented. The simulated results show that the proposed oscillator works in the tuning range of 29–49 GHz and dissipates 3.75 mW of power. It exhibits a phase noise of −129.2 dBc/Hz at 1 MHz offset from 49 GHz oscillation frequency, and a remarkable Figure of Merit (FoM) of −217.26 dBc/Hz. With similar power supply, the phase noise rises to −93.16 dBc/Hz for a second oscillator involving more of active components exactly 9 delay cells. Further, the impact of the operation temperature variation on the VCO performance is investigated. Results show a drift in the oscillation frequency for a temperature step from 27 °C to 40 °C and a degradation of 3dBc in the phase noise performance.

Ultra low power DG FinFET based voltage controlled oscillator circuits

ABSTRACTVoltage-controlled oscillator (VCO) significantly influences power and performance in many analog and digital applications. In this era of portable electronics, power consumption has emerged as an important design metric. Intended subthreshold circuits have proven their ability to satisfy this demand of ultra low-power consumption of a multitude of applications such as RFID, microsensors, etc. Double-gate Fin-FET technology is a promising alternative to the CMOS technology for the subthreshold circuits because of its enhanced gate control, improved performance, scalability, and robustness. Therefore, this paper investigates the viability of DG FinFET Current Starved Voltage Controlled Oscillator (CSVCO) in the subthreshold regime. The results indicate the superior performance of DG FinFET-based CSVCO in regard to speed, PDP, EDP, and variability as compared to CMOS-based CSVCO. Seven different CSVCO configurations, viz.. SG, IG, hybrid, hybrid reverse, pignsg, psgnig and MIGFET, designed using different configurations of DG FinFET, are simulated using 32 nm FinFET Predictive Technology Model (PTM) in HSPICE at 150 mv power supply. The proposed pignsg CSVCO shows better results in terms of frequency obtained versus power expended giving least PDP of 1.25E-16J and better immunity to supply voltage and process variations compared to all other CSVCO configurations.