Voltage Compensation Research Articles

A fully automated FAIMS-DIA mass spectrometry-based proteomic pipeline

Here, we present a standardized, "off-the-shelf" proteomics pipeline working in a single 96-well plate to achieve deep coverage of cellular proteomes with high throughput and scalability. This integrated pipeline streamlines a fully automated sample preparation platform, a data-independent acquisition (DIA) coupled with high-field asymmetric waveform ion mobility spectrometer (FAIMS) interface, and an optimized library-free DIA database search strategy. Our systematic evaluation of FAIMS-DIA showing single compensation voltage (CV) at -35V not only yields the deepest proteome coverage but also best correlates with DIA without FAIMS. Our in-depth comparison of direct-DIA database search engines shows that Spectronaut outperforms others, providing the highest quantifiable proteins. Next, we apply three common DIA strategies in characterizing human induced pluripotent stem cell (iPSC)-derived neurons and show single-shot mass spectrometry (MS) using single-CV (-35 V)-FAIMS-DIA results in >9,000 quantifiable proteins with <10% missing values, as well as superior reproducibility and accuracy compared with other existing DIA methods.

Studying and Realizing the Based-Intelligent IoT System for Pipeline Cathodic Protection

Cathodic protection (CP) emerges as the optimal approach for mitigating metal corrosion in pipeline networks. To ensure the continued efficiency of the CP system, monitoring the potential distribution throughout the network is crucial. In distribution networks, the pipeline potential is influenced by time-varying environmental factors, making it challenging to estimate the potential at locations away from the measurement point. This paper presents a proposed CP system for pipelines, utilizing an intelligent IoT system. The sensor nodes of the system designed based on the STM32 microcontroller perform the measurement of voltages from the reference electrodes, process the signal as well as perform wireless communication about the control stations via LoRa (Long Range Radio) communication. Besides, the control stations are designed to implement voltage compensation control through autotransformer and to communicate with the server through the GPRS communication. The objective is to deploy an affordable system capable of effectively monitoring and regulating the potential of the pipeline at a designated measurement location in industrial plants.

Quantitative Time-Course Analysis of Osmotic and Salt Stress in Arabidopsis thaliana Using Short Gradient Multi-CV FAIMSpro BoxCar DIA

A major limitation when undertaking quantitative proteomic time-course experimentation is the tradeoff between depth-of-analysis and speed-of-analysis. In high complexity and high dynamic range sample types, such as plant extracts, balance between resolution and time is especially apparent. To address this, we evaluate multiple compensation voltage (CV) high field asymmetric waveform ion mobility spectrometry (FAIMSpro) settings using the latest label-free single-shot Orbitrap-based DIA acquisition workflows for their ability to deeply quantify the Arabidopsis thaliana seedling proteome. Using a BoxCarDIA acquisition workflow with a -30 -50 -70 CV FAIMSpro setting, we were able to consistently quantify >5000 Arabidopsis seedling proteins over a 21-min gradient, facilitating the analysis of ∼42 samples per day. Utilizing this acquisition approach, we then quantified proteome-level changes occurring in Arabidopsis seedling shoots and roots over 24h of salt and osmotic stress, to identify early and late stress response proteins and reveal stress response overlaps. Here, we successfully quantify >6400 shoot and >8500 root protein groups, respectively, quantifying nearly ∼9700 unique protein groups in total across the study. Collectively, we pioneer a short gradient, multi-CV FAIMSpro BoxCarDIA acquisition workflow that represents an exciting new analysis approach for undertaking quantitative proteomic time-course experimentation in plants.

Suppression Strategy of Subsynchronous Oscillation Based on Dynamic Voltage Compensation Control for Grid-Forming D-PMSG in Weak Grid

The virtual impedance can suppress the low-frequency oscillation effectively caused by the power coupling effect for the grid-forming direct-drive permanent magnet synchronous generator (D-PMSG). However, there are few studies on the influence of virtual impedance on the subsynchronous oscillation caused by the interaction between the grid-forming D-PMSG and the weak grid. In this paper, the mechanism of virtual impedance improving the stability of virtual synchronous generator (VSG) control for the converter is revealed from the perspective of power coupling, and the influence of virtual impedance on the system stability in subsynchronous frequency range was analysed based on the sequence impedance model. The analysis results show that the virtual inductance cannot effectively improve the oscillation suppression effect, but the virtual resistance can greatly improve the damping characteristics of the system which has a good oscillation suppression effect. However, excessive increase in virtual resistance will cause power coupling oscillation, even subsynchronous oscillation, which shows limitations in subsynchronous oscillation suppression. To solve the problem, a dynamic voltage compensation control method based on active disturbance rejection control (ADRC) was proposed, and the parameters are designed by bandwidth method. The method can suppress the subsynchronous oscillation effectively in a certain frequency range under different grid strength and disturbance conditions. And it shows strong adaptability and good system robustness in weak grid. Finally, the effectiveness of the proposed oscillation suppression strategy was verified by time domain simulation.

Voltage Detection-Based Selective Harmonic Current Compensation Strategies for Photovoltaic Inverters

Voltage and current detection-based harmonic current compensation (VDB-HCC and CDB-HCC, respectively) strategies allow the use of photovoltaic (PV) inverters to enhance the grid power quality. CDB-HCC strategies require converter hardware retrofit by inserting an extra current sensor to measure load or downstream grid currents. On the other hand, VDB-HCC strategies are straightforward solutions employing only embedded measurements used for protection, control, and synchronization purposes. This paper provides a comprehensive comparison of three VDB-HCC strategies: VDB-HCC based on a single current loop (SCL); VDB-HCC based on dual parallel current control loops (DCL); and VDB-HCC based on parallel voltage and current control loops (VCL). The comparison includes the requirement of harmonic detection algorithms, PV array maximum power point tracking (MPPT) performance, stability over grid impedance variations and inverter power rating, steady-state harmonic compensation, enabling transient response, and computational burden. Experimental results using a 1.5-kW commercial PV inverter are conducted. Based on distributed HCC applications by PV systems, VCL has shown the best performance in terms of voltage distortion reduction under weak grids.

Improved Single-Phase UPQC With Integrating Auxiliary Capacitor for Power Rating Reduction

Unified Power Quality Conditioner (UPQC) can well achieve comprehensive control for power quality. However, the power rating reductions of the series side and parallel side of the back-to-back connected converters in UPQC are hard to be achieved simultaneously, and they even restrict each other. In this paper, a new topology of UPQC is proposed. It has an LC filter coupled with an external capacitor at the series part. Besides, a comprehensive coordination strategy is proposed to operate the improved UPQC (iUPQC) at reactive power compensation (RPC) mode and voltage fluctuation compensation (VC). Specifically, to achieve the low power rating, the proposed control strategy makes the series part undertakes partial reactive power that needs to be compensated at the parallel side in RPC mode. At the same time, it makes the parallel side coordinates the series side to expand the optimal operation range in VC mode. Compared with the conventional UPQCs, the iUPQC can well reduce the power rating of back-to-back connected converters from both parallel and series sides. Moreover, the optimal parameters design method is also provided. Finally, the effectiveness of the proposed topology and control method is validated by both simulation and experimental results.

Single-Phase AC-DC-AC Multilevel Five-Leg Converter Based on a High-Frequency Transformer

This paper investigates a single-phase ac-dc-ac multilevel five-leg converter based on a high-frequency transformer. The system consists of a three-leg module with a full-bridge module connected to the shared part of the system. In the proposed configuration, the dc link of the three-leg module is supplied by the full-bridge module through a single active bridge converter. This feature improves the power quality and efficiency of the structure and simplifies the design of the control strategy compared to the conventional solution that uses floating capacitors. The proposed system is composed of a shunt unit and a series unit. The first one is responsible for compensating reactive power and harmonic currents, while the second one provides load voltage compensation against voltage sags and harmonics in the grid voltage. In addition, the proposed converter operates with low dc-link voltages in applications with the same input and output frequency, such as unified power quality conditioner. The model of the system, a space-vector pulse-width modulation and the overall control scheme are addressed. Simulations and experimental results are presented to confirm the feasibility of the proposed converter and the correctness of the design methodology.

Research on Bidirectional DC-DC Converters in Distributed Electric Propulsion Systems

This paper investigates bidirectional DC-DC converters in distributed electric propulsion systems, focusing on the dual active bridge (DAB) converter. To minimize voltage fluctuations in aircraft operating under complex conditions, a virtual voltage compensation control strategy based on active disturbance rejection (ADR-VVCC) is presented. The presented control strategy is grounded on the working characteristics under single-phase-shift (SPS) and introduces a virtual voltage to compensate for voltage fluctuations and degraded dynamic performance caused by the inherent uncertainty of converter parameters and power losses during the energy transfer process. The active disturbance rejection control is incorporated to replace traditional PI control, thereby enhancing the converter’s dynamic performance. Simulation outcomes demonstrate that the presented control strategy effectively improves the converter’s dynamic performance and maintains output voltage stability.

A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces

A single-ended transmitter achieves low power consumption with an integrated voltage modulation (IVM) scheme for memory interfaces. The transmitter preserves the power advantages of the ground (VSS)-terminated single-ended signaling by consuming no static power when transmitting logic-0s before the last bit of consecutive logic-0s (CLZs). All the intersymbol interference (ISI) accumulated during CLZs is compensated at once by the proposed IVM, which provides the unit interval (UI) spaced compensation voltage during the period of the last logic-0. The equalization, combining four-tap IVM and two-tap pull-up feed-forward equalization (FFE), allows the transmitter to be energy efficient without degrading the compensation effect. Per-UI basis IVM also has better immunity to noise and process, supply voltage, and temperature (PVT) variations than conventional phase equalization and pulsewidth modulation. The compensation effect and power consumption of IVM are also mathematically analyzed and compared with other conventional equalizations. A prototype chip fabricated in 65-nm CMOS has an area of 0.0168 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> and achieves a data rate of 16 Gb/s/pin over a transmission channel with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 12.6 dB loss, with an energy efficiency of 0.85 pJ/bit.

A Review on AC Voltage Variation Compensators in Low Voltage Distribution Network

Power quality is one of the most important aspects of the power system, especially in the distribution system. This system can be affected by such disturbances as short-term voltage sags/swells, long-term voltage increases/decreases over the normative limits, harmonic distortion, interruptions, etc. Maintaining the electricity quality parameters in accordance with the applicable standards in the power distribution system will require the use of additional devices. The scientific literature on the subject indicates a very wide range of different topologies of AC voltage compensators. In this paper, different power electronics-based AC voltage compensator topologies are reviewed that are typically used with distribution energy systems. A summary of the properties and functionalities of the selected topologies has been presented. This review focuses mainly on the different topologies of the Unified Power Quality Controllers (UPQC) and Hybrid Transformers (HT). This review is divided into several sections. The first section presents the topologies used in UPQC and HT. The second section discusses selected control methods for these systems. The third section presents the basic properties of the systems related to compensating changes in the supply voltage and improvement of power quality. The fourth section presents the use of UPQC and HT systems. Finally, a summary and conclusions are presented.

A Combined Gas-Phase Separation Strategy for ADP-ribosylated Peptides.

ADP-ribosylation (ADPr) is a post-translational modification that is best studied using mass spectrometry. Method developments that are permissive with low inputs or baseline levels of protein ribosylation represent the next frontier in the field. High-field asymmetric waveform ion mobility spectrometry (FAIMS) reduces peptide complexity in the gas phase, providing a means to achieve maximal ADPr peptide sequencing depth. We therefore investigated the extent to which FAIMS with or without traditional gas-phase fractionation-separation (GPS) can increase the number of ADPr peptides. We examined ADPr peptides enriched from mouse spleens. We gleaned additional insight by also reporting findings from the corresponding non-ADPr peptide contaminants and the peptide inputs for ADPr peptide enrichment. At increasingly higher negative compensation voltages, ADPr peptides were more stable, whereas the non-ADPr peptides were filtered out. A combination of 3 GPS survey scans, each with 8 compensation voltages, resulted in 790 high-confidence ADPr peptides, compared to 90 with GPS alone. A simplified acquisition strategy requiring only two injections corresponding to two MS1 scan ranges coupled to optimized compensation voltage settings provided 402 ADPr peptides corresponding to 234 ADPr proteins. We conclude that our combined GPS strategy is a valuable addition to any ADP-ribosylome workflow. The data are available via ProteomeXchange with identifier PXD040898.

Voltage Sag Detection and Compensation Signal Extraction for Power Quality Mitigation Devices

The importance of voltage quality is continuously increasing in electrical networks due to the rising manufacturing costs resulting from system faults and disturbances in utility dynamics. Researchers generally prefer reference-frame transformation-based methods to detect and mitigate these disturbances. However, these methods are adversely affected during unbalanced loading and disturbances due to their direct dependence on system dynamics (currents and voltages). In this study, a new and simple method based on Clarke transformation is proposed to detect disturbances and generate compensation signals for Power Quality Mitigation Devices. The aim is to address the deficiencies of existing approaches. Firstly, the Clarke transformation is introduced through the vector presentation. Then, the mathematical derivation of the proposed method is provided to enhance readers’ understanding. The voltage sag detection and compensation signal extraction of its control algorithm for a Dynamic Voltage Restorer is illustrated graphically. Subsequently, a simple power system is created using a simulation program. Balanced and unbalanced voltage disturbances are applied to the test system to demonstrate the validation of the proposed method under distorted system conditions. The results of voltage sag detection and compensation signal extraction for both the proposed and existing methods are compared at the end of the case studies.

A 0.26 [formula omitted]Vrms instrumentation amplifier based on discrete-time DC servo loop with successive-approximation-compensation technique and Chopper DAC Array

A low-noise instrumentation amplifier for bio-signal recording is proposed in this paper. One of the significant disturbances, electrode DC offset, is suppressed using the proposed successive-approximation-compensation (SAC) circuit based on a discrete-time DC servo loop with Chopper DAC Array. Firstly, the DC offset at the output is quantified using the SAR quantizer. Next, the digital code produced by the SAR quantizer is used to control the chopper DAC array. Finally, a suitable compensation voltage is generated and used directly to correct the electrode DC offset at the input of the chopper amplifier. By using the proposed compensation technique, the first-stage chopper amplifier’s quiescent operating state is unaffected. When a 50-mV DC offset voltage exists at the differential input, the SAC circuit can compensate the DC offset voltage close to zero in a relatively short time. At the same time, there are fewer capacitors, which significantly decrease the area consumption. The proposed instrumentation amplifier is implemented in a standard 0.18μm CMOS process. The experiment results show that over a bandwidth from 0.1 Hz to 100 Hz, an input referred noise of 0.26 μVrms at the TT corner has been attained. The total power consumption is about 13.72 μW at the supply voltage of 1.8 V. The gain of the instrumentation amplifier is about 39.15 dB and its Noise Efficiency Factor (NEF) is 2.76.

11 b 200 MS/s 28‐nm CMOS 2b/cycle successive‐approximation register analogue‐to‐digital converter using offset‐mismatch calibrated comparators

AbstractThis letter presents an 11 b 200 MS/s 28 nm CMOS 2b/cycle successive‐approximation register (SAR) analogue‐to‐digital converter (ADC). The offset calibration technique is proposed to reduce the comparator offset mismatch that degrades the linearity of the high‐resolution 2b/cycle SAR ADC. The offset mismatch is reduced to within 0.25 least significant bit (LSB) by generating a compensation voltage from capacitor‐resistor (C‐R) hybrid digital‐to‐analogue converters (DACs). The prototype ADC implemented in a 28‐nm CMOS process demonstrates measured differential and integral non‐linearities within 0.6 LSB and 1.73 LSB at 11 b resolution, respectively. The measured signal‐to‐noise‐and‐distortion ratio (SNDR) and spurious‐free dynamic range (SFDR) are 50.9 dB and 66.2 dB at Nyquist, respectively. The prototype ADC occupies an active die area of 0.115 mm2 and consumes 3.98 mW at a 1.1‐V supply voltage.

A Differential Rectifier With VTH Compensation for High-Frequency RF Inputs.

A CMOS differential-drive bootstrap (BS) rectifier achieving an efficient dynamic threshold voltage ( VTH)-drop compensation at high-frequency RF inputs is proposed for small biomedical implants with wireless power transmission. A bootstrapping circuit with a dynamically controlled NMOS transistor and two capacitors is proposed to implement a dynamic VTH-drop compensation (DVC). The proposed bootstrapping circuit dynamically compensates the VTH drop of the main rectifying transistors by generating a compensation voltage only when the compensation is required, improving the power conversion efficiency (PCE) of the proposed BS rectifier. The proposed BS rectifier is designed for an ISM-band frequency of 433.92MHz. A prototype of the proposed rectifier is co-fabricated in a 0.18- μm standard CMOS process with another configuration of the rectifier and two conventional BS rectifiers for fair performance comparison at various conditions. According to the measurement results, the proposed BS rectifier achieves better DC output voltage level, voltage conversion ratio, and PCE than the conventional BS rectifiers. With 0-dBm input power, 433.92-MHz frequency, and 3-k Ω load resistor, the proposed BS rectifier achieves a peak PCE of 68.5%.

Voltage Control in LV Distribution Grid Using AC Voltage Compensator with Bipolar AC/AC Matrix Choppers

The modern low-voltage distribution system is exposed to frequent changes in voltage amplitude due to the presence of high-power receivers with variable operating characteristics as well as distributed renewable energy sources whose generation levels depend on weather conditions. Maintaining the appropriate parameters related to power quality in the context of permissible voltage levels more and more often requires the use of additional voltage regulators. These are static systems in which the values of taps on transformers are changed, or dynamic compensators using power electronic converters. This article presents the continuation of research on one of the proposals of AC voltage compensators based on a bipolar AC/AC converter. The general properties of the presented system are reviewed and an analysis of the range of generated output voltages depending on the phase shift of the compensating voltage are presented. The next part of the article presents the formulas for calculating the duty cycle factors for the control functions of individual converters. The verification of the determined dependencies is presented on the basis of simulation tests of the proposed system. At the end of this article, the disadvantages of the proposed open-loop control system regulation and a proposal for further research are indicated.

Power quality enhancement by using Z-DVR based series voltage compensation with black widow optimization technique

In distribution system, voltage quality issues are the most concerning disturbances influencing the power quality (PQ). As a result, to alleviate this PQ concerns such as sag, swell, fluctuation, interruption, and harmonics on the sensitive load, the series voltage compensator dynamic voltage restorer (DVR) is utilized. Furthermore, a Z-source inverter (ZSI) based DVR is proposed in this paper to improve the power system's voltage restoration properties. To compensate the voltage concerns which is occurs in passive and transmission components, the 3-φ Z-DVR inverter with proportional integral derivative (PID) controller tuned by black widow optimization (BWO). By short circuiting the legs of inverter in the ZSI, prepare the possibility of buck and boost in voltage and utilize the LC impedance grid which incorporated power source to inverter circuit. In addition, to obtain the injecting voltage, PID control scheme for ZSI based DVR is proposed in this paper. The proposed modelling and simulation of DVR is implemented in MATLAB/Simulink tool and the outcomes are analyzed. Furthermore, reduction in voltage concerns, and total harmonics distribution (THD) with BWO tuned PID controller is superior which is 1.01% when compared with existing methods such as Harris Hawks optimization (HHO) based PID, genetic algorithm (GA) based PID controller.

Performance and Comparison of Voltage Compensation Based on Hybrid Metaheuristic Technique Tuned Z-Dynamic Voltage Restorer

Performance and Comparison of Voltage Compensation Based on Hybrid Metaheuristic Technique Tuned Z-Dynamic Voltage Restorer

A fully connected neural Network-based voltage compensation method for accurate reconstruction in brain electrical impedance tomography

Acute cerebral ischemia is commonly accompanied by cerebral edema. With brain electrical impedance tomography (EIT), it is possible to monitor conductivity variation during dehydration treatment of the cerebral edema. However, the scalp is also dehydrated when dehydrating brain tissue which exerts a large impact on boundary measurement. Consequently, reconstruction quality of cerebral edema is seriously affected. To reduce the influence of scalp dehydration, a voltage data compensation method based on a fully connected neural network (FCNN) is proposed in this work. With this method, the voltage measured when brain tissue and scalp are simultaneously dehydrated can be compensated. To evaluate the performance of the proposed method, reconstruction of simulated cerebral ischemia in a three-layer head model is conducted. Images reconstructed with the compensated voltage data are compared with the results when there is no compensation. Besides, quantitative comparison is performed. The results indicate that it is almost impossible to identify the simulated cerebral ischemia without voltage compensation. In contrast, cerebral ischemia can be much more accurately reconstructed when the measured voltage is compensated with the proposed method.

Operation Algorithm of Electrical Reconfiguration Device and Voltage Compensation Device for PV Module

Operation Algorithm of Electrical Reconfiguration Device and Voltage Compensation Device for PV Module