Voltage Balancing Strategy Research Articles

Analysis of pulsation concentration effect related to sorting-algorithm-based voltage-balancing strategy in an MMC system

The sorting-algorithm-based voltage-balancing strategy in modular multilevel converter (MMC) changes the submodule operating state to regulate the charging and discharging time of submodule capacitors and to balance the capacitor voltages. However, these changes and regulations can lead to the pulsation concentration effect in the switching drives, thus significantly decreasing the efficiency of the system and severely deteriorating the system operating performance. Therefore, this study first proposes the mechanism of pulsation concentration effect in the voltage-balancing strategy. A quantitative analysis of the relations between the pulsation concentration effect, the voltage-balancing strategy and corresponding deteriorations is then provided, indicating the root cause of such effect and types of associated deteriorations, such as switching drive redistributions and switching frequency fluctuation in the MMC system. Based on the above analysis, an optimal voltage-balancing strategy is then provided to effectively suppress the pulsation concentration effect; and a code restructuration method is presented at the same time to further avoid the extra switching actions and decrease the switching loss. The deteriorations caused by the pulsation concentration effect and effectiveness of proposed optimal voltage-balancing strategy are finally demonstrated via experiments.

Modified LUT-based DTC of NPC 3-Level Inverter fed Sensorless IPMSM Drive with DC Link Voltage Balance

In the proposed work, a modified look-up table-based direct torque control (DTC) scheme is reported for a neutral point-clamped three-level inverter-fed interior permanent magnet synchronous motor drive. In the classical DTC scheme, there are significant torque and flux ripples in the drive due to low number of available switching states. To reduce the oscillations in torque and flux, a three-level inverter-operated IPMSM drive is discussed. In a three-level inverter, the increased count of active voltage vectors is results in more sinusoidal output waveforms. Moreover, stator flux plane has 12 sectors in the proposed work unlike classical DTC. Besides, the higher level of flux and torque hysteresis comparators is implemented. DC link capacitor voltage balancing scheme is also instigated to minimize voltage stress on semiconductor devices, improve stator current THD and increased capacitor life. Based on the sector information, flux and torque hysteresis output and capacitor voltage balance logic, an improved LUT is established and explained for a three-level DTC scheme. Consequently, improved stator current (THD) and decrement in torque and flux ripples are observed. To make the system robust, model reference adaptive control (MRAC) based sensorless speed estimation algorithm is realized. The proposed DTC scheme is compared with a two-level inverter-fed and a three-level-inverter-fed DTC scheme without DC link voltage balance strategy. To carry out the analysis, MATLAB/Simulink environment is utilized. Moreover, to validate the simulation results, experimental analysis of the proposed technique is carried out using dSPACE1104.

Novel multi‐level inverters with flyback high frequency link

A novel topological family of multi-level inverters with flyback high frequency link is proposed in this study. The inverters can transfer high DC voltage into regulated sinusoidal voltage with low total harmonic distortion (THD). The circuit configuration consists of high DC input voltage, DC-link capacitors, novel multi-level conversion unit, high frequency flyback transformer, cyclo-converter, output filter capacitor and AC load. This topological family includes diode-clamp type full-wave mode, hybrid-clamp half-bridge mode, multi-end mode and improved multi-end mode. To achieve reliable multi-level inversion and overcome DC-link capacitor voltages unbalance, multi-carrier modulation and DC-link capacitor voltage balancing strategy are presented. In addition, steady principle and AC small-signal model are analysed. Simulation and experimental results are given to prove that the novel flyback high frequency isolated multi-level inverters have the following advantages such as the high frequency electrical isolation, the bi-directional power flow, the two-stage power conversion (DC-high frequency AC (HFAC) - low frequency AC (LFAC)), the lower voltage stress of power switches and the low THD of output voltage.

Voltage-Balancing Strategy for Three-Level Neutral-Point-Clamped Cascade Converter under Sequence Smooth Modulation

Three-level neutral-point clamped cascaded converters (3LNPC-CC) are widely used in high power nigh-voltage applications. This paper mainly discusses the open-circuit fault in DC-side of the 3LNPC-CC. Optimized by the sequence pulse modulation, a sequence smooth modulation (SSM) is proposed to keep the DC-side voltage balance while the 3LNPC-CC suffers open-circuit fault from DC-side. The SSM found efficient switch-state path through a 3-D cube model and simplified the path from thousands of switch state. The SSM avoids the complex calculation in the voltage-balancing modulation, while the dynamic character of it was less influenced. At the same time, the modulation changes the voltage level smoothly and balances the fault DC-side voltage effectively. The characters of the proposed modulation are verified by the simulation and the experiment.

Improved post‐fault operation strategy for a cascaded H‐bridge based STATCOM

This study presents a multi-fault tolerant strategy for a cascaded H-bridge (CHB) based static synchronous compensator (STATCOM) with star configuration. A new method for post-fault operation of CHB-STATCOM is proposed, where after switch failures, the full-bridge (FB) submodules are used as two different types of half-bridge submodules named as positive half-bridge (P-HB) and negative half-bridge (N-HB). Using a modified level shift pulse-width modulation technique, a combination of FB, P-HB and N-HB submodules is employed in three legs of the converter to generate the maximum attainable ac side voltage in post-fault condition. In order to restore the nominal capacity of CHB-STATCOM, the capacitor voltage of submodules is increased based on the type and number of switch failures. Furthermore, by utilising a voltage balancing strategy, the voltages of submodules’ capacitors are kept balanced and regulated at the desired value in post-fault condition. The feasibility and effectiveness of the proposed strategy is validated on a scaled-down 9-level CHB-STATCOM laboratory prototype.

Improved equivalent circuit model of MMC and influence analysis of simulation time step

Modelling and simulation of a high voltage-level modular multilevel converter (MMC) is challenging due to large amount of semiconductor switches, various submodule (SM) circuits, and different operating conditions. Several equivalent models have been proposed for modelling and simulation in system level, which did not consider an industrial or digital controller. To accelerate MMC station design, a highly efficient model is needed with considering control parameters/strategies and accurate dynamics of voltage/current. In this study, an improved equivalent circuit model (ECM) is developed for large-scale system simulation and MMC station design. The proposed ECM considered the MMCs based on various SM circuits under different operating conditions. It can generate bipolar arm voltage and simulate static compensator under dc fault condition. Based on the proposed ECM, the influences of simulation time step on accuracy/efficiency are investigated by considering the sample period and voltage balancing strategies. This research is conducted based on an MMC-HVDC system in the PSCAD/EMTDC software. The study results demonstrate the effectiveness of the proposed ECM and show the relationship between simulation accuracy/efficiency and control/simulation parameters for determining simulation time step. Based on study results, the computational efficiency of proposed model is not significantly affected by the complexity of SM circuit.

A Comprehensive Review of Capacitor Voltage Balancing Strategies for Multilevel Converters Under Selective Harmonic Elimination PWM

In recent decades, applications of selective harmonic elimination pulsewidth modulation (SHE-PWM) have been extended from two-level to multilevel converters (MLCs). For most MLC topologies, one of the main challenges of using SHE-PWM lies on capacitor voltage balancing, especially with very low switching frequency in high-power applications. Due to the broad variety of MLCs, it is of great difficulty to develop a generalized capacitor voltage balancing method under SHE-PWM that is suitable for all topologies. In order to further facilitate the industrial applications of SHE-PWM on MLCs, this article provides a comprehensive review of the state-of-the-art capacitor voltage balancing strategies for MLCs under SHE-PWM. The voltage balancing methods in this article include self-balancing control, charge amount regulation, zero-sequence harmonic adjustment, redundant switching angle sets adjustment, angle modification, selective harmonic elimination model predictive control, space voltage vectors adjustment, and redundant states adjustment. Detailed comparisons of the eight voltage balancing strategies under SHE-PWM are presented to facilitate the selections of the most suitable method for specific applications. Moreover, discussions on open questions and future trends of this topic are also presented, to motivate future research and explore new alternatives.

Implementation of Five-Level DPWM on Parallel Three-Level Inverters to Reduce Common-Mode Voltage and AC Current Ripples

Conventional reduced common-mode voltage discontinuous pulsewidth modulation method for a three-level inverter can reduce the common-mode voltage and switching transitions compared with continuous modulation. However, it suffers from poor output current quality and cannot provide additional performance enhancements when applied directly on parallel three-level inverters. Based on the interactions between the parallel inverters, this article reveals that dual parallel three-level inverters could be analyzed and controlled as a single five-level inverter. Based on this idea, a novel five-level discontinuous modulation method is therefore proposed to further reduce the common-mode voltage of the system by half, in addition to dramatically improving the output current quality compared with conventional three-level method. The specific implementation process is explained in detail, and a unique switching sequence design is developed considering keeping zero average circulating current, which is crucial to the proper function of parallel operation. Furthermore, a neutral point voltage balancing strategy through alternatively applying charging and discharging switching sequences is proposed for the five-level modulation process, which can effectively restore the neutral point balance in case imbalance occurs. The effectiveness and advantages of the proposed method are verified by both simulation and experimental results.

Multiple boundaries sliding mode control applied to capacitor voltage-balancing systems

Capacitor voltage-balancing systems are usually applied to power electronic circuits. The main issue in these systems is equalising the voltage of a large number of capacitors connected to a voltage source in serial or parallel arrangements. A particular application of the capacitor voltage-balancing systems is found in modular multilevel converters (MMC). The voltage balancing of the floating capacitors in the submodules of the MMC during its pre-charging operating stage is a key issue since it is a critical task for the correct operating of these converters. The stability analysis of an active voltage balancing strategy for pre-charging MMCs is addressed in this paper. The adopted voltage-balancing strategy consists in adding a resistance to each submodule of the MMC by means of a controlled switch. These switches are being controlled by a sliding mode control algorithm with multiple boundaries (discontinuity surfaces of high co-dimension). These systems are essentially discontinuous piecewise smooth dynamical systems (Filippov systems) commanded by electronic switches. In this paper, the local stability of the voltage balanced system is analytically proven for an arbitrary number of submodules. In addition, a detailed analysis of the global dynamics of this system with two submodules and two switching boundaries sliding mode control is presented. Simulation results obtained on a MMC with 10 submodules are shown to validate the theoretical analysis.

Analysis of Capacitor Charging Characteristics and Low-Frequency Ripple Mitigation by Two New Voltage-Balancing Strategies for MMC-Based Solid-State Transformers

This article investigates and compares various modulation methods and capacitor voltage-balancing algorithms of a modular multilevel converter for solid-state transformer applications. Characteristics of capacitor charging and discharging are analyzed for the existing single-step alternating voltage balancing and the conventional sorting algorithms with phase-shift (PS) modulation and nearest level control (NLC) methods. Based on the analysis, the single-step alternating algorithm leads to a low-frequency voltage ripple, while the conventional sorting algorithm introduces additional switching actions. To address these issues, two new voltage-balancing algorithms are proposed: a multistep alternating voltage-balancing algorithm, and a currentless sorting algorithm. The performance of the proposed algorithms with the PS and NLC modulation methods is comprehensively investigated and compared based on theoretical analysis and experimental results. The study results demonstrate the capability of the proposed methods to balance capacitor voltages while reducing the low-frequency voltage ripple and avoiding additional switching actions.

Multilevel Converters With Symmetrical Half-Bridge Submodules and Sensorless Voltage Balance

H-bridge-based multilevel converters (e.g., cascaded H-bridge converters) benefit from modularity and scalability. However, they suffer from the complexity and costs associated with a large count of semiconductor switches, together with their drivers and peripheral circuits, as well as higher conduction losses as compared to half-bridge-based counterparts, as two switches in each submodule must simultaneously conduct to provide a current path. To reduce the number of active switch semiconductors and conduction losses, this article proposes novel multilevel converters with symmetrical half-bridge submodules. The symmetrical half-bridge submodule features a bipolar voltage output, a reduced switch count, and simplicity. Furthermore, this article proposes a sensorless voltage balance scheme that successfully gets rid of capacitor voltage mismatch problems through diodes and submodule parallelization. This scheme can greatly reduce capacitor voltage ripples, thereby allowing the saving of dc capacitances, particularly in the case of numerous submodules. Finally, simulation and experimental results validate the superiority of the proposed multilevel converters and voltage balance scheme.

DC‐link capacitor voltage balance strategy of independent double three‐phase common bus five‐level NPC/H‐bridge inverter based on finite control set

This study aims at the DC-link capacitor voltage imbalance problem of independent double three-phase common bus five-level neutral point-clamped/H-bridge inverter, which is applied to an electromagnetic launch system under instant high-power and high-current conditions. First, the traditional method of voltage balance strategy based on redundant vectors is described, and the key factors leading to the DC-link capacitor voltage fluctuation is analysed in detail. Second, the objective function is constructed to predict the variation trend of DC-link capacitance voltage difference. Third, an optimised voltage balance strategy is proposed. At first, the optimised strategy calculates the variation trends of the voltage difference for all three-phase switch vector combinations. Then, the results make up a voltage balance finite control set. At last, compare the results in the set to select the vector combination corresponding to the minimum variation for output. Finally, tested by the semi-physical real-time simulation platform, and the proposed optimised voltage balance strategy is verified effective for improving DC-link capacitor voltage imbalance and inhibiting the voltage difference fluctuation.

Multi-loop voltage control strategy of half-bridge voltage balancers with current sensorless scheme

This paper proposes a multi-loop voltage balancing strategy for half-bridge voltage balancers. The proposed multi-loop scheme consists of a voltage controller and a current variation controller without current sensors. The proposed current variation controller (CVC) aims to regulate the derivative of the average inductor current to be zero at the steady-states as well as to increase the damping of the entire control loop. Furthermore, the CVC is implemented based on a current sensorless scheme. For this purpose, a simple method for detecting current variation by using dc-link voltages and a control model is also proposed. To secure the stability of the proposed CVC with the current sensorless method, a well-known type II regulator is adopted, and its design procedure is detailed. The proposed multi-loop strategy is applied to a 2.4-kW half-bridge voltage balancer. Both simulation and experimental results show good agreements with the theoretical analyses.

A Voltage Balancing Scheme for Series IGBTs to Increase Their Expected Lifetime in Pulsed Load Applications

Clamp mode resistor capacitor diode (CMRCD) snubbers have a simple and easy implementing structure. They have been widely adopted in the pulsed power supplies to provide a safe operating condition for the series insulated gate bipolar transistors (IGBTs). The main problem of the CMRCD snubbers is their poor performance in the voltage balancing of the series IGBTs. They are essentially overvoltage protectors and clamp the voltage of the IGBTs in a probable potentially dangerous condition. This issue diminishes the expected lifetime of the series IGBTs, where a number of them face a higher level of the voltage than that of the others. The unbalanced voltage of the series IGBTs will result in a lower value of the expected lifetime of the series IGBTs. For improving the expected lifetime of the series IGBTs a CMRCD snubber with balanced voltage sharing for the series IGBTs is proposed. Adopting this proposal will lead to the balanced voltage sharing of the series IGBTs, even in the blocking voltage below the nominal designed value. Consequently, the highest value of the lifetime is estimated for the series IGBTs in the stack. The simulation and experimental results truly demonstrate the effectiveness of the proposed structure.

Unified Selective Harmonic Elimination Control for Four-Level Hybrid-Clamped Inverters

A unified selective harmonic elimination (SHE) control for four-level hybrid-clamped (4L-HC) inverters is presented in this article. With this unified strategy, all four-level switching patterns and the corresponding switching angles can be obtained simultaneously by solving one group of unified four-level SHE equations. Therefore, the optimal switching pattern of each modulation index with the designed optimization goal can be evaluated, and the best overall output performance is achieved. In order to ensure the proper operation of the 4L-HC inverter, the voltages across the three-phase flying capacitors and three dc-link capacitors must be controlled and balanced at one-third of the dc-link voltage. The proposed voltage control method is based on redundant switching states and introducing a slight variation to the precalculated switching angles, which extends or limits the conduction time of capacitors depending on voltage deviation and current direction. The effect of switching angle variations on the harmonic performance is also studied. Simulation and experimental results are presented to confirm the validity of the unified model and the proposed voltage-balancing strategy. Comparisons with phase-shifted pulsewidth modulation (PWM) are also presented to demonstrate that the implemented SHE-PWM could significantly reduce the switching frequency while keeping the capacitor voltages well balanced within the expected band limits.

Common-Mode Resonance Damping and DC Voltage Balancing Strategy for LCCL-Filtered Three-Level Photovoltaic Grid-Tied Inverters

The leakage current caused by common-mode (CM) voltage is a critical issue in transformerless three-level photovoltaic (PV) inverters, which can increase the output current distortion, bring extra power losses, aggravate the electromagnetic interference, and even cause degradation of the panels and safety issues. The LCCL filter was proven to be effective to mitigate the leakage current, whose capacitor is split into two parts, and the common point of the smaller one is connected to the neutral-point (NP) of the DC-link. However, the LCCL-filtered three-level inverter suffers from the CM resonance of the neutral current and the NP voltage imbalance. Therefore, this paper proposes a CM resonance damping and NP voltage balancing strategy for the transformerless LCCL-filtered three-level PV inverter. A novel dual-cascade-loop with a dc voltage-difference outer-loop and a neutral-current inner-loop is proposed to control the CM voltage with a αβγ-frame space vector pulse width modulation (SVPWM) for damping the CM resonance and balancing the NP voltage. At last, the effectiveness of the proposed strategy is experimentally validated through a 10 kW transformerless LCCL-filtered T-type three-level PV inverter.

Switching Loss Balancing Technique for Modular Multilevel Converters Operated by Model Predictive Control Method

The sorting algorithm is the most widely accepted capacitor voltage balancing strategy for a modular multilevel converter. This strategy offers to keep the balance among submodule capacitor voltages under all of the modular multilevel converter working conditions. However, this method generates unnecessary switching transitions in submodules, which results in high switching frequency and switching loss, and uneven distribution of switching transitions and switching loss among submodules (SMs). In this paper, a simplified switching loss balancing control strategy was proposed in order to handle these issues. The proposed approach adjusted the submodule selection process of the sorting algorithm by taking into consideration the number of switching transitions in addition to the capacitor voltages. Even distribution of switching transitions and switching loss was achieved, and the average switching loss was reduced at the cost of slightly increasing the capacitor voltage fluctuations. The effectiveness of the proposed approach was verified through both simulation and experimental results.

Voltage-Balancing Strategy for Three-Level Neutral Point Clamped Cascade Converter under Sequence Pulse Modulation

In response to the unbalanced DC-port fault of three-level neutral point clamped cascaded converter (3LNPC-CC), a sequence pulse modulation (SPM) voltage-balancing strategy is proposed in this paper to balance DC-link voltage, not only within the module but also among modules. With the steps of carrier cascaded calculation and sequence pulse generator, the voltage level of cascaded modules would take a smooth transition. Then the limitation of the SPM strategy is calculated according to the law of volt-second balance and the law of energy conservation. The proposed strategy has the advantage of simple calculation and control stability. Simulation and experimental results show the superiority of the proposed strategy.

Novel space vector-based control scheme with dc-link voltage balancing capability for 10 switch converter in bipolar hybrid microgrid

Abstract Bipolar hybrid microgrid application is enhancing in power systems since this type of microgrid owns a DC and AC bus simultaneously, feeds local loads with local resources, and presents two dc voltage levels to users and resources. Interlinking converter (ILC) is the most important part of the microgrid structure due to its essential responsibilities in various applications. In this paper, a 10 switch converter is presented as an ILC for bipolar hybrid microgrid that advantages from both two and three-level converters’ benefits simultaneously, plus it is applicable to a wide variety of power ranges. This paper presents a novel space vector modulation (SVM) for 10 switch converter in order to reduce total harmonic distortion (THD) and increase the dc-link voltage utilization in comparison to prior carrier-based modulation methods. Also, a simplified, full-scale dc-link voltage balancing strategy is proposed for this converter. The performance of existing dc-link voltage balancing strategies for carrier-based modulation method which are an extension to the general control structure of a grid-tied ILC is compared to the method presented in this paper that shows the superiority of the proposed robust full-scale balancing strategy and the proposed SVM method. Moreover, the structure of grid-tied ILCs is upgraded to eliminate low order harmonics.

A Modular Multilevel Converter With Self-Voltage Balancing Part II: Y-Matrix Modulation

In Part I of this paper, the self-voltage balancing nature of modular multilevel converters (MMCs) has been proven mathematically. To utilize this merit of MMCs, a novel modulation, namely Y-matrix modulation (YMM), is proposed to transform the math analysis of Part I into modulation practice. With the proposed YMM, MMCs have secured self-voltage balancing. Conventionally, either a complicated voltage balancing control, or extra components are embedded in MMCs to balance the capacitor voltage. Compared to conventional MMC capacitor voltage balancing strategies, YMM features simple algorithms and good reachability to high-level MMCs while maintaining the original half-bridge submodule topology. To simplify the analysis, YMM is introduced to two-level and three-level MMCs as examples. Then, the generalized YMM is derived, which is suitable for high-level MMCs. Several YMM based MMC case studies are provided for verification purposes.