Analog Voltage Research Articles

The Design of a Low-Noise CMOS Image Sensor Using a Hybrid Single-Slope Analog-to-Digital Converter.

In this study, we describe a low-noise complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a 10/11-bit hybrid single-slope analog-to-digital converter (SS-ADC). The proposed hybrid SS-ADC provides a resolution of 11 bits in low-light and 10 bits in high-light. To this end, in the low-light section, the digital-correlated double sampling method using a double data rate structure was used to obtain a noise performance similar to that of the 11-bit SS-ADC under low-light conditions, while maintaining linear in-out characteristics. The CIS with the proposed 10/11-bit hybrid SS-ADC was fabricated using a 110 nm 1-poly 4-metal CIS process. The measurement results showed that dark random noise was reduced by 8% in low light when using the proposed hybrid SS-ADC, compared with the existing 10-bit ADC. Additionally, in the case of high brightness, when using a 10-bit resolution, the dynamic power consumption decreased by approximately 31%, compared to the 11-bit ADC. The total power consumption is 3.9 mW at 15 fps when the analog, pixel, and digital supply voltages are 3.3 V, 3.3 V, and 1.5 V, respectively.

Comparative Analysis of Analogue and Digital Methods for Magnetic Flux Estimation in the Core of a Medium-Voltage Voltage Transformer Operating Under Ferroresonance Conditions

The main objective of the research described in the article was to determine the following: Is it possible to estimate the magnetic flux linkage in the core of a voltage transformer using analogue or digital methods? Will it be possible to estimate it approximately both in the normal state and in the state of deep core saturation (ferroresonant state)? The research aimed to identify the advantages and disadvantages of both proposed estimation methods. As part of the research described in this paper, a simulation model was developed and executed in the MATLAB/Simulink environment to generate a series of secondary voltage and flux waveforms in voltage transformers. The secondary voltage and flux waveforms were modelled under ground fault conditions, initiating ferroresonance oscillations in the medium-voltage network. To determine the associated flux from the simulated secondary voltages of the voltage transformers, an analogue integration circuit, a voltage analogue input circuit and a numerical integration algorithm with offset elimination were developed and implemented in an STM32 microcontroller. The obtained reference flux waveforms were used to verify the accuracy of the estimation of flux waveforms obtained using the analogue and digital methods. As a result, it was determined that both methods allow for a relatively accurate estimation of the periodic component of the magnetic flux. It also presented how both methods respond to the presence of slowly changing (aperiodic) components. Possible applications were proposed in order to create an innovative criterion for detecting ferroresonance oscillations.

ROVIGA: Model-Driven Soil Moisture Sensor for Internet-Connected Plant Pot

The soil moisture sensor provides numerical measurements to detect changes in soil moisture using an analog voltage output. This research aims to develop a capacitive sensor based on a statistical model to detect soil moisture for plant watering, leveraging the Internet of Things (IoT). The analysis was conducted using polynomial and linear regression models. The modeling process was based on primary gravimetric test results from dried soil. The best model coefficients, selected based on the highest adjusted R-squared value, were used for sensor recalibration. A watering system was then developed using an Arduino and a model-driven capacitive soil moisture sensor integrated into an internet-connected smart plant pot, enabling remote control via a mobile phone. The research findings indicate that the 8th-order polynomial model, with the highest adjusted R-squared value of 0.9583, is the most accurate. The smart watering system using the model-driven capacitive sensor achieved soil moisture prediction outcomes ranging from 0.08 to 1.01 for 150 to 418 sensor data points. The internet-connected smart plant pot allows precise and real-time control, delivering notifications and enabling actions when plants require watering.

Scalable Multispecies Ion Transport in a Grid-Based Surface-Electrode Trap

Quantum processors based on linear arrays of trapped ions have achieved exceptional performance, but scaling to large qubit numbers requires realizing two-dimensional ion arrays as envisioned in the quantum charge-coupled device (QCCD) architecture. Here, we present a scalable method for the control of ion crystals in a grid-based surface-electrode Paul trap and characterize it in the context of transport operations that sort and reorder multispecies crystals. By combining cowiring of control electrodes at translationally symmetric locations in each grid site with the sitewise ability to exchange the voltages applied to two special electrodes gated by a binary input, site-dependent operations can be achieved using only a fixed number of analog voltage signals and a single digital input per site. In two separate experimental systems containing nominally identical grid traps, one using Yb+171−Ba+138 crystals and the other Ba+137−Sr+88, we demonstrate this method by characterizing the conditional intrasite crystal reorder and the conditional exchange of ions between adjacent sites on the grid. Averaged across a multisite region of interest, we measure subquanta motional excitation in the axial in-phase and out-of-phase modes of the crystals following these operations at exchange rates of 2.5 kHz. In this initial demonstration, the logic controlling the voltage exchange occurs in software, but the applied signals mimic a proposed hardware implementation using crossover switches. These techniques can be further extended to implement other conditional operations in the QCCD architecture such as gates, initialization, and measurement. Published by the American Physical Society 2024

Chaotic dynamics in a class of generalized memristive maps.

The memory effects of the memristors in nonlinear systems make the systems generate complicated dynamics, which inspires the development of the applications of memristors. In this article, the model of the discrete memristive systems with the generalized Ohm's law is introduced, where the classical Ohm's law is a linear relationship between voltage and current, and a generalized Ohm's law is a nonlinear relationship. To illustrate the rich dynamics of this model, the complicated dynamical behavior of three types of maps with three types of discrete memristances is investigated, where a cubic function representing a kind of generalized Ohm's law is used, and this cubic function is a simplified characteristic of the famous tunnel diode. The existence of attractors with one or two positive Lyapunov exponents (corresponding to chaotic or hyperchaotic dynamics) is obtained, and the coexistence of (infinitely) many attractors is observable. A hardware device is constructed to implement these maps and the analog voltage signals are experimentally acquired.

A 28 GHz balun‐first LNA with db‐linear 32 db gain range for 5 G applications

AbstractThis letter presents a 28 GHz balun‐first low noise amplifier (LNA) featuring a wide dB‐linear variable gain range. The architecture of LNA includes three‐stage cascode amplifiers. An integrated balun at the input stage provides RF ESD protection and converts a single‐ended signal to a differential one (S‐to‐D). A transformer‐based dual‐resonant matching network is designed and analyzed to achieve wideband performance. To realize a continuous dB‐linear variable gain range and consistent input/output matching, gain control is implemented in the second stage using a 5‐bit digital‐to‐analog converter (DAC) for a 32 dB gain range. The DAC can generate a nonlinear analog voltage to control the gate of the common‐gate transistor in the second cascode stage, inversely compensating for the nonlinear gain variations of the cascode amplifier. The LNA is fabricated in 65‐nm CMOS process with a core size of 0.154 mm². Measurement results exhibit a maximum gain of 33.5 dB and a minimum noise figure (NF) of 3.65 dB with a 3‐dB bandwidth of 23–29.5 GHz. The measured variable gain range is approximately 32 dB across 32 different gain states, with a linear gain step of ~1 dB per state and an IP1dB ranging from −6.5 dBm to −35.25 dBm. The power consumption is 35.4–48 mW from a 1.2 V supply voltage.

Open-source synthetic photoplethysmographic signal generator with analog output.

The photoplethysmographic (PPG) signal of the finger is being used to create embedded devices that estimate physiological variables. This project outlines an innovative method for developing a synthetic PPG generator that produces both actual reference digital signals and their equivalent analog signals using open-source technology. A series of PPG profiles is synthesized using three variant Gaussian functions. A low-frequency trend induced by respiratory frequency and background noise are then added. To generate a diverse range of continuously variable PPG profiles within specified boundaries and customizable levels of interference, all parameters undergo random fluctuations on a cycle-by-cycle basis, as per user-defined constraints. The generated signal is then converted into its equivalent analog form through the use of an RC filter that low-frequency filters a Pulse-Width Modulation square wave that is modulated directly by the generated signal. The software returns different PPG profiles and allows the signal comparison before vs after the addition of different-intensity modulated respiratory trends and background noise. The digital signal is faithfully converted into an equivalent analog voltage signal capable of reproducing not only the waveform profile but also the respiratory trend and various levels of noise.

Voltage‐controlled attenuator based on PIN diode and compensated gold wire inductors

AbstractThis paper proposes an innovative design approach for a voltage‐controlled (variable) attenuator that allows continuous control of attenuation through analog voltage. Different from fixed attenuators, this work employs PIN diodes and compensated gold wire inductors to configure the attenuation network. It is based in imperfect matching theory, ensuring to obtain the acceptable S‐parameters over the operating band. Measurement results demonstrate effective performance of the attenuator within the voltage range of 0.7–1.03 V. Return losses of the attenuator are all better than 15 dB in the operating range of 10.5–19 GHz. The insertion losses exhibit continuous variation from 2 to 15 dB, requiring only a single controlled voltage to adjust the attenuation value.

A 18-bit 1-MS/s fully-differential SAR ADC with digital calibration achieving 96.1 dB SNDR

This paper presents a 18-bit 1 MS/s fully-differential Successive-Approximation-Register Analog-to-Digital Converter (SAR ADC) achieving an ENOB of 15.7-bit. To achieve higher performance, a differential DAC utilizing both split and monotonic switching timing is designed. For both dynamic and static performance improvement, five techniques are proposed. First, a foreground digital self-calibration method based on normalized-full-scale-referencing is described to eliminate the capacitor mismatch errors. L-segment capacitors are utilized to measure and calculate the bit weights of other capacitors. Second, a DNL enhancement technique is presented. The fractional capacitors are used to subtract an analog voltage from the DAC before the conversion is finished, which further improve the ADC performance. Third, an adaptive-tracking-extra-bit-trail together with comparator noise extraction and correction for further accuracy enhancement is proposed. Forth, a harmonic calibration technique, which can efficiently attenuate 2-order and 3-order harmonic is introduced. Fifth, a comparator with ultra-low noise and offset is designed to meet the 18-bit 1-MS/s ADC. The ADC is fabricated in a 0.18-μm 5-V CMOS process. It measures a 96.1 dB SNDR and a 110.7 dB SFDR. The DNL and INL are within ±0.32 LSB and ±0.5 LSB, respectively. The overall power consumption of ADC core, drawn from the 5 V power supply, is 45 mW.

Piezoelectric Behaviour in Biodegradable Carrageenan and Iron (III) Oxide Based Sensor.

This paper is dedicated to the research of phenomena noticed during tests of biodegradable carrageenan-based force and pressure sensors. Peculiar voltage characteristics were noticed during the impact tests. Therefore, the sensors' responses to impact were researched more thoroughly, defining time-dependent sensor output signals from calibrated energy impact. The research was performed using experimental methods when a free-falling steel ball impacted the sensor material to create relatively definable impact energy. The sensor's output signal, which is analogue voltage, was registered using an oscilloscope and transmitted to the PC for further analysis. The obtained results showed a very interesting outcome, where the sensor, which was intended to be piezoresistive, demonstrated a combination of behaviour typical for galvanic cells and piezoelectric material. It provides a stable DC output that is sensitive to the applied statical pressure, and in case of a sudden impact, like a hit, it demonstrates piezoelectric behaviour with some particular effects, which are described in the paper as proton transfer in the sensor-sensitive material. Such phenomena and sensor design are a matter of further development and research.

Digital horizontal crosstalk compensation in 8K LCD displays for enhanced image quality

AbstractAs ultra‐high‐definition displays have gained popularity, mitigating the horizontal crosstalk effect in 8K LCD panels is crucial. High display resolution requires narrower signal line integration, intensifying the coupling effect. Traditional methods like Vcom feedback and increasing analog voltage drain‐drain (AVDD) load are slower and less accurate, leading to increased power consumption. In response, we propose an advanced digital signal compensation method. In this study, we developed a predictive model and investigated the intricate relationships among AVDD, Vcom, and storage capacity (Cst) ripples on horizontal crosstalk. Optimizing the ripple change (∆G) by varying the compensation coefficient (a) and decay ratio (τ) significantly reduces crosstalk effects. The digital compensation method allows rapid and precise compensation without delays, reducing horizontal crosstalk in 8K LCD panels from 4% to below 0.9%. This surpasses the requirement of minimizing crosstalk to less than 2%, substantially enhancing the image quality of high‐resolution displays.

Probing the electric and thermoelectric response of ferroelectric 2H and 3R α-In2Se3

Two-dimensional van der Waals ferroelectric materials play an important role in a wide spectrum of semiconductor technologies and device applications. Integration of ferroelectrics into 2D-layered material-based devices is expected to offer intriguing working principles and add desired functionalities for next-generation electronics. Here, we investigate the electric and thermoelectric properties of thin layers of the 2H and 3R polymorphs of α-In2Se3 embedded in solid-state three-terminal devices. Charge transport measurements reveal a hysteretic behavior that can be ascribed to the effect of ferroelectric polarization at the metal electrode/2D semiconductor interfaces. The thermoelectric investigation of the same devices unveils a well-defined negative signal of the order of 100–200 μV/K in absolute value for the 2H polymorph, showing a slight modulation as a function of the gate voltage. An analogous but noisy thermoelectric voltage is measured for devices based on the 3R polymorph, where indeed a constant finite transversal offset in the 100 μV-few mV range is detected, which does not depend on the applied temperature gradient. We argue that these experimental observations are related to a strong residual in-plane ferroelectric polarization in the 3R α-In2Se3 polymorph thin layer. Our results show that the thermoelectric response is a fine probe of the ferroelectric character of 2D layered α-In2Se3.

A compact and highly integrated 128-channel FPGA-based readout electronics for nuclear imaging application

As silicon photomultiplier (SiPM) technology develops, its possible applications are being growingly expanded. However, the current technical obstacle is the signal readout from large-scale, multi-pixel SiPMs, especially in a large nuclear imaging device. Although the application-specific integrated circuits (ASICs) provide ways to reach that goal, it needs a long period with iterative electronic process and a very high cost. We developed a high-integrated positron emission tomography (PET) electronics system with field programmable gate array based charge-to-digital converter (FPGA-QDC) technology instead of the ASICs. Unlike traditional FPGA-based charge readout method in which low-voltage differential signaling (LVDS) receivers serve as analog voltage comparators, in the proposed electronics system voltage-referenced receivers work as analog comparators.Theoretically, nearly all of input/output (I/O) ports in the FPGA can achieve the function of analog comparators using voltage-referenced I/O standard. The electronics system is constructed using off-the-shelf low-cost commercial components. Therefore, it is feasible to fast build a distributed readout system with multiple such electronics system. The flexibility and reconfigurability of the FPGA provide multi-channel grouping and diverse triggering for different kinds of detector configurations, such as row/column summation and resistor-based readout. These features are greatly sought after in readout electronics for the SiPM-based radiation detectors. Experimental results show that the proposed highly-integrated electronics system overcomes the bottleneck that has limited the development of advanced PET detectors and scanners.

Generation and Storage of Random Voltage Values via Ring Oscillators Comprising Feedback Field-Effect Transistors.

In this study, we demonstrate the generation and storage of random voltage values using a ring oscillator consisting of feedback field-effect transistors (FBFETs). This innovative approach utilizes the logic-in-memory function of FBFETs to extract continuous output voltages from oscillatory cycles. The ring oscillator exhibited uniform probability distributions of 51.6% for logic 0 and 48.4% for logic 1. The generation of analog voltages provides binary random variables that are stored for over 5000 s. This demonstrates the potential of the ring oscillator in advanced physical functions and true random number generator technologies.

Investigation of sound pressure leakage effect for primary calibration down to 10−2 Hz using a laser pistonphone system

Recently, the demand for sensor calibration in the infrasonic range has increased to obtain accurate information when monitoring infrasound generated by large-scale natural disasters. The laser pistonphone method is a primary calibration method to evaluate infrasound sensors in the low-frequency range. In this method, sound pressure is generated in a fixed sealed volume of air, by a volume change via an attached piston movement. By measuring the piston displacement using laser interferometer, the generated sound pressure can be calculated by multiplying the velocity of volume change by acoustic transfer impedance of a pistonphone. The main concern with this method is that sound pressure leakage from a gap adjacent to piston significantly changes the acoustic transfer impedance at lower frequencies. To apply the laser pistonphone method in the low-frequency range down to 10−2 Hz, it is essential to accurately evaluate and compensate for the leakage effect, i.e. the gap’s acoustic transfer impedance. In this study, we propose a technique for experimentally evaluating the gap impedance. The main idea is to determine the total acoustic transfer impedance by dividing the sound pressure by the volume velocity and then deducing the gap impedance by subtracting the chamber impedance from the obtained total acoustic transfer impedance. A digital pressure sensor was used to precisely measure sound pressure below 100 Hz because pressure sensors are suitable for accurate measurement of pressure fluctuations at low frequencies. We validated the proposed approach by calibrating an analog pressure sensor that outputs an analog voltage proportional to the absolute pressure. As a result, the sensitivity calibrated by the laser pistonphone method at 0.02 Hz agreed with the static sensitivity provided by the manufacturer within 0.02 dB.

Efficient and Accurate Analog Voltage Measurement Using a Direct Sensor-to-Digital Port Interface for Microcontrollers and Field-Programmable Gate Arrays

Portable sensor systems are usually based on microcontrollers and/or Field-Programmable Gate Arrays (FPGAs) that are interfaced with sensors by means of an Analog-to-Digital converter (ADC), either integrated in the computing device or external. An alternative solution is based on the direct connection of the sensors to the digital input port of the microcontroller or FPGA. This solution is particularly interesting in the case of devices not integrating an internal ADC or featuring a small number of ADC channels. In this paper, a technique is presented to directly interface sensors with analog voltage output to the digital input port of a microcontroller or FPGA. The proposed method requires only a few passive components and is based on the measurements of the duty cycle of a digital square-wave signal. This technique was investigated by means of circuit simulations using LTSpice and was implemented in a commercial low-cost FPGA device (Gowin GW1NR-9). The duty cycle of the square-wave signal features a good linear correlation with the analog voltage to be measured. Thus, a look-up table to map the analog voltage values to the measured duty cycle is not required with benefits in terms of memory occupation. The experimental results on the FPGA device have shown that the analog voltage can be measured with a maximum accuracy of 1.09 mV and a sampling rate of 9.75 Hz. The sampling rate can be increased to 31.35 Hz and 128.31 Hz with an accuracy of 1.61 mV and 2.68 mV, respectively.

Linear Potentiometer Sensor-Based of Athlete Flexibility Measurement Tool

This study aims to develop a novel "sit and reach test" flexometer device utilizing a linear potentiometer sensor to quantitatively evaluate an individual's body flexibility. The innovation in this research lies in the utilization of electronic means to measure flexibility, replacing conventional manual methods. The device employs a linear potentiometer sensor that translates analog voltage into a digital value (ADC) and subsequently converts the digital data into distance measurements in centimeters (cm). The processed data, representing the distance measurements, is wirelessly transmitted to a personal computer (PC) for automatic capture and analysis. The design considerations prioritize modernity, practicality, effectiveness, and efficiency. The experimental outcomes demonstrate the efficacy of the developed tool. The readings from the linear potentiometer sensor exhibit a high linearity, indicated by an R2 value of 0.9999. The average error percentage is minimal, measuring at 0.17%. Moreover, the device allows for direct wireless transmission of data to a PC immediately after assessing an athlete's flexibility. This study not only introduces a novel electronic approach for assessing body flexibility but also validates its accuracy and efficiency through comprehensive testing and analysis.

Design of Phase-Locked Loop Using Special Analog Multipliers and Voltage Buffers: Demodulation of Transposed Signals From Sensors

Design of Phase-Locked Loop Using Special Analog Multipliers and Voltage Buffers: Demodulation of Transposed Signals From Sensors

Radiation tolerance of SiGe BiCMOS monolithic silicon pixel detectors without internal gain layer

A monolithic silicon pixel prototype produced for the MONOLITH ERC Advanced project was irradiated with 70 MeV protons up to a fluence of 1 × 1016 1 MeV n eq/cm2. The ASIC contains a matrix of hexagonal pixels with 100 μm pitch, readout by low-noise and very fast SiGe HBT frontend electronics. Wafers with 50 μm thick epilayer with a resistivity of 350 Ωcm were used to produce a fully depleted sensor. Laboratory tests conducted with a 90Sr source show that the detector works satisfactorily after irradiation. The signal-to-noise ratio is not seen to change up to fluence of 6 × 1014 n eq/cm2. The signal time jitter was estimated as the ratio between the voltage noise and the signal slope at threshold. At -35°C, sensor bias voltage of 200 V and frontend power consumption of 0.9 W/cm2, the time jitter of the most-probable signal amplitude was estimated to be σ t 90Sr = 21 ps for proton fluence up to 6 × 1014 n eq/cm2 and 57 ps at 1 × 1016 n eq/cm2. Increasing the sensor bias to 250 V and the analog voltage of the preamplifier from 1.8 to 2.0 V provides a time jitter of 40 ps at 1 × 1016 n eq/cm2.

DFT based atomic modeling and temperature analysis on the RF and VTC curve of high-k dielectric layer-assisted NCFET

In this report, Density Functional Theory (DFT) based calculation using a Quantum Atomistic Tool Kit (ATK) simulator is done for the hafnia-based ferroelectric material. The band structure, projected density of states (PDOS), and Hartree potential (VH) are taken into account for hafnium oxide (HfO2) and silicon-doped hafnium oxide (Si-doped HfO2). Further, we analyze the temperature variation impact on analog parameters and voltage transfer characteristic (VTC) curve of inverter application of Modified Negative Capacitance Field-Effect-Transistor (NCFET) using the Visual Technology-Computer-Aided-Design (TCAD) simulator. The Modified NCFET structure enhances the DC parameters like leakage current (IOFF) and Subthreshold Swing (SS) compared to the conventional NCFET structure. With the temperature impact, the variation in the parameters of Modified NCFET is discussed at 250 K, 275 K, 300 K, 325 K, and 350 K like transconductance (gm), output conductance (gd), early voltage (VEA) shows the increment as we move from 250 K to 350 K. The short channel effects (SCEs) like Drain Induced Barrier Lowering (DIBL) and Subthreshold Swing (SS) decrease with the temperature fall at 32.98% and 34.74%, respectively. Further, the VTC curve, Noise Margin (NM), and propagation delay of Modified NCFET-based inverter are discussed with the impact of temperature. The propagation delay for the circuit decreased by 67.94% with the rise in the temperature. These factors show that the Modified NCFET-based inverter gives a fast switching performance at high temperatures.