Voids In Interconnects Research Articles

Study of migration and coalescence of voids driven by electric current stressing in solder interconnects using phase field simulation

Voids in solder interconnects play a crucial role in influencing performance and reliability of solder interconnects, and even lead to the open failure of electronics, especially when high density electric current flowing through the solder interconnects. In this paper, the morphological evolution and migration behaviour of the voids in the solder domain of solder interconnects under electric current stressing is investigated using a developed phase field model. Results show that the surface energy drives the coalescence of voids, and large size voids grow up at the expense of small size ones. The voids migrate along the electric current direction, and the current density distribution and void distribution interactively affect the evolution and migration of the voids. The high magnitude of electric field can potentially induce the open-circuit failure, and the void size is affected by the electric field. Moreover, the voltage across the solder domain increases as the voids migrate to the cathode side. Furthermore, the electric field can promote the void coarsening, and the void migration velocity increases almost linearly with the magnitude of the electric field.

Phase field simulation of healing and growth of voids in interconnects under electric field-induced interface migration

The micro-damage such as voids, inclusions, or cracks in interconnects of integrated circuits (IC) will evolve dramatically under different mass flow transport mechanisms driven by a variety of external physical fields, which will lead to the decrease of the reliability of the interconnects and the occurrence of failure in severe cases. Based on the microstructure evolution theory of solid materials, a phase field model under the mechanism of electric field-induced interface migration is constructed in this paper. The compatibility between the phase field model and the sharp interface model is proved by the asymptotic analysis. The modified theoretical solution of two-dimensional intragranular void in interconnects is derived, and the reliability of the finite element algorithm is verified by checking with the numerical results. Numerical simulation is carried out to discuss the effects of the electric field intensity χ, the initial morphological ratio β0, and the free energy density difference between the vapor-solid phase Δg˜ on the morphological evolution of the void. The results indicate that the external electric field drives the void to drift in the direction of the electric field, which is widely known as electromigration, and the morphology of the void becomes cylindrization gradually under the action of interface energy. With the increase of the external electric field, there are three morphological evolution trends of the void, including growth, equilibrium, and healing. The electric field critical value χcr, representing the equilibrium state of the void, is used to distinguish different evolution trends. The increase of β0 or the decrease of Δg˜ will lead to the acceleration of void drift velocity, the delay of cylindrization time, and the decrease of critical value, which aggravates the reliability problem of interconnects. Therefore, we should focus on the control of parameters such as χ, β0, and Δg˜, so that the current density of the interconnects is under the condition of χ<χcr. It can cause the intragranular void to shrink and even heal, effectively improving the reliability of IC and prolonging its service life.

Analysis of a Multiple Supply Voltage Floorplan Considering Voltage Drop and Electron Migration Risk

In Contemporary Integrated Circuits (IC), the Voltage drop in the power rails and Electron migration risk (EM) due to high current densities are the most important factors degrading the reliability of the chip. The effect of these factors leads to an imbalance in the flow of charge carriers and voids in interconnects. This paper resolves the above issues, through analyzing and predetermining it in a Multiple Supply Voltage (MSV) design during the floorplanning stage. Simulations were carried out in Cadence digital Encounter system with 180nm technology for the circuit net list of 8 point FFT (Fast Fourier Transform) and FIR filter. Results show that floorplanning scheme is powerful in reducing 100% of voltage drop and 50% of EM risk in the chip as compared to previous works.

Effects of voids on thermal-mechanical reliability of lead-free solder joints

Reliability of electronic packages has become a major issue, particularly in systems used in electrical or hybrid cars where severe operating conditions must be met. Many studies have shown that solder interconnects are critical elements since many failure mechanisms originate from their typical response under thermal cycles. In this study, effects of voids in solder interconnects on the electronic assembly lifetime are estimated based on finite element simulations.

Growth Mechanism and Prevention Measure of Stress-Induced Voids in Copper Interconnects

Growth Mechanism and Prevention Measure of Stress-Induced Voids in Copper Interconnects

A three-dimensional model of electromigration and stress induced void nucleation in interconnect structures

A three-dimensional finite element method is developed to predict the critical conditions necessary to nucleate electromigration or stress induced voids in interconnects. Our approach is to model interfaces using a modified cohesive zone, which permits the interfaces to separate at a critical stress, and also accounts for mass transport along the interfaces. A simple boundary value problem is solved to verify the numerical procedure. The method is then used to simulate the nucleation and initial growth of voids in a realistic interconnect test structure. Predicted void nucleation sites are in good agreement with experimental observations. In addition, modeling analysis is also consistent with qualitative effects of geometric and material parameters such as the line length, cap layer and passivation material on critical times to nucleate voids.

A finite element model of electromigration induced void nucleation, growth and evolution in interconnects

We describe a two-dimensional finite element method designed to model the nucleation, growth and evolution of voids in polycrystalline interconnects. Our computations extend earlier models by accounting in detail for the effects of grain boundaries and interfaces in the solid. In particular, the model includes the effects grain boundary sliding, grain boundary diffusion, grain boundary migration and surface diffusion, as well as elastic deformation and electric current flow within the grains themselves. Front tracking and adaptive mesh generation are used to follow changes in the grain structure and void shape. The method is used to solve representative boundary value problems to illustrate its capabilities.

Mini-Workshop: Anisotropic Motion Laws

Anisotropic motion laws play a key role in many applications ranging from materials science, biophysics to image processing. All these highly diversified disciplines have made it necessary to develop common math- ematical foundations and framworks to deal with anisotropy in geometric motion. The workshop brings together leading experts from various fields to address well-posedness, accuracy, and computational efficiency of the math- ematical models and algorithms.

Current-driven interactions between voids in metallic interconnect lines and their effects on line electrical resistance

We present a theoretical analysis based on self-consistent numerical simulations of current-driven interactions between voids in metallic thin-film interconnects and the resulting void migration, morphological evolution, and coalescence phenomena. The analysis reveals the complex nature of electromigration-induced void-void interactions, and their implications for the evolution of interconnect line electrical resistance. Most importantly, it is demonstrated that current-driven void-void interaction effects, such as void coalescence, can cause sudden changes in the interconnect line electrical resistance, in qualitative agreement with observations in accelerated electromigration testing experiments.

Imaging and analysis of subsurface Cu interconnects by detecting backscattered electrons in the scanning electron microscope

Cu – Si O 2 – Si N x interconnects that were located 0.65–2.7-μm below the surface of silicon-integrated circuits were imaged in a scanning electron microscope and a transmission electron microscope with a scanning attachment by detecting backscattered electrons (BSEs) with an incident electron-beam energy (Eo) in the range of 30–400keV. BSE images could be used to detect voids in subsurface Cu interconnects, even in regions covered with upper level Cu lines or vias. As Eo was increased from 30to400keV, structures could be seen as a result of atomic number (Z) contrast farther below the surface while structures closer to the surface had reduced Z contrast. The subsurface beam diameter was measured from BSE images as a function of Eo and depth below the surface. For all Eo, the subsurface beam diameter initially rapidly increased with SiO2 overlayer thickness but, for 150keV, a leveling off in the beam spread was seen for depths &amp;gt;1.7μm. Beam broadening affected whether the TaN∕Ta liners that surrounded the Cu conductors could be seen at the edges of the lines; this contrast was observed only when the subsurface beam diameter was ⩽1.5× the liner thickness. The BSE information depth for imaging 0.2-μm-sized voids in subsurface Cu–SiO2–SiNx interconnect structures at 30 and 150keV was estimated to be 0.65 and 3μm, respectively.

Physical failure analysis in semiconductor industry—challenges of the copper interconnect process

Since the copper interconnect dimensions shrunk continuously, physical failure analysis becomes increasingly important for process optimization. Failure localization and defect analysis in interconnect structures as well as analysis of barrier/seed step coverage are challenges of the copper inlaid technology. Failure localization in via chain test structures using voltage contrast analysis with SEM/FIB tools and OBIRCH and subsequent destructive failure analysis using FIB/SEM and TEM are described. The inspections of voids in copper interconnects and of buried residuals in vias are typical tasks for process monitoring, which make the application of leading-edge analytical techniques necessary. Barrier/seed step coverage analysis at via chains challenges both TEM sample preparation and analysis. 3D object reconstruction by electron tomography is a promising future method for this task.

Voiding induced stress redistribution and its reliability implications in metal interconnects

The evolution of stress affected by the formation of voids in metal interconnects is studied numerically. The objective is to examine how thermal stresses redistribute in response to voiding, rather than how voids form in response to stress, for gaining insights into the physics of reliability in integrated circuit devices. The finite element method is employed to model the thermal and voiding histories of the interconnect structure. Voiding is simulated by removing relevant material elements in the metal. Bulky and slit-like voids of various sizes are considered. The stress relaxation due to voiding is found to be a local phenomenon, bearing no direct relation with the global thermomechanical conditions of the interconnect. The concept of the saturation void fraction thus needs to be revisited. The stress gradient along the line on both sides of the void is found to be essentially constant for the various void shapes and sizes considered. This has implications on the resolution limit of micro-diffraction techniques needed for sensing the existence of voids. The resulting stress field is also used as the initial condition in modeling the electromigration flux divergence by employing the finite difference method. A mechanistic understanding of electromigration voiding due to the presence of locally debonded slits is established. The debond-induced stress gradient is found to cause back atomic flow, leading to local flux divergence. The flux divergence, and thus the voiding propensity, increases with an increasing size of the debond. The same approach is also used to study if a pre-existing stress-void can grow into an electromigration void. A simple correlation, which appears to rationalize experimental observations, is identified: a large stress-void is more prone to growth during subsequent electromigration. The validity of applying the critical stress concept in characterizing electromigration failure is discussed.

Void nucleation on intentionally added defects in Al interconnects

Void nucleation in passivated aluminum interconnects was studied using high voltage scanning electron microscopy. To test theories about stress-induced and electromigration void nucleation, Ar ions were implanted into Al specimens. The Ar atoms precipitated and formed bubbles that served as nucleation sites with high surface energy. In the implanted samples, voids formed away from the interconnect sidewalls, in contrast to voids in ordinary passivated Al interconnects. The evolution of the void volume was also affected by the reduction in the nucleation barrier. These results strongly support the theory of void nucleation on interface flaws in Al interconnects.

The Spreading of a Void on a Facet During Electromigration

ABSTRACTA void of cross sectional area A may spread perpendicular to the applied electric field Ea during electromigration because its leading surface develops a facet whose advance is limited by the supply of steps. If the facet is immobile (no step source) and the remaining surface is free to move, and if EaA is less than a threshold value, then the void assumes a stationary elongated shape dictated by a balance between capillarity and electric field. If EaA exceeds the threshold value, however, a balance is no longer possible, and the void spreads along the facet without arrest. If the facet has limited mobility, a balance is possible for all values of EaA, resulting in an elongated moving steady-state shape. The treatment simplifies the void shape as rectangular but preserves the essential features of capillarity and surface electromigration. We argue that the motion of a facet on a void along the outward normal requires defects (e.g. intersecting screw dislocations) that act as step sources since homogeneous nucleation of steps on the facet is expected to be negligible. Since voids in fine-line interconnects are often observed to be partially faceted, restricted void motion and resultant spreading which depend sensitively on crystallographic features, such as defect structure and grain orientation, may indeed limit the lifetime of fine-line interconnects in electronic devices.

Microscopic Estimates for Electromigration Velocities of Intragranular Voids in Thin Aluminum Lines

AbstractWe explore the effect of faceting on possible mechanisms for mass transport around electromigration voids in aluminum interconnects. Motivated by linear response estimates which suggest that particle flux would be much higher along steps than across terraces on a clean aluminum surface, we study step nucleation in the presence of a small driving force along a surface. We find that step nucleation, even on a nearly defect-free void surface, would be slow if the step energy is equal to that calculated for a clean aluminum surface. In the presence of a uniform electromigration force, the creation of new steps between existing ones should not occur unless the free energy cost of a step is much less than thermal energies. We conclude that voids cannot move intragranularly at μm/hr rates without help from other factors such as local heating and impurities.

Atomistic simulation of void nucleation in aluminium lines

Abstract The formation of voids in aluminium interconnects in integrated circuits was studied atomistically with emphasis on nucleation. Input computational cells included different levels of concentrations of vacancies and stresses together with the typically observed structural defects (grain boundaries and dislocations) in metal lines. The input cells were relaxed using Monte Carlo (atom transpose) and static energy minimization (strain relaxation) techniques concurrently. Besides agglomeration of vacancies in unstrained crystals, the formation of vacancies in crystals under tension was found to be a main contributor to void nucleation. Climb and glide of dislocations were observed atomistically during the formation of voids. Compressive stresses in the metal lines, on the other hand, prevented the formation of voids.

Stress induced voids in aluminum interconnects during IC processing : J. T. Yue, W. P. Funsten and R. V. Taylor. 23 a. Proc. Reliab. Phys. Symp. 126 (1985)

Stress induced voids in aluminum interconnects during IC processing : J. T. Yue, W. P. Funsten and R. V. Taylor. 23 a. Proc. Reliab. Phys. Symp. 126 (1985)